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Merge pull request #2588 from fpistm/stm32cubeU0_update
chore(u0): update to latest STM32CubeU0 v1.2.0
2 parents 2ae138f + f671ecf commit d7b460f

34 files changed

+340
-174
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -706,6 +706,10 @@ typedef struct
706706
#define UID_BASE (0x1FFF3E50UL) /*!< Unique device ID register base address */
707707
#define FLASHSIZE_BASE (0x1FFF3EA0UL) /*!< Flash size data register base address */
708708

709+
/*!< Bootloader Firmware */
710+
/************ Bootloader Exit Secure Memory Firmware *************/
711+
#define BL_EXIT_SEC_MEM_BASE (0x1FFF3500UL)
712+
709713
/**
710714
* @}
711715
*/

‎system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u073xx.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -775,6 +775,10 @@ typedef struct
775775
#define UID_BASE (0x1FFF6E50UL) /*!< Unique device ID register base address */
776776
#define FLASHSIZE_BASE (0x1FFF6EA0UL) /*!< Flash size data register base address */
777777

778+
/*!< Bootloader Firmware */
779+
/************ Bootloader Exit Secure Memory Firmware *************/
780+
#define BL_EXIT_SEC_MEM_BASE (0x1FFF6000UL)
781+
778782
/**
779783
* @}
780784
*/

‎system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u083xx.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -809,6 +809,10 @@ typedef struct
809809
#define UID_BASE (0x1FFF6E50UL) /*!< Unique device ID register base address */
810810
#define FLASHSIZE_BASE (0x1FFF6EA0UL) /*!< Flash size data register base address */
811811

812+
/*!< Bootloader Firmware */
813+
/************ Bootloader Exit Secure Memory Firmware *************/
814+
#define BL_EXIT_SEC_MEM_BASE (0x1FFF6000UL)
815+
812816
/**
813817
* @}
814818
*/

‎system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u0xx.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@
88
* is using in the C source code, usually in main.c. This file contains:
99
* - Configuration section that allows to select:
1010
* - The STM32U0xx device used in the target application
11-
* - To use or not the peripheral’s drivers in application code(i.e.
12-
* code will be based on direct access to peripheral’s registers
11+
* - To use or not the peripheral's drivers in application code(i.e.
12+
* code will be based on direct access to peripheral's registers
1313
* rather than drivers API), this option is controlled by
1414
* "#define USE_HAL_DRIVER"
1515
*
@@ -76,10 +76,10 @@
7676
#endif /* USE_HAL_DRIVER */
7777

7878
/**
79-
* @brief CMSIS Device version number 1.0.0
79+
* @brief CMSIS Device version number 1.2.0
8080
*/
8181
#define __STM32U0_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
82-
#define __STM32U0_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
82+
#define __STM32U0_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
8383
#define __STM32U0_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
8484
#define __STM32U0_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
8585
#define __STM32U0_CMSIS_VERSION ((__STM32U0_CMSIS_VERSION_MAIN << 24)\
@@ -127,8 +127,8 @@ typedef enum
127127

128128
typedef enum
129129
{
130-
ERROR = 0,
131-
SUCCESS = !ERROR
130+
SUCCESS = 0,
131+
ERROR = !SUCCESS
132132
} ErrorStatus;
133133

134134
/**

‎system/Drivers/CMSIS/Device/ST/STM32U0xx/Release_Notes.html

Lines changed: 19 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -30,27 +30,42 @@ <h1 id="release-notes-for-stm32u0xx-cmsis">Release Notes for <mark> STM32U0xx C
3030
<div class="col-sm-12 col-lg-8">
3131
<h1 id="update-history"><strong>Update History</strong></h1>
3232
<div class="collapse">
33-
<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 05-June-2024</strong></label>
33+
<input type="checkbox" id="collapse-section3" checked aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 30-October-2024</strong></label>
3434
<div>
3535
<h2 id="main-changes">Main Changes</h2>
3636
<ul>
3737
<li><strong>CMSIS Device</strong> Maintenance Release version of bits and registers definition aligned with the <strong>RM0503</strong> (STM32U0 reference manual).
3838
<ul>
39+
<li>Fixed the right CFGR_HPRE shift in the SystemCoreClockUpdate API.</li>
40+
<li>Align the ErrorStatus typedef declaration with HAL_StatusTypeDef.</li>
41+
<li>Add the address to use for the bootloader jump service.</li>
42+
</ul></li>
43+
</ul>
44+
<h1 id="section"></h1>
45+
</div>
46+
</div>
47+
<div class="collapse">
48+
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 05-June-2024</strong></label>
49+
<div>
50+
<h2 id="main-changes-1">Main Changes</h2>
51+
<ul>
52+
<li><strong>CMSIS Device</strong> Maintenance Release version of bits and registers definition aligned with the <strong>RM0503</strong> (STM32U0 reference manual).
53+
<ul>
3954
<li>Add I2C_CR1_SBC bit definition.</li>
4055
<li>Removed the I2C_CR1_SWRST bit definition.</li>
4156
</ul></li>
4257
</ul>
43-
<h1 id="section"></h1>
58+
<h1 id="section-1"></h1>
4459
</div>
4560
</div>
4661
<div class="collapse">
4762
<input type="checkbox" id="collapse-section1" ria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 12-February-2024</strong></label>
4863
<div>
49-
<h2 id="main-changes-1">Main Changes</h2>
64+
<h2 id="main-changes-2">Main Changes</h2>
5065
<ul>
5166
<li>First official release version of bits and registers definition aligned with the <strong>RM0503</strong> (STM32U0 reference manual).</li>
5267
</ul>
53-
<h1 id="section-1"></h1>
68+
<h1 id="section-2"></h1>
5469
</div>
5570
</div>
5671
</div>

‎system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -327,7 +327,7 @@ void SystemCoreClockUpdate(void)
327327
}
328328
/* Compute HCLK clock frequency --------------------------------------------*/
329329
/* Get HCLK prescaler */
330-
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U) & 0xFU];
330+
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos) & 0xFU];
331331
/* HCLK clock frequency */
332332
SystemCoreClock >>= tmp;
333333
}

‎system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
* STM32L4: 1.7.4
1717
* STM32L5: 1.0.6
1818
* STM32MP1: 1.6.0
19-
* STM32U0: 1.0.0
19+
* STM32U0: 1.2.0
2020
* STM32U5: 1.4.0
2121
* STM32WB: 1.12.2
2222
* STM32WBA: 1.4.0

‎system/Drivers/STM32U0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

Lines changed: 53 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -472,7 +472,9 @@ extern "C" {
472472
#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
473473
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
474474
#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
475+
#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5)
475476
#define PAGESIZE FLASH_PAGE_SIZE
477+
#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */
476478
#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
477479
#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
478480
#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
@@ -601,6 +603,15 @@ extern "C" {
601603
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
602604
#endif /* STM32G4 */
603605

606+
#if defined(STM32U5)
607+
608+
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster
609+
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster
610+
#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection
611+
#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection
612+
613+
#endif /* STM32U5 */
614+
604615
#if defined(STM32H5)
605616
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
606617
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
@@ -875,6 +886,10 @@ extern "C" {
875886
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
876887
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
877888

889+
#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7)
890+
#define HRTIMInterruptResquests HRTIMInterruptRequests
891+
#endif /* STM32F3 || STM32G4 || STM32H7 */
892+
878893
#if defined(STM32G4)
879894
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
880895
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
@@ -1012,8 +1027,8 @@ extern "C" {
10121027
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
10131028
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
10141029
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
1015-
10161030
#endif /* STM32F3 */
1031+
10171032
/**
10181033
* @}
10191034
*/
@@ -1264,10 +1279,10 @@ extern "C" {
12641279
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
12651280
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
12661281

1267-
#if defined(STM32H5) || defined(STM32H7RS)
1282+
#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
12681283
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
12691284
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
1270-
#endif /* STM32H5 || STM32H7RS */
1285+
#endif /* STM32H5 || STM32H7RS || STM32N6 */
12711286

12721287
#if defined(STM32WBA)
12731288
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
@@ -1279,10 +1294,10 @@ extern "C" {
12791294
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
12801295
#endif /* STM32WBA */
12811296

1282-
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
1297+
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
12831298
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
12841299
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
1285-
#endif /* STM32H5 || STM32WBA || STM32H7RS */
1300+
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
12861301

12871302
#if defined(STM32F7)
12881303
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
@@ -1466,7 +1481,7 @@ extern "C" {
14661481
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
14671482
#endif
14681483

1469-
#if defined(STM32U5) || defined(STM32MP2)
1484+
#if defined(STM32U5)
14701485
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
14711486
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
14721487
#endif
@@ -2014,12 +2029,12 @@ extern "C" {
20142029
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
20152030
* @{
20162031
*/
2017-
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
2032+
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
20182033
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
20192034
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
20202035
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
20212036
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
2022-
#endif /* STM32H5 || STM32WBA || STM32H7RS */
2037+
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
20232038

20242039
/**
20252040
* @}
@@ -3680,7 +3695,7 @@ extern "C" {
36803695
#endif
36813696

36823697
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
3683-
defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
3698+
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0)
36843699
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
36853700
#else
36863701
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3931,7 +3946,8 @@ extern "C" {
39313946
*/
39323947
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
39333948
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
3934-
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
3949+
defined (STM32WBA) || defined (STM32V7) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \
3950+
defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
39353951
#else
39363952
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
39373953
#endif
@@ -4225,6 +4241,33 @@ extern "C" {
42254241

42264242
#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
42274243
#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
4244+
#if defined(STM32U5)
4245+
#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD
4246+
#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK
4247+
#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC
4248+
#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST
4249+
#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF
4250+
#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT
4251+
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM
4252+
#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM
4253+
#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK
4254+
#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ
4255+
#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT
4256+
#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0
4257+
#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1
4258+
#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM
4259+
#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG
4260+
#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM
4261+
#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM
4262+
#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT
4263+
#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM
4264+
#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM
4265+
#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID
4266+
#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0
4267+
#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1
4268+
#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
4269+
#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
4270+
#endif
42284271
/**
42294272
* @}
42304273
*/

‎system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -462,6 +462,14 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
462462
#define PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND
463463
#define PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND
464464

465+
/**
466+
* @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
467+
* @param USBx USB peripheral instance register address.
468+
* @param bEpNum Endpoint Number.
469+
* @retval None
470+
*/
471+
#define PCD_SET_OUT_STATUS USB_DRD_SET_CHEP_KIND
472+
#define PCD_CLEAR_OUT_STATUS USB_DRD_CLEAR_CHEP_KIND
465473

466474
/**
467475
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.

‎system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd_ex.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,6 @@ extern "C" {
4747
*/
4848

4949

50-
5150
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
5251
uint16_t ep_kind, uint32_t pmaadress);
5352

‎system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rcc.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -619,7 +619,7 @@ typedef struct
619619
*/
620620
/* Flags in the CR register */
621621
#define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)) /*!< MSI Ready flag */
622-
#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIDY_Pos)) /*!< HSI Ready flag */
622+
#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */
623623
#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */
624624
#define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL Ready flag */
625625

‎system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_usb.h

Lines changed: 18 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -53,26 +53,26 @@ typedef enum
5353
*/
5454
typedef struct
5555
{
56-
uint32_t dev_endpoints; /*!< Device Endpoints number.
56+
uint8_t dev_endpoints; /*!< Device Endpoints number.
5757
This parameter depends on the used USB core.
5858
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
5959

60-
uint32_t speed; /*!< USB Core speed.
61-
This parameter can be any value of @ref PCD_Speed/HCD_Speed
62-
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
60+
uint8_t speed; /*!< USB Core speed.
61+
This parameter can be any value of @ref PCD_Speed/HCD_Speed
62+
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
6363

64-
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
64+
uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
6565

66-
uint32_t phy_itface; /*!< Select the used PHY interface.
67-
This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
66+
uint8_t phy_itface; /*!< Select the used PHY interface.
67+
This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
6868

69-
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
69+
uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
7070

71-
uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */
71+
uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */
7272

73-
uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
73+
uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */
7474

75-
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
75+
uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */
7676
} USB_CfgTypeDef;
7777

7878
typedef struct
@@ -526,20 +526,17 @@ typedef USB_EPTypeDef USB_DRD_EPTypeDef;
526526
\
527527
(pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \
528528
\
529-
if ((wCount) > 62U) \
529+
if ((wCount) == 0U) \
530530
{ \
531-
USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
531+
(pdwReg) |= USB_CNTRX_BLSIZE; \
532+
} \
533+
else if ((wCount) <= 62U) \
534+
{ \
535+
USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
532536
} \
533537
else \
534538
{ \
535-
if ((wCount) == 0U) \
536-
{ \
537-
(pdwReg) |= USB_CNTRX_BLSIZE; \
538-
} \
539-
else \
540-
{ \
541-
USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
542-
} \
539+
USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
543540
} \
544541
} while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */
545542

‎system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_utils.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -294,6 +294,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS
294294
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
295295
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
296296
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
297+
ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
297298

298299
/**
299300
* @}

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