diff --git a/README.md b/README.md
index 5d7d776bfe..efe4509790 100644
--- a/README.md
+++ b/README.md
@@ -91,6 +91,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32F412ZG | [Nucleo F412ZG](http://www.st.com/en/evaluation-tools/nucleo-f412zg.html) | *2.6.0* | |
| :green_heart: | STM32F413ZH | [Nucleo F413ZH](http://www.st.com/en/evaluation-tools/nucleo-f413zh.html) | *2.4.0* | |
| :green_heart: | STM32F429ZI | [Nucleo F429ZI](http://www.st.com/en/evaluation-tools/nucleo-f429zi.html) | *0.1.0* | |
+| :yellow_heart: | STM32F446ZE | [Nucleo F446ZE](http://www.st.com/en/evaluation-tools/nucleo-f446ze.html) | **2.7.0** | |
| :green_heart: | STM32F722ZE | [Nucleo F722ZE](http://www.st.com/en/evaluation-tools/nucleo-f722ze.html) | *2.4.0* | |
| :green_heart: | STM32F767ZI | [Nucleo F767ZI](http://www.st.com/en/evaluation-tools/nucleo-f767zi.html) | *1.4.0* | |
| :green_heart: | STM32F746ZG | [Nucleo F746ZG](https://www.st.com/en/evaluation-tools/nucleo-f746zg.html) | *1.9.0* | |
@@ -368,6 +369,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32F437ZG<br>STM32F437ZI | Generic Board | **2.0.0** |
| :green_heart: | STM32F439ZG<br>STM32F439ZI | Generic Board | **2.0.0** |
| :green_heart: | STM32F446RC<br>STM32F446RE | Generic Board | *1.9.0* | |
+| :yellow_heart: | STM32F446ZC<br>STM32F446ZE | Generic Board | **2.7.0** | |
| :green_heart: | STM32F446VC<br>STM32F446VE | Generic Board | **2.0.0** |
| :green_heart: | STM32F411CE | [ThunderPack v1.1+](https://github.com/jgillick/ThunderPack) | *1.9.0* | |
diff --git a/boards.txt b/boards.txt
index 6e9b145ce5..e0206e16c9 100644
--- a/boards.txt
+++ b/boards.txt
@@ -76,6 +76,19 @@ Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.series=STM32F4xx
Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.product_line=STM32F429xx
Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.variant=STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)
+# NUCLEO_F446RE board
+Nucleo_144.menu.pnum.NUCLEO_F446ZE=Nucleo F446ZE
+Nucleo_144.menu.pnum.NUCLEO_F446ZE.node=NODE_F446ZE
+Nucleo_144.menu.pnum.NUCLEO_F446ZE.upload.maximum_size=524288
+Nucleo_144.menu.pnum.NUCLEO_F446ZE.upload.maximum_data_size=131072
+Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.mcu=cortex-m4
+Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.fpu=-mfpu=fpv4-sp-d16
+Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.float-abi=-mfloat-abi=hard
+Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.board=NUCLEO_F446ZE
+Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.series=STM32F4xx
+Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.product_line=STM32F446xx
+Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.variant=STM32F4xx/F446Z(C-E)(H-J-T)
+
# NUCLEO_F722ZE board
Nucleo_144.menu.pnum.NUCLEO_F722ZE=Nucleo F722ZE
Nucleo_144.menu.pnum.NUCLEO_F722ZE.node=NODE_F722ZE
@@ -4451,6 +4464,54 @@ GenF4.menu.pnum.GENERIC_F446VETX.build.board=GENERIC_F446VETX
GenF4.menu.pnum.GENERIC_F446VETX.build.product_line=STM32F446xx
GenF4.menu.pnum.GENERIC_F446VETX.build.variant=STM32F4xx/F446V(C-E)T
+# Generic F446ZCHx
+GenF4.menu.pnum.GENERIC_F446ZCHX=Generic F446ZCHx
+GenF4.menu.pnum.GENERIC_F446ZCHX.upload.maximum_size=262144
+GenF4.menu.pnum.GENERIC_F446ZCHX.upload.maximum_data_size=131072
+GenF4.menu.pnum.GENERIC_F446ZCHX.build.board=GENERIC_F446ZCHX
+GenF4.menu.pnum.GENERIC_F446ZCHX.build.product_line=STM32F446xx
+GenF4.menu.pnum.GENERIC_F446ZCHX.build.variant=STM32F4xx/F446Z(C-E)(H-J-T)
+
+# Generic F446ZCJx
+GenF4.menu.pnum.GENERIC_F446ZCJX=Generic F446ZCJx
+GenF4.menu.pnum.GENERIC_F446ZCJX.upload.maximum_size=262144
+GenF4.menu.pnum.GENERIC_F446ZCJX.upload.maximum_data_size=131072
+GenF4.menu.pnum.GENERIC_F446ZCJX.build.board=GENERIC_F446ZCJX
+GenF4.menu.pnum.GENERIC_F446ZCJX.build.product_line=STM32F446xx
+GenF4.menu.pnum.GENERIC_F446ZCJX.build.variant=STM32F4xx/F446Z(C-E)(H-J-T)
+
+# Generic F446ZCTx
+GenF4.menu.pnum.GENERIC_F446ZCTX=Generic F446ZCTx
+GenF4.menu.pnum.GENERIC_F446ZCTX.upload.maximum_size=262144
+GenF4.menu.pnum.GENERIC_F446ZCTX.upload.maximum_data_size=131072
+GenF4.menu.pnum.GENERIC_F446ZCTX.build.board=GENERIC_F446ZCTX
+GenF4.menu.pnum.GENERIC_F446ZCTX.build.product_line=STM32F446xx
+GenF4.menu.pnum.GENERIC_F446ZCTX.build.variant=STM32F4xx/F446Z(C-E)(H-J-T)
+
+# Generic F446ZEHx
+GenF4.menu.pnum.GENERIC_F446ZEHX=Generic F446ZEHx
+GenF4.menu.pnum.GENERIC_F446ZEHX.upload.maximum_size=524288
+GenF4.menu.pnum.GENERIC_F446ZEHX.upload.maximum_data_size=131072
+GenF4.menu.pnum.GENERIC_F446ZEHX.build.board=GENERIC_F446ZEHX
+GenF4.menu.pnum.GENERIC_F446ZEHX.build.product_line=STM32F446xx
+GenF4.menu.pnum.GENERIC_F446ZEHX.build.variant=STM32F4xx/F446Z(C-E)(H-J-T)
+
+# Generic F446ZEJx
+GenF4.menu.pnum.GENERIC_F446ZEJX=Generic F446ZEJx
+GenF4.menu.pnum.GENERIC_F446ZEJX.upload.maximum_size=524288
+GenF4.menu.pnum.GENERIC_F446ZEJX.upload.maximum_data_size=131072
+GenF4.menu.pnum.GENERIC_F446ZEJX.build.board=GENERIC_F446ZEJX
+GenF4.menu.pnum.GENERIC_F446ZEJX.build.product_line=STM32F446xx
+GenF4.menu.pnum.GENERIC_F446ZEJX.build.variant=STM32F4xx/F446Z(C-E)(H-J-T)
+
+# Generic F446ZETx
+GenF4.menu.pnum.GENERIC_F446ZETX=Generic F446ZETx
+GenF4.menu.pnum.GENERIC_F446ZETX.upload.maximum_size=524288
+GenF4.menu.pnum.GENERIC_F446ZETX.upload.maximum_data_size=131072
+GenF4.menu.pnum.GENERIC_F446ZETX.build.board=GENERIC_F446ZETX
+GenF4.menu.pnum.GENERIC_F446ZETX.build.product_line=STM32F446xx
+GenF4.menu.pnum.GENERIC_F446ZETX.build.variant=STM32F4xx/F446Z(C-E)(H-J-T)
+
# Upload menu
GenF4.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD)
GenF4.menu.upload_method.swdMethod.upload.protocol=0
diff --git a/variants/STM32F4xx/F446Z(C-E)(H-J-T)/generic_clock.c b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/generic_clock.c
index fa2bd0fb33..955a0053b5 100644
--- a/variants/STM32F4xx/F446Z(C-E)(H-J-T)/generic_clock.c
+++ b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/generic_clock.c
@@ -22,8 +22,58 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 8;
+ RCC_OscInitStruct.PLL.PLLN = 180;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 8;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+ /** Activate the Over-Drive mode
+ */
+ if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+ Error_Handler();
+ }
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLRCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ Error_Handler();
+ }
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.PLLSAI.PLLSAIM = 16;
+ PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
+ PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2;
+ PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4;
+ PeriphClkInitStruct.PLLSAIDivQ = 1;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
+ PeriphClkInitStruct.SdioClockSelection = RCC_SDIOCLKSOURCE_CLK48;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32F4xx/F446Z(C-E)(H-J-T)/ldscript.ld b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/ldscript.ld
new file mode 100644
index 0000000000..e1c9c38967
--- /dev/null
+++ b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32F446ZETx Device from STM32F4 series
+** 512Kbytes FLASH
+** 128Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2023 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32F4xx/F446Z(C-E)(H-J-T)/variant_NUCLEO_F446ZE.cpp b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/variant_NUCLEO_F446ZE.cpp
new file mode 100644
index 0000000000..743437e092
--- /dev/null
+++ b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/variant_NUCLEO_F446ZE.cpp
@@ -0,0 +1,245 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2023, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_NUCLEO_F446ZE)
+
+#include "pins_arduino.h"
+
+// Pin number
+const PinName digitalPin[] = {
+ PG_9, //D0
+ PG_14, //D1
+ PF_15, //D2
+ PE_13, //D3
+ PF_14, //D4
+ PE_11, //D5
+ PE_9, //D6
+ PF_13, //D7
+ PF_12, //D8
+ PD_15, //D9
+ PD_14, //D10
+ PA_7, //D11
+ PA_6, //D12
+ PA_5, //D13
+ PB_9, //D14
+ PB_8, //D15
+ PC_6, //D16
+ PB_15, //D17
+ PB_13, //D18
+ PB_12, //D19
+ PA_15, //D20
+ PC_7, //D21
+ PB_5, //D22
+ PB_3, //D23
+ PA_4, //D24
+ PB_4, //D25
+ PB_6, //D26
+ PB_2, //D27
+ PD_13, //D28
+ PD_12, //D29
+ PD_11, //D30
+ PE_2, //D31
+ PA_0, //D32
+ PB_0, //D33/A23 - LED_GREEN
+ PE_0, //D34
+ PB_11, //D35
+ PB_10, //D36
+ PE_15, //D37
+ PE_14, //D38
+ PE_12, //D39
+ PE_10, //D40
+ PE_7, //D41
+ PE_8, //D42
+ PC_8, //D43
+ PC_9, //D44
+ PC_10, //D45
+ PC_11, //D46
+ PC_12, //D47
+ PD_2, //D48
+ PG_2, //D49
+ PG_3, //D50
+ PD_7, //D51
+ PD_6, //D52
+ PD_5, //D53
+ PD_4, //D54
+ PD_3, //D55
+ PE_2, //D56
+ PE_4, //D57
+ PE_5, //D58
+ PE_6, //D59
+ PE_3, //D60
+ PF_8, //D61
+ PF_7, //D62
+ PF_9, //D63
+ PG_1, //D64
+ PG_0, //D65
+ PD_1, //D66
+ PD_0, //D67
+ PF_0, //D68
+ PF_1, //D69
+ PF_2, //D70
+ NC, //D71
+ NC, //D72
+ PB_7, //D73 - LED_BLUE
+ PB_14, //D74 - LED_RED
+ PC_13, //D75 - USER_BTN
+ PD_9, //D76 - Serial Rx
+ PD_8, //D77 - Serial Tx
+ PA_3, //D78/A0
+ PC_0, //D79/A1
+ PC_3, //D80/A2
+ PF_3, //D81/A3
+ PF_5, //D82/A4
+ PF_10, //D83/A5
+ PB_1, //D84/A6
+ PC_2, //D85/A7
+ PF_4, //D86/A8
+ PF_6, //D87/A9
+ PA_1, //D88/A18
+ PA_2, //D89/A19
+ PA_8, //D90
+ PA_9, //D91
+ PA_10, //D92
+ PA_11, //D93
+ PA_12, //D94
+ PA_13, //D95
+ PA_14, //D96
+ PC_1, //D97/A20
+ PC_4, //D98/A21
+ PC_5, //D99/A22
+ PC_14, //D100
+ PC_15, //D101
+ PD_10, //D102
+ PE_1, //D103
+ PF_11, //D104
+ PG_4, //D105
+ PG_5, //D106
+ PG_6, //D107
+ PG_7, //D108
+ PG_8, //D109
+ PG_10, //D110
+ PG_11, //D111
+ PG_12, //D112
+ PG_13, //D113
+ PG_15, //D114
+ PH_0, //D115
+ PH_1 //D116
+};
+
+// Analog (Ax) pin number array
+const uint32_t analogInputPin[] = {
+ 78, //A0
+ 79, //A1
+ 80, //A2
+ 81, //A3
+ 82, //A4
+ 83, //A5
+ 84, //A6
+ 85, //A7
+ 86, //A8
+ 87, //A9
+ 11, //A10
+ 12, //A11
+ 13, //A12
+ 24, //A13
+ 32, //A14
+ 61, //A15
+ 62, //A16
+ 63, //A17
+ 88, //A18
+ 89, //A19
+ 97, //A20
+ 98, //A21
+ 99, //A22
+ 33 //A23
+};
+
+// ----------------------------------------------------------------------------
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief System Clock Configuration
+ * @param None
+ * @retval None
+ */
+WEAK void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
+
+ /** Configure LSE Drive Capability
+ */
+ HAL_PWR_EnableBkUpAccess();
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 4;
+ RCC_OscInitStruct.PLL.PLLN = 180;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 7;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Activate the Over-Drive mode
+ */
+ if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.PLLSAI.PLLSAIM = 4;
+ PeriphClkInitStruct.PLLSAI.PLLSAIN = 96;
+ PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2;
+ PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4;
+ PeriphClkInitStruct.PLLSAIDivQ = 1;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
+ PeriphClkInitStruct.SdioClockSelection = RCC_SDIOCLKSOURCE_CLK48;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ARDUINO_NUCLEO_L476RG */
diff --git a/variants/STM32F4xx/F446Z(C-E)(H-J-T)/variant_NUCLEO_F446ZE.h b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/variant_NUCLEO_F446ZE.h
new file mode 100644
index 0000000000..765541d1ef
--- /dev/null
+++ b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/variant_NUCLEO_F446ZE.h
@@ -0,0 +1,277 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2023, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#pragma once
+
+/*----------------------------------------------------------------------------
+ * STM32 pins number
+ *----------------------------------------------------------------------------*/
+#define PG9 0
+#define PG14 1
+#define PF15 2
+#define PE13 3
+#define PF14 4
+#define PE11 5
+#define PE9 6
+#define PF13 7
+#define PF12 8
+#define PD15 9
+#define PD14 10
+#define PA7 PIN_A10
+#define PA6 PIN_A11
+#define PA5 PIN_A12
+#define PB9 14
+#define PB8 15
+#define PC6 16
+#define PB15 17
+#define PB13 18
+#define PB12 19
+#define PA15 20
+#define PC7 21
+#define PB5 22
+#define PB3 23
+#define PA4 PIN_A13
+#define PB4 25
+#define PB6 26
+#define PB2 27
+#define PD13 28
+#define PD12 29
+#define PD11 30
+#define PE2 31
+#define PA0 PIN_A14
+#define PB0 PIN_A23 // LED_GREEN
+#define PE0 34
+#define PB11 35
+#define PB10 36
+#define PE15 37
+#define PE14 38
+#define PE12 39
+#define PE10 40
+#define PE7 41
+#define PE8 42
+#define PC8 43
+#define PC9 44
+#define PC10 45
+#define PC11 46
+#define PC12 47
+#define PD2 48
+#define PG2 49
+#define PG3 50
+#define PD7 51
+#define PD6 52
+#define PD5 53
+#define PD4 54
+#define PD3 55
+// 56 is PE2 (31)
+#define PE4 57
+#define PE5 58
+#define PE6 59
+#define PE3 60
+#define PF8 PIN_A15
+#define PF7 PIN_A16
+#define PF9 PIN_A17
+#define PG1 64
+#define PG0 65
+#define PD1 66
+#define PD0 67
+#define PF0 68
+#define PF1 69
+#define PF2 70
+// 71 is NC
+// 72 is NC
+#define PB7 73 // LED_BLUE
+#define PB14 74 // LED_RED
+#define PC13 75 // USER_BTN
+#define PD9 76 // Serial Rx
+#define PD8 77 // Serial Tx
+#define PA3 PIN_A0
+#define PC0 PIN_A1
+#define PC3 PIN_A2
+#define PF3 PIN_A3
+#define PF5 PIN_A4
+#define PF10 PIN_A5
+#define PB1 PIN_A6
+#define PC2 PIN_A7
+#define PF4 PIN_A8
+// ST Morpho
+#define PF6 PIN_A9
+#define PA1 PIN_A18
+#define PA2 PIN_A19
+#define PA8 90
+#define PA9 91
+#define PA10 92
+#define PA11 93
+#define PA12 94
+#define PA13 95 // SWD
+#define PA14 96 // SWD
+#define PC1 PIN_A20
+#define PC4 PIN_A21
+#define PC5 PIN_A22
+#define PC14 100
+#define PC15 101
+#define PD10 102
+#define PE1 103
+#define PF11 104
+#define PG4 105
+#define PG5 106
+#define PG6 107
+#define PG7 108
+#define PG8 109
+#define PG10 110
+#define PG11 111
+#define PG12 112
+#define PG13 113
+#define PG15 114
+#define PH0 115 // MCO
+#define PH1 116
+
+// Alternate pins number
+#define PA0_ALT1 (PA0 | ALT1)
+#define PA0_ALT2 (PA0 | ALT2)
+#define PA1_ALT1 (PA1 | ALT1)
+#define PA1_ALT2 (PA1 | ALT2)
+#define PA2_ALT1 (PA2 | ALT1)
+#define PA2_ALT2 (PA2 | ALT2)
+#define PA3_ALT1 (PA3 | ALT1)
+#define PA3_ALT2 (PA3 | ALT2)
+#define PA4_ALT1 (PA4 | ALT1)
+#define PA5_ALT1 (PA5 | ALT1)
+#define PA6_ALT1 (PA6 | ALT1)
+#define PA7_ALT1 (PA7 | ALT1)
+#define PA7_ALT2 (PA7 | ALT2)
+#define PA7_ALT3 (PA7 | ALT3)
+#define PA15_ALT1 (PA15 | ALT1)
+#define PB0_ALT1 (PB0 | ALT1)
+#define PB0_ALT2 (PB0 | ALT2)
+#define PB1_ALT1 (PB1 | ALT1)
+#define PB1_ALT2 (PB1 | ALT2)
+#define PB3_ALT1 (PB3 | ALT1)
+#define PB4_ALT1 (PB4 | ALT1)
+#define PB5_ALT1 (PB5 | ALT1)
+#define PB8_ALT1 (PB8 | ALT1)
+#define PB9_ALT1 (PB9 | ALT1)
+#define PB14_ALT1 (PB14 | ALT1)
+#define PB14_ALT2 (PB14 | ALT2)
+#define PB15_ALT1 (PB15 | ALT1)
+#define PB15_ALT2 (PB15 | ALT2)
+#define PC0_ALT1 (PC0 | ALT1)
+#define PC0_ALT2 (PC0 | ALT2)
+#define PC1_ALT1 (PC1 | ALT1)
+#define PC1_ALT2 (PC1 | ALT2)
+#define PC2_ALT1 (PC2 | ALT1)
+#define PC2_ALT2 (PC2 | ALT2)
+#define PC3_ALT1 (PC3 | ALT1)
+#define PC3_ALT2 (PC3 | ALT2)
+#define PC4_ALT1 (PC4 | ALT1)
+#define PC5_ALT1 (PC5 | ALT1)
+#define PC6_ALT1 (PC6 | ALT1)
+#define PC7_ALT1 (PC7 | ALT1)
+#define PC8_ALT1 (PC8 | ALT1)
+#define PC9_ALT1 (PC9 | ALT1)
+#define PC10_ALT1 (PC10 | ALT1)
+#define PC11_ALT1 (PC11 | ALT1)
+
+// This must be a literal
+#define NUM_DIGITAL_PINS 117
+// This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS
+#define NUM_ANALOG_INPUTS 24
+
+// On-board LED pin number
+#define LED_GREEN PB0
+#ifndef LED_BUILTIN
+ #define LED_BUILTIN LED_GREEN
+#endif
+#define LED_BLUE PB7
+#define LED_RED PB14
+
+// On-board user button
+#ifndef USER_BTN
+ #define USER_BTN PC13
+#endif
+
+// Timer Definitions
+// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
+#ifndef TIMER_TONE
+ #define TIMER_TONE TIM6
+#endif
+#ifndef TIMER_SERVO
+ #define TIMER_SERVO TIM7
+#endif
+
+// UART Definitions
+#ifndef SERIAL_UART_INSTANCE
+ #define SERIAL_UART_INSTANCE 3 //Connected to ST-Link
+#endif
+// Serial pin used for console (ex: stlink)
+// Rerquired by Firmata
+#ifndef PIN_SERIAL_RX
+ #define PIN_SERIAL_RX PD9
+#endif
+#ifndef PIN_SERIAL_TX
+ #define PIN_SERIAL_TX PD8
+#endif
+
+// Value of the External oscillator in Hz
+#define HSE_VALUE 8000000U
+
+// SDMMC signals not available
+#define SDMMC_CKIN_NA
+#define SDMMC_CDIR_NA
+#define SDMMC_D0DIR_NA
+#define SDMMC_D123DIR_NA
+
+// Extra HAL modules
+#if !defined(HAL_DAC_MODULE_DISABLED)
+ #define HAL_DAC_MODULE_ENABLED
+#endif
+#if !defined(HAL_ETH_MODULE_DISABLED)
+ #define HAL_ETH_MODULE_ENABLED
+#endif
+#if !defined(HAL_QSPI_MODULE_DISABLED)
+ #define HAL_QSPI_MODULE_ENABLED
+#endif
+#if !defined(HAL_SD_MODULE_DISABLED)
+ #define HAL_SD_MODULE_ENABLED
+#endif
+
+// Last Flash sector used for EEPROM emulation, address/sector depends on single/dual bank configuration.
+// By default 512kB single bank
+#define FLASH_BASE_ADDRESS 0x08060000
+#define FLASH_DATA_SECTOR 7
+
+/*----------------------------------------------------------------------------
+ * Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ // These serial port names are intended to allow libraries and architecture-neutral
+ // sketches to automatically default to the correct port name for a particular type
+ // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
+ // the first hardware serial port whose RX/TX pins are not dedicated to another use.
+ //
+ // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
+ //
+ // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
+ //
+ // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
+ //
+ // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
+ //
+ // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
+ // pins are NOT connected to anything by default.
+ #ifndef SERIAL_PORT_MONITOR
+ #define SERIAL_PORT_MONITOR Serial
+ #endif
+ #ifndef SERIAL_PORT_HARDWARE
+ #define SERIAL_PORT_HARDWARE Serial
+ #endif
+#endif