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[RISCV] Rename Spimm to StackAdj in most places. NFC
Spimm in the spec refers to the 2-bit encoded value. All of the code uses the 0, 16, 32, or 48 adjustment value. Also remove the decodeZcmpSpimm as its identical to the default behavior for no custom DecoderMethod.
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6 files changed

+34
-42
lines changed

6 files changed

+34
-42
lines changed

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -350,7 +350,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
350350
FRM,
351351
Fence,
352352
RegList,
353-
Spimm,
353+
StackAdj,
354354
RegReg,
355355
} Kind;
356356

@@ -392,7 +392,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
392392
unsigned Encoding;
393393
};
394394

395-
struct SpimmOp {
395+
struct StackAdjOp {
396396
unsigned Val;
397397
};
398398

@@ -412,7 +412,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
412412
FRMOp FRM;
413413
FenceOp Fence;
414414
RegListOp RegList;
415-
SpimmOp Spimm;
415+
StackAdjOp StackAdj;
416416
RegRegOp RegReg;
417417
};
418418

@@ -451,8 +451,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
451451
case KindTy::RegList:
452452
RegList = o.RegList;
453453
break;
454-
case KindTy::Spimm:
455-
Spimm = o.Spimm;
454+
case KindTy::StackAdj:
455+
StackAdj = o.StackAdj;
456456
break;
457457
case KindTy::RegReg:
458458
RegReg = o.RegReg;
@@ -486,7 +486,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
486486
bool isRegListS0() const {
487487
return Kind == KindTy::RegList && RegList.Encoding != RISCVZC::RA;
488488
}
489-
bool isSpimm() const { return Kind == KindTy::Spimm; }
489+
bool isStackAdj() const { return Kind == KindTy::StackAdj; }
490490

491491
bool isGPR() const {
492492
return Kind == KindTy::Register &&
@@ -1014,9 +1014,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
10141014
RISCVZC::printRegList(RegList.Encoding, OS);
10151015
OS << '>';
10161016
break;
1017-
case KindTy::Spimm:
1018-
OS << "<Spimm: ";
1019-
OS << Spimm.Val;
1017+
case KindTy::StackAdj:
1018+
OS << "<stackadj: ";
1019+
OS << StackAdj.Val;
10201020
OS << '>';
10211021
break;
10221022
case KindTy::RegReg:
@@ -1116,9 +1116,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
11161116
return Op;
11171117
}
11181118

1119-
static std::unique_ptr<RISCVOperand> createSpimm(unsigned Spimm, SMLoc S) {
1120-
auto Op = std::make_unique<RISCVOperand>(KindTy::Spimm);
1121-
Op->Spimm.Val = Spimm;
1119+
static std::unique_ptr<RISCVOperand> createStackAdj(unsigned StackAdj, SMLoc S) {
1120+
auto Op = std::make_unique<RISCVOperand>(KindTy::StackAdj);
1121+
Op->StackAdj.Val = StackAdj;
11221122
Op->StartLoc = S;
11231123
return Op;
11241124
}
@@ -1194,9 +1194,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
11941194
Inst.addOperand(MCOperand::createReg(RegReg.Reg2));
11951195
}
11961196

1197-
void addSpimmOperands(MCInst &Inst, unsigned N) const {
1197+
void addStackAdjOperands(MCInst &Inst, unsigned N) const {
11981198
assert(N == 1 && "Invalid number of operands!");
1199-
Inst.addOperand(MCOperand::createImm(Spimm.Val));
1199+
Inst.addOperand(MCOperand::createImm(StackAdj.Val));
12001200
}
12011201

12021202
void addFRMArgOperands(MCInst &Inst, unsigned N) const {
@@ -2699,8 +2699,8 @@ ParseStatus RISCVAsmParser::parseZcmpStackAdj(OperandVector &Operands,
26992699
"be a multiple of 16 bytes in the range");
27002700
}
27012701

2702-
unsigned Spimm = (StackAdjustment - StackAdjBase) / 16;
2703-
Operands.push_back(RISCVOperand::createSpimm(Spimm << 4, S));
2702+
unsigned StackAdj = (StackAdjustment - StackAdjBase);
2703+
Operands.push_back(RISCVOperand::createStackAdj(StackAdj, S));
27042704
Lex();
27052705
return ParseStatus::Success;
27062706
}

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -527,8 +527,8 @@ static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
527527
uint64_t Address,
528528
const MCDisassembler *Decoder);
529529

530-
static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm,
531-
uint64_t Address, const void *Decoder);
530+
static DecodeStatus decodeZcmpStackAdj(MCInst &Inst, uint32_t Imm,
531+
uint64_t Address, const void *Decoder);
532532

533533
static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
534534
uint64_t Address,
@@ -668,12 +668,6 @@ static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
668668
return MCDisassembler::Success;
669669
}
670670

671-
static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm,
672-
uint64_t Address, const void *Decoder) {
673-
Inst.addOperand(MCOperand::createImm(Imm));
674-
return MCDisassembler::Success;
675-
}
676-
677671
// Add implied SP operand for C.*SP compressed instructions. The SP operand
678672
// isn't explicitly encoded in the instruction.
679673
void RISCVDisassembler::addSPOperands(MCInst &MI) const {

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -352,7 +352,7 @@ enum OperandType : unsigned {
352352
OPERAND_RVKRNUM_2_14,
353353
OPERAND_RLIST,
354354
OPERAND_RLIST_S0,
355-
OPERAND_SPIMM,
355+
OPERAND_STACKADJ,
356356
// Operand is a 3-bit rounding mode, '111' indicates FRM register.
357357
// Represents 'frm' argument passing to floating-point operations.
358358
OPERAND_FRMARG,

‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -962,10 +962,10 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
962962
// stack space. Align the stack size down to a multiple of 16. This is
963963
// needed for RVE.
964964
// FIXME: Can we increase the stack size to a multiple of 16 instead?
965-
uint64_t Spimm =
965+
uint64_t StackAdj =
966966
std::min(alignDown(StackSize, 16), static_cast<uint64_t>(48));
967-
FirstFrameSetup->getOperand(1).setImm(Spimm);
968-
StackSize -= Spimm;
967+
FirstFrameSetup->getOperand(1).setImm(StackAdj);
968+
StackSize -= StackAdj;
969969

970970
unsigned CFIIndex = MF.addFrameInst(
971971
MCCFIInstruction::cfiDefCfaOffset(nullptr, RealStackSize - StackSize));
@@ -1278,10 +1278,10 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
12781278
// space. Align the stack size down to a multiple of 16. This is needed for
12791279
// RVE.
12801280
// FIXME: Can we increase the stack size to a multiple of 16 instead?
1281-
uint64_t Spimm =
1281+
uint64_t StackAdj =
12821282
std::min(alignDown(StackSize, 16), static_cast<uint64_t>(48));
1283-
MBBI->getOperand(1).setImm(Spimm);
1284-
StackSize -= Spimm;
1283+
MBBI->getOperand(1).setImm(StackAdj);
1284+
StackSize -= StackAdj;
12851285

12861286
if (StackSize != 0)
12871287
deallocateStack(MF, MBB, MBBI, DL, StackSize,
@@ -1984,7 +1984,7 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
19841984
MBB.addLiveIn(Reg);
19851985
// TODO: Handle QCI Interrupt + Push/Pop
19861986
} else if (RVFI->isPushable(*MF)) {
1987-
// Emit CM.PUSH with base SPimm & evaluate Push stack
1987+
// Emit CM.PUSH with base StackAdj & evaluate Push stack
19881988
unsigned PushedRegNum = RVFI->getRVPushRegs();
19891989
if (PushedRegNum > 0) {
19901990
// Use encoded number to represent registers to spill.

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2702,8 +2702,8 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
27022702
case RISCVOp::OPERAND_RLIST_S0:
27032703
Ok = Imm >= RISCVZC::RA_S0 && Imm <= RISCVZC::RA_S0_S11;
27042704
break;
2705-
case RISCVOp::OPERAND_SPIMM:
2706-
Ok = (Imm & 0xf) == 0;
2705+
case RISCVOp::OPERAND_STACKADJ:
2706+
Ok = Imm >= 0 && Imm <= 48 && Imm % 16 == 0;
27072707
break;
27082708
case RISCVOp::OPERAND_FRMARG:
27092709
Ok = RISCVFPRndMode::isValidRoundingMode(Imm);

‎llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -46,16 +46,16 @@ def StackAdjAsmOperand : AsmOperandClass {
4646
let Name = "StackAdj";
4747
let ParserMethod = "parseZcmpStackAdj";
4848
let DiagnosticType = "InvalidStackAdj";
49-
let PredicateMethod = "isSpimm";
50-
let RenderMethod = "addSpimmOperands";
49+
let PredicateMethod = "isStackAdj";
50+
let RenderMethod = "addStackAdjOperands";
5151
}
5252

5353
def NegStackAdjAsmOperand : AsmOperandClass {
5454
let Name = "NegStackAdj";
5555
let ParserMethod = "parseZcmpNegStackAdj";
5656
let DiagnosticType = "InvalidStackAdj";
57-
let PredicateMethod = "isSpimm";
58-
let RenderMethod = "addSpimmOperands";
57+
let PredicateMethod = "isStackAdj";
58+
let RenderMethod = "addStackAdjOperands";
5959
}
6060

6161
def reglist : RISCVOp<OtherVT> {
@@ -77,8 +77,7 @@ def reglist : RISCVOp<OtherVT> {
7777
def stackadj : RISCVOp<OtherVT> {
7878
let ParserMatchClass = StackAdjAsmOperand;
7979
let PrintMethod = "printStackAdj";
80-
let DecoderMethod = "decodeZcmpSpimm";
81-
let OperandType = "OPERAND_SPIMM";
80+
let OperandType = "OPERAND_STACKADJ";
8281
let MCOperandPredicate = [{
8382
int64_t Imm;
8483
if (!MCOp.evaluateAsConstantImm(Imm))
@@ -90,8 +89,7 @@ def stackadj : RISCVOp<OtherVT> {
9089
def negstackadj : RISCVOp<OtherVT> {
9190
let ParserMatchClass = NegStackAdjAsmOperand;
9291
let PrintMethod = "printNegStackAdj";
93-
let DecoderMethod = "decodeZcmpSpimm";
94-
let OperandType = "OPERAND_SPIMM";
92+
let OperandType = "OPERAND_STACKADJ";
9593
let MCOperandPredicate = [{
9694
int64_t Imm;
9795
if (!MCOp.evaluateAsConstantImm(Imm))

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