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[RISCV] Mark the Zfa extension as non-experimental (llvm#68113)
Following the version bump in llvm#67964 and the bug fix in llvm#68026 I believe we're ready to mark Zfa as non-experimental. I'll note the GCC torture suite passes now with Zfa enabled (though it's more of a litmus test than anything else).
1 parent f2357da commit eae1e28

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+55
-58
lines changed

‎clang/test/Driver/riscv-arch.c

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Original file line numberDiff line numberDiff line change
@@ -372,24 +372,24 @@
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// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
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// RV32-ZFHMIN: "-target-feature" "+zfhmin"
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375-
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izfa -### %s \
375+
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \
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// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
377-
// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izfa'
377+
// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32iztso'
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// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
379379

380-
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izfa -menable-experimental-extensions -### %s \
380+
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -menable-experimental-extensions -### %s \
381381
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
382-
// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izfa'
382+
// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32iztso'
383383
// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number
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385-
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izfa0p1 -menable-experimental-extensions -### %s \
385+
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso0p7 -menable-experimental-extensions -### %s \
386386
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
387-
// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izfa0p1'
388-
// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension 'zfa' (this compiler supports 1.0)
387+
// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32iztso0p7'
388+
// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'ztso' (this compiler supports 0.1)
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390-
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfa1p0 -menable-experimental-extensions -### %s \
390+
// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso0p1 -menable-experimental-extensions -### %s \
391391
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
392-
// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zfa"
392+
// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-ztso"
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// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
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// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s

‎clang/test/Preprocessor/riscv-target-features.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1001,11 +1001,11 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
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// CHECK-ZACAS-EXT: __riscv_zacas 1000000{{$}}
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1004-
// RUN: %clang --target=riscv32-unknown-linux-gnu -menable-experimental-extensions \
1005-
// RUN: -march=rv32izfa1p0 -x c -E -dM %s \
1004+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
1005+
// RUN: -march=rv32izfa -x c -E -dM %s \
10061006
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu -menable-experimental-extensions \
1008-
// RUN: -march=rv64izfa1p0 -x c -E -dM %s \
1007+
// RUN: %clang --target=riscv64-unknown-linux-gnu \
1008+
// RUN: -march=rv64izfa -x c -E -dM %s \
10091009
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
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// CHECK-ZFA-EXT: __riscv_zfa 1000000{{$}}
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‎llvm/docs/RISCVUsage.rst

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@@ -109,6 +109,7 @@ on support follow.
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``Zcmp`` Assembly Support
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``Zcmt`` Assembly Support
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``Zdinx`` Supported
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``Zfa`` Supported
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``Zfh`` Supported
113114
``Zfhmin`` Supported
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``Zfinx`` Supported
@@ -196,9 +197,6 @@ The primary goal of experimental support is to assist in the process of ratifica
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``experimental-zacas``
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LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zacas/releases/tag/v1.0-rc1>`_.
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``experimental-zfa``
200-
LLVM implements the `1.0 specification <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-056b6ff-2023-10-02>`__.
201-
202200
``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
203201
LLVM implements assembler support for the `0.8.0 draft specification <https://github.com/riscv/riscv-bfloat16/releases/tag/20230629>`_.
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‎llvm/docs/ReleaseNotes.rst

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@@ -109,7 +109,7 @@ Changes to the PowerPC Backend
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Changes to the RISC-V Backend
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-----------------------------
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* The Zfa extension version was upgraded to 1.0.
112+
* The Zfa extension version was upgraded to 1.0 and is no longer experimental.
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* Zihintntl extension version was upgraded to 1.0 and is no longer experimental.
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Changes to the WebAssembly Backend

‎llvm/lib/Support/RISCVISAInfo.cpp

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@@ -106,6 +106,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
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{"zdinx", RISCVExtensionVersion{1, 0}},
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109+
{"zfa", RISCVExtensionVersion{1, 0}},
109110
{"zfh", RISCVExtensionVersion{1, 0}},
110111
{"zfhmin", RISCVExtensionVersion{1, 0}},
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{"zfinx", RISCVExtensionVersion{1, 0}},
@@ -166,7 +167,6 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
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167168
{"zacas", RISCVExtensionVersion{1, 0}},
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169-
{"zfa", RISCVExtensionVersion{1, 0}},
170170
{"zfbfmin", RISCVExtensionVersion{0, 8}},
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172172
{"zicfilp", RISCVExtensionVersion{0, 2}},

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -159,7 +159,7 @@ def HasStdExtZhinxOrZhinxmin
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"'Zhinxmin' (Half Float in Integer Minimal)">;
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161161
def FeatureStdExtZfa
162-
: SubtargetFeature<"experimental-zfa", "HasStdExtZfa", "true",
162+
: SubtargetFeature<"zfa", "HasStdExtZfa", "true",
163163
"'Zfa' (Additional Floating-Point)",
164164
[FeatureStdExtF]>;
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def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,

‎llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

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@@ -8,7 +8,6 @@
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//
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// This file describes the RISC-V instructions from the standard 'Zfa'
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// additional floating-point extension, version 1.0.
11-
// This version is still experimental.
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//
1312
//===----------------------------------------------------------------------===//
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‎llvm/test/CodeGen/RISCV/attributes.ll

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@@ -63,7 +63,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIFENCEI %s
6464
; RUN: llc -mtriple=riscv32 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICNTR %s
6565
; RUN: llc -mtriple=riscv32 -mattr=+zihpm %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIHPM %s
66-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFA %s
66+
; RUN: llc -mtriple=riscv32 -mattr=+zfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFA %s
6767
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - | FileCheck --check-prefix=RV32ZVBB %s
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; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV32ZVBC %s
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; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV32ZVKB %s
@@ -153,7 +153,7 @@
153153
; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIFENCEI %s
154154
; RUN: llc -mtriple=riscv64 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICNTR %s
155155
; RUN: llc -mtriple=riscv64 -mattr=+zihpm %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIHPM %s
156-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFA %s
156+
; RUN: llc -mtriple=riscv64 -mattr=+zfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFA %s
157157
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - | FileCheck --check-prefix=RV64ZVBB %s
158158
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV64ZVBC %s
159159
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV64ZVKB %s

‎llvm/test/CodeGen/RISCV/double-zfa.ll

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@@ -1,7 +1,7 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+experimental-zfa,+d < %s \
2+
; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zfa,+d < %s \
33
; RUN: | FileCheck --check-prefixes=CHECK,RV32IDZFA %s
4-
; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+experimental-zfa,+d < %s \
4+
; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+zfa,+d < %s \
55
; RUN: | FileCheck --check-prefixes=CHECK,RV64DZFA %s
66

77
define double @loadfpimm1() {

‎llvm/test/CodeGen/RISCV/fli-licm.ll

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@@ -1,7 +1,7 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2-
; RUN: llc < %s -mtriple=riscv32 -target-abi=ilp32f -mattr=+experimental-zfa \
2+
; RUN: llc < %s -mtriple=riscv32 -target-abi=ilp32f -mattr=+zfa \
33
; RUN: | FileCheck %s --check-prefix=RV32
4-
; RUN: llc < %s -mtriple=riscv64 -target-abi=lp64f -mattr=+experimental-zfa \
4+
; RUN: llc < %s -mtriple=riscv64 -target-abi=lp64f -mattr=+zfa \
55
; RUN: | FileCheck %s --check-prefix=RV64
66

77
; The purpose of this test is to check that an FLI instruction that

‎llvm/test/CodeGen/RISCV/float-zfa.ll

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@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa < %s \
2+
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa < %s \
33
; RUN: | FileCheck %s
4-
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa < %s \
4+
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa < %s \
55
; RUN: | FileCheck %s
66

77
define float @loadfpimm1() {

‎llvm/test/CodeGen/RISCV/half-zfa-fli.ll

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11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa,+zfh < %s \
2+
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa,+zfh < %s \
33
; RUN: | FileCheck %s
4-
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa,+zfh < %s \
4+
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa,+zfh < %s \
55
; RUN: | FileCheck %s
6-
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa,+zfhmin < %s \
6+
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa,+zfhmin < %s \
77
; RUN: | FileCheck %s --check-prefix=ZFHMIN
8-
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa,+zfhmin < %s \
8+
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa,+zfhmin < %s \
99
; RUN: | FileCheck %s --check-prefix=ZFHMIN
1010

1111
define half @loadfpimm1() {

‎llvm/test/CodeGen/RISCV/half-zfa.ll

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@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa,+zfh < %s \
2+
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa,+zfh < %s \
33
; RUN: | FileCheck %s
4-
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa,+zfh < %s \
4+
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa,+zfh < %s \
55
; RUN: | FileCheck %s
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77
declare half @llvm.minimum.f16(half, half)

‎llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll

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@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+zfh,+experimental-zfa,+zvfh,+v -target-abi ilp32d -verify-machineinstrs < %s \
2+
; RUN: llc -mtriple=riscv32 -mattr=+zfh,+zfa,+zvfh,+v -target-abi ilp32d -verify-machineinstrs < %s \
33
; RUN: | FileCheck %s --check-prefixes=CHECK
4-
; RUN: llc -mtriple=riscv64 -mattr=+zfh,+experimental-zfa,+zvfh,+v -target-abi lp64d -verify-machineinstrs < %s \
4+
; RUN: llc -mtriple=riscv64 -mattr=+zfh,+zfa,+zvfh,+v -target-abi lp64d -verify-machineinstrs < %s \
55
; RUN: | FileCheck %s --check-prefixes=CHECK
66

77
define <vscale x 8 x half> @vsplat_f16_0p625() {

‎llvm/test/MC/RISCV/rv32zfa-only-valid.s

Lines changed: 3 additions & 3 deletions
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@@ -1,7 +1,7 @@
1-
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh -riscv-no-aliases -show-encoding \
1+
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfa,+d,+zfh -riscv-no-aliases -show-encoding \
22
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
3-
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh < %s \
4-
# RUN: | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d -r - \
3+
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zfa,+d,+zfh < %s \
4+
# RUN: | llvm-objdump --mattr=+zfa,+d,+zfh -M no-aliases -d -r - \
55
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
66
#
77
# RUN: not llvm-mc -triple riscv32 -mattr=+d,+zfh \

‎llvm/test/MC/RISCV/zfa-double-invalid.s

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@@ -1,7 +1,7 @@
1-
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfa,+zfh \
1+
# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+zfh \
22
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
33
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXTD %s
4-
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zfa,+zfh \
4+
# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+zfh \
55
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
66
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXTD %s
77

‎llvm/test/MC/RISCV/zfa-half-invalid.s

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@@ -1,7 +1,7 @@
1-
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfa,+d \
1+
# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d \
22
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
33
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXTZFH %s
4-
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zfa,+d \
4+
# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d \
55
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
66
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXTZFH %s
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‎llvm/test/MC/RISCV/zfa-invalid.s

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@@ -1,5 +1,5 @@
1-
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zfa,+d,+zfh < %s 2>&1 | FileCheck -check-prefixes=CHECK-NO-RV32 %s
2-
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfa,+d,+zfh < %s 2>&1 | FileCheck -check-prefixes=CHECK-NO-RV64 %s
1+
# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck -check-prefixes=CHECK-NO-RV32 %s
2+
# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck -check-prefixes=CHECK-NO-RV64 %s
33

44
# Invalid rounding modes
55
# CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode

‎llvm/test/MC/RISCV/zfa-valid.s

Lines changed: 6 additions & 6 deletions
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@@ -1,12 +1,12 @@
1-
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh -riscv-no-aliases -show-encoding \
1+
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfa,+d,+zfh -riscv-no-aliases -show-encoding \
22
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
3-
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfa,+d,+zfh -riscv-no-aliases -show-encoding \
3+
# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+d,+zfh -riscv-no-aliases -show-encoding \
44
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
5-
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh < %s \
6-
# RUN: | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d -r - \
5+
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zfa,+d,+zfh < %s \
6+
# RUN: | llvm-objdump --mattr=+zfa,+d,+zfh -M no-aliases -d -r - \
77
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
8-
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfa,+d,+zfh < %s \
9-
# RUN: | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d -r - \
8+
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+d,+zfh < %s \
9+
# RUN: | llvm-objdump --mattr=+zfa,+d,+zfh -M no-aliases -d -r - \
1010
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
1111
#
1212
# RUN: not llvm-mc -triple riscv32 -mattr=+d,+zfh \

‎llvm/test/MC/RISCV/zfa-zfhmin-zvfh-valid.s

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
1-
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfa,+zfhmin,+zvfh -riscv-no-aliases -show-encoding \
1+
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfa,+zfhmin,+zvfh -riscv-no-aliases -show-encoding \
22
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
3-
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfa,+zfhmin,+zvfh -riscv-no-aliases -show-encoding \
3+
# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+zfhmin,+zvfh -riscv-no-aliases -show-encoding \
44
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
5-
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfa,+zfhmin,+zvfh < %s \
6-
# RUN: | llvm-objdump --mattr=+experimental-zfa,+zfhmin,+zvfh -M no-aliases -d -r - \
5+
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zfa,+zfhmin,+zvfh < %s \
6+
# RUN: | llvm-objdump --mattr=+zfa,+zfhmin,+zvfh -M no-aliases -d -r - \
77
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
8-
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfa,+zfhmin,+zvfh < %s \
9-
# RUN: | llvm-objdump --mattr=+experimental-zfa,+zfhmin,+zvfh -M no-aliases -d -r - \
8+
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+zfhmin,+zvfh < %s \
9+
# RUN: | llvm-objdump --mattr=+zfa,+zfhmin,+zvfh -M no-aliases -d -r - \
1010
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
1111
#
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# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \

‎llvm/unittests/Support/RISCVISAInfoTest.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -653,6 +653,7 @@ R"(All available -march extensions for RISC-V
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zihpm 2.0
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zmmul 1.0
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zawrs 1.0
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zfa 1.0
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zfh 1.0
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zfhmin 1.0
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zfinx 1.0
@@ -729,7 +730,6 @@ Experimental extensions
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zicfilp 0.2 This is a long dummy description
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zicond 1.0
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zacas 1.0
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zfa 1.0
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zfbfmin 0.8
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ztso 0.1
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zvbb 1.0

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