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.github/ISSUE_TEMPLATE/bug_report.md

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---
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**Notes (delete this)**
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Github Discussions (https://github.com/zephyrproject-rtos/zephyr/discussions)
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are available to first verify that the issue is a genuine Zephyr bug and not a
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consequence of Zephyr services misuse.
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This issue list is only for bugs in the main Zephyr code base
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(https://github.com/zephyrproject-rtos/zephyr/). If the bug is for a project
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fork (such as NCS) specific feature, please open an issue in the fork project
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instead.
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**Describe the bug**
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A clear and concise description of what the bug is.
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(Note that [Github Discussions](https://github.com/zephyrproject-rtos/zephyr/discussions) are available to first verify that the issue
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is a genuine Zephyr bug and not a consequence of Zephyr services misuse.)
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Please also mention any information which could help others to understand
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the problem you're facing:

boards/xtensa/intel_adsp_ace15_mtpm/board.cmake

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# SPDX-License-Identifier: Apache-2.0
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board_set_rimage_target(mtl)
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set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in ace15_mtpm/board.cmake")

boards/xtensa/intel_adsp_ace20_lnl/board.cmake

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set(SUPPORTED_EMU_PLATFORMS acesim)
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board_set_rimage_target(lnl)
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set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in ace20_lnl/board.cmake")

boards/xtensa/intel_adsp_cavs25/board.cmake

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board_set_flasher_ifnset(intel_adsp)
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set(RIMAGE_SIGN_KEY otc_private_key_3k.pem)
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set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in cavs25/board.cmake")
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if(CONFIG_BOARD_INTEL_ADSP_CAVS25)
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board_set_rimage_target(tgl)

doc/develop/west/sign.rst

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.. _imgtool:
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https://pypi.org/project/imgtool/
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rimage
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******
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rimage configuration uses a different approach that does not rely on Kconfig or CMake
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but on :ref:`west config<west-config>` instead, similar to
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:ref:`west-building-cmake-config`.
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Signing involves a number of "wrapper" scripts stacked on top of each other: ``west
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flash`` invokes ``west build`` which invokes ``cmake`` and ``ninja`` which invokes
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``west sign`` which invokes ``imgtool`` or `rimage`_. As long as the signing
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parameters desired are the default ones and fairly static, these indirections are
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not a problem. On the other hand, passing ``imgtool`` or ``rimage`` options through
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all these layers can causes issues typical when the layers don't abstract
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anything. First, this usually requires boilerplate code in each layer. Quoting
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whitespace or other special characters through all the wrappers can be
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difficult. Reproducing a lower ``west sign`` command to debug some build-time issue
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can be very time-consuming: it requires at least enabling and searching verbose
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build logs to find which exact options were used. Copying these options from the
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build logs can be unreliable: it may produce different results because of subtle
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environment differences. Last and worst: new signing feature and options are
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impossible to use until more boilerplate code has been added in each layer.
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To avoid these issues, ``rimage`` parameters can bet set in ``west config``
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instead. Here's a ``workspace/.west/config`` example:
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.. code-block:: ini
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[sign]
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# Not needed when invoked from CMake
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tool = rimage
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[rimage]
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# Quoting is optional and works like in Unix shells
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# Not needed when rimage can be found in the default PATH
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path = "/home/me/zworkspace/build-rimage/rimage"
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# Not needed when using the default development key
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extra-args = -i 4 -k 'keys/key argument with space.pem'
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In order to support quoting, values are parsed by Python's ``shlex.split()`` like in
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:ref:`west-building-cmake-args`.
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The ``extra-args`` are passed directly to the ``rimage`` command. The example
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above has the same effect as appending them on command line after ``--`` like this:
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``west sign --tool rimage -- -i 4 -k 'keys/key argument with space.pem'``. In case
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both are used, the command-line arguments go last.
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.. _rimage:
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https://github.com/thesofproject/rimage

doc/releases/release-notes-3.4.rst

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correctly, allowing other transports or other parts of the application
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code to use it.
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* RTIO
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* Added policy that every ``sqe`` will generate a ``cqe`` (previously an RTIO_SQE_TRANSACTION
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entry would only trigger a ``cqe`` on the last ``sqe`` in the transaction.
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HALs
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****
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