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refactor: remove packed from MMIO structs
rust-lang/rust#46043 makes accessing members of packed structs unsafe. For MMIO structs, `repr(C)` alone should be sufficient as the layout by definition has no holes.
1 parent f02c818 commit dd0e9cc

29 files changed

+42
-42
lines changed

‎arch/cortex-m0/src/nvic.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
33
use kernel::common::volatile_cell::VolatileCell;
44

5-
#[repr(C, packed)]
5+
#[repr(C)]
66
// Registers for the NVIC
77
struct Registers {
88
// Interrupt set-enable

‎arch/cortex-m4/src/mpu.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ use kernel::common::math::PowerOfTwo;
66

77
/// Indicates whether the MPU is present and, if so, how many regions it
88
/// supports.
9-
#[repr(C,packed)]
9+
#[repr(C)]
1010
pub struct MpuType {
1111
/// Indicates whether the processor support unified (0) or separate
1212
/// (1) instruction and data regions. Always reads 0 on the
@@ -23,7 +23,7 @@ pub struct MpuType {
2323
_reserved: u8,
2424
}
2525

26-
#[repr(C,packed)]
26+
#[repr(C)]
2727
/// MPU Registers for the Cortex-M4 family
2828
///
2929
/// Described in section 4.5 of

‎arch/cortex-m4/src/nvic.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
33
use kernel::common::volatile_cell::VolatileCell;
44

5-
#[repr(C, packed)]
5+
#[repr(C)]
66
// Registers for the NVIC
77
struct Registers {
88
// Interrupt set-enable

‎arch/cortex-m4/src/scb.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
55
use kernel::common::VolatileCell;
66

7-
#[repr(C, packed)]
7+
#[repr(C)]
88
struct ScbRegisters {
99
cpuid: VolatileCell<u32>,
1010
icsr: VolatileCell<u32>,

‎capsules/src/net/ip.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ impl IPAddr {
6767
}
6868
}
6969

70-
#[repr(C, packed)]
70+
#[repr(C)]
7171
#[derive(Copy, Clone)]
7272
pub struct IP6Header {
7373
pub version_class_flow: [u8; 4],

‎chips/nrf51/src/peripheral_registers.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ use kernel::common::VolatileCell;
44

55
pub const RADIO_BASE: usize = 0x40001000;
66
#[allow(non_snake_case)]
7-
#[repr(C, packed)]
7+
#[repr(C)]
88
pub struct RADIO_REGS {
99
pub txen: VolatileCell<u32>, // 0x000 ---> 0x004
1010
pub rxen: VolatileCell<u32>, // 0x004 ---> 0x008

‎chips/nrf51/src/uart.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ use kernel::common::take_cell::TakeCell;
44
use kernel::hil::uart;
55
use nrf5x::pinmux::Pinmux;
66

7-
#[repr(C, packed)]
7+
#[repr(C)]
88
pub struct Registers {
99
pub task_startrx: VolatileCell<u32>,
1010
pub task_stoprx: VolatileCell<u32>,

‎chips/nrf52/src/ficr.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ use kernel::common::VolatileCell;
1212
/// Struct of the FICR registers
1313
///
1414
/// Section 13.1 of http://infocenter.nordicsemi.com/pdf/nRF52832_PS_v1.0.pdf
15-
#[repr(C, packed)]
15+
#[repr(C)]
1616
struct FicrRegisters {
1717
_reserved0: [VolatileCell<u32>; 4], // (0x10 - 0x00) / 4 = 4
1818
codepagesize: VolatileCell<u32>,

‎chips/nrf52/src/peripheral_registers.rs

+4-4
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ use kernel::common::VolatileCell;
22
use nrf5x;
33

44
pub const UARTE_BASE: u32 = 0x40002000;
5-
#[repr(C, packed)]
5+
#[repr(C)]
66
pub struct UARTE {
77
pub task_startrx: VolatileCell<u32>, // 0x000-0x004
88
pub task_stoprx: VolatileCell<u32>, // 0x004-0x008
@@ -54,7 +54,7 @@ pub struct UARTE {
5454
}
5555

5656
pub const UICR_BASE: usize = 0x10001200;
57-
#[repr(C, packed)]
57+
#[repr(C)]
5858
pub struct UICR {
5959
pub pselreset0: VolatileCell<u32>, // 0x200 - 0x204
6060
pub pselreset1: VolatileCell<u32>, // 0x204 - 0x208
@@ -63,7 +63,7 @@ pub struct UICR {
6363
}
6464

6565
pub const NVMC_BASE: usize = 0x4001E400;
66-
#[repr(C, packed)]
66+
#[repr(C)]
6767
pub struct NVMC {
6868
pub ready: VolatileCell<u32>, // 0x400-0x404
6969
_reserved1: [VolatileCell<u32>; 64], // 0x404-0x504
@@ -80,7 +80,7 @@ pub struct NVMC {
8080

8181
pub const RADIO_BASE: usize = 0x40001000;
8282
#[allow(non_snake_case)]
83-
#[repr(C, packed)]
83+
#[repr(C)]
8484
pub struct RADIO {
8585
pub task_txen: VolatileCell<u32>, // 0x000 - 0x004
8686
pub task_rxen: VolatileCell<u32>, // 0x004 - 0x008

‎chips/nrf52/src/spi.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -122,7 +122,7 @@ mod registers {
122122
}
123123

124124
/// Represents one of NRF52's three `SPIM` instances.
125-
#[repr(C, packed)]
125+
#[repr(C)]
126126
pub struct SPIM {
127127
_reserved0: [u32; 4],
128128
/// Start SPI transaction

‎chips/nrf5x/src/clock.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ use core::cell::Cell;
1515
use core::mem;
1616
use kernel::common::VolatileCell;
1717

18-
#[repr(C, packed)]
18+
#[repr(C)]
1919
struct Registers {
2020
pub tasks_hfclkstart: VolatileCell<u32>,
2121
pub tasks_hfclkstop: VolatileCell<u32>,

‎chips/nrf5x/src/gpio.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ const NUM_GPIOTE: usize = 8;
2121
/// Event) channel, and bind the channel to the desired pin. There are 4
2222
/// channels for the nrf51 and 8 channels for the nrf52. This means that
2323
/// requesting an interrupt can fail, if they are all already allocated.
24-
#[repr(C, packed)]
24+
#[repr(C)]
2525
struct GpioteRegisters {
2626
out: [VolatileCell<u32>; NUM_GPIOTE], // 0x0
2727
_reserved0: [u8; 0x100 - (0x0 + NUM_GPIOTE * 4)],

‎chips/nrf5x/src/peripheral_registers.rs

+6-6
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
use kernel::common::VolatileCell;
22

33
pub const RTC1_BASE: usize = 0x40011000;
4-
#[repr(C, packed)]
4+
#[repr(C)]
55
pub struct RTC1 {
66
pub tasks_start: VolatileCell<u32>,
77
pub tasks_stop: VolatileCell<u32>,
@@ -29,7 +29,7 @@ pub struct RTC1 {
2929
// FIXME: check registers and add TIMER3 and TIMER4
3030
pub const TIMER_SIZE: usize = 0x1000;
3131
pub const TIMER_BASE: usize = 0x40008000;
32-
#[repr(C, packed)]
32+
#[repr(C)]
3333
pub struct TIMER {
3434
pub task_start: VolatileCell<u32>,
3535
pub task_stop: VolatileCell<u32>,
@@ -55,7 +55,7 @@ pub struct TIMER {
5555
}
5656

5757
pub const AESECB_BASE: usize = 0x4000E000;
58-
#[repr(C, packed)]
58+
#[repr(C)]
5959
pub struct AESECB_REGS {
6060
pub task_startecb: VolatileCell<u32>, // 0x000 - 0x004
6161
pub task_stopecb: VolatileCell<u32>, // 0x004 - 0x008
@@ -70,7 +70,7 @@ pub struct AESECB_REGS {
7070
}
7171

7272
pub const GPIO_BASE: usize = 0x50000000;
73-
#[repr(C, packed)]
73+
#[repr(C)]
7474
pub struct GPIO {
7575
_reserved1: [u32; 321],
7676
pub out: VolatileCell<u32>,
@@ -85,7 +85,7 @@ pub struct GPIO {
8585
}
8686

8787
pub const TEMP_BASE: usize = 0x4000C000;
88-
#[repr(C, packed)]
88+
#[repr(C)]
8989
pub struct TEMP_REGS {
9090
pub task_start: VolatileCell<u32>, // 0x000 - 0x004
9191
pub task_stop: VolatileCell<u32>, // 0x004 - 0x008
@@ -100,7 +100,7 @@ pub struct TEMP_REGS {
100100
}
101101

102102
pub const RNG_BASE: usize = 0x4000D000;
103-
#[repr(C, packed)]
103+
#[repr(C)]
104104
pub struct RNG_REGS {
105105
pub task_start: VolatileCell<u32>, // 0x000 - 0x004
106106
pub task_stop: VolatileCell<u32>, // 0x004 - 0x008

‎chips/sam4l/src/adc.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -129,7 +129,7 @@ pub struct Adc {
129129
}
130130

131131
/// Memory mapped registers for the ADC.
132-
#[repr(C, packed)]
132+
#[repr(C)]
133133
pub struct AdcRegisters {
134134
// From page 1005 of SAM4L manual
135135
pub cr: VolatileCell<u32>, // Control (0x00)

‎chips/sam4l/src/aes.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ use pm;
99
use scif;
1010

1111
/// The registers used to interface with the hardware
12-
#[repr(C, packed)]
12+
#[repr(C)]
1313
struct AesRegisters {
1414
ctrl: VolatileCell<u32>, // 0x00
1515
mode: VolatileCell<u32>, // 0x04

‎chips/sam4l/src/ast.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ use pm::{self, PBDClock};
2626
/// tics. Seems safe enough and in practice has seemed to work.
2727
const ALARM0_SYNC_TICS: u32 = 8;
2828

29-
#[repr(C, packed)]
29+
#[repr(C)]
3030
struct AstRegisters {
3131
cr: VolatileCell<u32>,
3232
cv: VolatileCell<u32>,

‎chips/sam4l/src/bpm.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
33
use kernel::common::VolatileCell;
44

5-
#[repr(C, packed)]
5+
#[repr(C)]
66
struct BpmRegisters {
77
interrupt_enable: VolatileCell<u32>,
88
interrupt_disable: VolatileCell<u32>,

‎chips/sam4l/src/bscif.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
33
use kernel::common::VolatileCell;
44

5-
#[repr(C, packed)]
5+
#[repr(C)]
66
struct BscifRegisters {
77
ier: VolatileCell<u32>,
88
idr: VolatileCell<u32>,

‎chips/sam4l/src/crccu.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -124,7 +124,7 @@ registers![
124124
];
125125

126126
// CRCCU Descriptor (from Table 41.2 in Section 41.6):
127-
#[repr(C, packed)]
127+
#[repr(C)]
128128
struct Descriptor {
129129
addr: u32, // Transfer Address Register (RW): Address of memory block to compute
130130
ctrl: TCR, // Transfer Control Register (RW): IEN, TRWIDTH, BTSIZE
@@ -134,7 +134,7 @@ struct Descriptor {
134134

135135
// Transfer Control Register (see Section 41.6.18)
136136
#[derive(Copy, Clone)]
137-
#[repr(C, packed)]
137+
#[repr(C)]
138138
struct TCR(u32);
139139

140140
impl TCR {

‎chips/sam4l/src/dac.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ use kernel::common::VolatileCell;
1111
use kernel::hil;
1212
use pm::{self, Clock, PBAClock};
1313

14-
#[repr(C, packed)]
14+
#[repr(C)]
1515
pub struct DacRegisters {
1616
// From page 905 of SAM4L manual
1717
cr: VolatileCell<u32>, // Control (0x00)

‎chips/sam4l/src/dma.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ use kernel::common::take_cell::TakeCell;
88
use pm;
99

1010
/// Memory registers for a DMA channel. Section 16.6.1 of the datasheet.
11-
#[repr(C, packed)]
11+
#[repr(C)]
1212
#[allow(dead_code)]
1313
struct DMARegisters {
1414
memory_address: VolatileCell<u32>, // 0x00

‎chips/sam4l/src/flashcalw.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ use kernel::hil;
3131
use pm;
3232

3333
/// Struct of the FLASHCALW registers. Section 14.10 of the datasheet.
34-
#[repr(C, packed)]
34+
#[repr(C)]
3535
struct FlashcalwRegisters {
3636
fcr: VolatileCell<u32>,
3737
fcmd: VolatileCell<u32>,

‎chips/sam4l/src/gpio.rs

+3-3
Original file line numberDiff line numberDiff line change
@@ -7,23 +7,23 @@ use core::sync::atomic::{AtomicUsize, Ordering};
77
use kernel::common::VolatileCell;
88
use kernel::hil;
99

10-
#[repr(C, packed)]
10+
#[repr(C)]
1111
struct Register {
1212
val: VolatileCell<u32>,
1313
set: VolatileCell<u32>,
1414
clear: VolatileCell<u32>,
1515
toggle: VolatileCell<u32>,
1616
}
1717

18-
#[repr(C, packed)]
18+
#[repr(C)]
1919
struct RegisterRC {
2020
val: VolatileCell<u32>,
2121
reserved0: u32,
2222
clear: VolatileCell<u32>,
2323
reserved1: u32,
2424
}
2525

26-
#[repr(C, packed)]
26+
#[repr(C)]
2727
struct Registers {
2828
gper: Register,
2929
pmr0: Register,

‎chips/sam4l/src/i2c.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ use pm;
1919

2020
// Listing of all registers related to the TWIM peripheral.
2121
// Section 27.9 of the datasheet
22-
#[repr(C, packed)]
22+
#[repr(C)]
2323
#[allow(dead_code)]
2424
struct TWIMRegisters {
2525
control: VolatileCell<u32>,
@@ -43,7 +43,7 @@ struct TWIMRegisters {
4343

4444
// Listing of all registers related to the TWIS peripheral.
4545
// Section 28.9 of the datasheet
46-
#[repr(C, packed)]
46+
#[repr(C)]
4747
#[allow(dead_code)]
4848
struct TWISRegisters {
4949
control: VolatileCell<u32>,

‎chips/sam4l/src/pm.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ use gpio;
1010
use kernel::common::VolatileCell;
1111
use scif;
1212

13-
#[repr(C, packed)]
13+
#[repr(C)]
1414
struct PmRegisters {
1515
mcctrl: VolatileCell<u32>,
1616
cpusel: VolatileCell<u32>,

‎chips/sam4l/src/scif.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ pub enum GenericClock {
6363
GCLK11,
6464
}
6565

66-
#[repr(C, packed)]
66+
#[repr(C)]
6767
struct Registers {
6868
ier: VolatileCell<u32>,
6969
idr: VolatileCell<u32>,

‎chips/sam4l/src/spi.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ use kernel::hil::spi::SpiSlaveClient;
2424
use pm;
2525

2626
/// The registers used to interface with the hardware
27-
#[repr(C, packed)]
27+
#[repr(C)]
2828
struct SpiRegisters {
2929
cr: VolatileCell<u32>, // 0x0
3030
mr: VolatileCell<u32>, // 0x4

‎chips/sam4l/src/usart.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ use kernel::hil;
1313
use pm;
1414

1515
// Register map for SAM4L USART
16-
#[repr(C, packed)]
16+
#[repr(C)]
1717
struct USARTRegisters {
1818
cr: VolatileCell<u32>, // 0x00
1919
mr: VolatileCell<u32>,

‎chips/sam4l/src/wdt.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ use kernel::common::VolatileCell;
55
use kernel::hil;
66
use pm::{self, Clock, PBDClock};
77

8-
#[repr(C, packed)]
8+
#[repr(C)]
99
pub struct WdtRegisters {
1010
cr: VolatileCell<u32>,
1111
clr: VolatileCell<u32>,

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