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platform: nordic_nrf: Add initial support for nRF54L10
This adds nRF54L10 initial support for TF-M. This is NOT full upstream support. There are important limitations: - Hardware crypto acceleration with Cracen is not supported - Random number generation with Cracen is not supported - The tests suites PSA arch tests and TF-M regression tests are not tested - BL2 is not supported - Some soc related configurations are not supported and they rely on hard-coded values (check nordicsemi_nrf54l_init for more info) This was tested using some basic Zephyr samples. Only one flash/RAM layout is supported at the moment. This adds the same level of support with the nRF54L15, the configuration is nearly identical, the main difference is the partitioning scheme since these devices have different RRAM/RAM sizes. Signed-off-by: Georgios Vasilakis <[email protected]> Change-Id: I396d0d570ebd9b471138b7f02019bc0a1279e0d1 (cherry picked from commit d301766)
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‎platform/ext/target/nordic_nrf/common/core/CMakeLists.txt

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# At the time of writing there is no systematic way to identify which
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# NVM technology is used by the SoC from the Kconfig, so we just
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# hardcode this information here instead.
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if((NRF_SOC_VARIANT STREQUAL nrf54l15) OR (TFM_PLATFORM STREQUAL "nordic_nrf/nrf54l15dk_nrf54l15_cpuapp") OR (PSA_API_TEST_TARGET STREQUAL nrf54l15))
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if((NRF_SOC_VARIANT MATCHES "^nrf54l1[05]$") OR (TFM_PLATFORM MATCHES "nordic\_nrf\/nrf54l15dk\_nrf54l1[05]\_cpuapp") OR (PSA_API_TEST_TARGET MATCHES "^nrf54l1[05]$"))
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# Maybe we only need to check one of these options but these
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# variables keep changing so we check both to be future proof
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set(HAS_RRAMC 1)

‎platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt

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#-------------------------------------------------------------------------------
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# Copyright (c) 2020-2022, Arm Limited. All rights reserved.
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# Copyright (c) 2020, Nordic Semiconductor ASA.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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#-------------------------------------------------------------------------------
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cmake_policy(SET CMP0076 NEW)
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set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR})
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set(target nrf54l)
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add_subdirectory(../core nrf_common)
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#========================= Platform Secure ====================================#
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target_include_directories(platform_s
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PUBLIC
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.
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../nrf54l
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)
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target_sources(platform_s
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PRIVATE
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${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c
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../nrf54l/nrf54l_init.c
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)
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target_compile_definitions(platform_s
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PUBLIC
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NRF_SKIP_FICR_NS_COPY_TO_RAM
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)
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#========================= tfm_spm ============================================#
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target_sources(tfm_spm
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PRIVATE
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$<$<OR:$<BOOL:${CONFIG_TFM_FLIH_API}>,$<BOOL:${CONFIG_TFM_SLIH_API}>>:${CMAKE_CURRENT_SOURCE_DIR}/../nrf54l/tfm_interrupts.c>
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)
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#========================= Files for building NS side platform ================#
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install(FILES ../nrf54l/nrfx_config_nrf54l.h
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ns/CMakeLists.txt
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config.cmake
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cpuarch.cmake
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DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54l10
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)
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install(DIRECTORY partition
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tests
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DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54l10
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)

‎platform/ext/target/nordic_nrf/common/nrf54l10/config.cmake

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#-------------------------------------------------------------------------------
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# Copyright (c) 2020, Nordic Semiconductor ASA.
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# Copyright (c) 2020-2023, Arm Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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#-------------------------------------------------------------------------------
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include(${PLATFORM_PATH}/common/nrf54l/config.cmake)
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‎platform/ext/target/nordic_nrf/common/nrf54l10/cpuarch.cmake

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#
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# Copyright (c) 2023, Nordic Semiconductor ASA.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# cpuarch.cmake is used to set things that related to the platform that are both
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# immutable and global, which is to say they should apply to any kind of project
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# that uses this platform. In practice this is normally compiler definitions and
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# variables related to hardware.
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# Set architecture and CPU
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set(TFM_SYSTEM_PROCESSOR cortex-m33)
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set(TFM_SYSTEM_ARCHITECTURE armv8-m.main)
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set(CONFIG_TFM_FP_ARCH "fpv5-sp-d16")
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add_compile_definitions(
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NRF54L10_XXAA
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NRF54L_SERIES
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NRF_APPLICATION
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# SKIP configuring the SAU from the MDK as it does not fit TF-M's needs
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NRF_SKIP_SAU_CONFIGURATION
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NRF_SKIP_FICR_NS_COPY_TO_RAM
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)

‎platform/ext/target/nordic_nrf/common/nrf54l10/ns/CMakeLists.txt

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#-------------------------------------------------------------------------------
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# Copyright (c) 2023, Arm Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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#-------------------------------------------------------------------------------
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cmake_policy(SET CMP0076 NEW)
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set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR})
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set(target nrf54l)
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add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../core nrf_common)
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target_include_directories(platform_ns
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PUBLIC
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${CMAKE_CURRENT_LIST_DIR}
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)
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target_sources(platform_ns
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PRIVATE
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${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c
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)
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target_compile_definitions(platform_ns
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PUBLIC
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NRF_TRUSTZONE_NONSECURE
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NRF_SKIP_CLOCK_CONFIGURATION
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DOMAIN_NS=1
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)

‎platform/ext/target/nordic_nrf/common/nrf54l10/partition/flash_layout.h

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __FLASH_LAYOUT_H__
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#define __FLASH_LAYOUT_H__
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#ifdef BL2
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#error "BL2 is not supported for this platform"
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#endif
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/* Flash layout on NRF54L15 Application MCU without BL2:
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*
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* 0x0000_0000 Secure image primary (384 KB)
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* 0x0006_0000 Protected Storage Area (16 KB)
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* 0x0006_4000 Internal Trusted Storage Area (16 KB)
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* 0x0006_8000 OTP / NV counters area (8 KB)
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* 0x0006_A000 Non-secure image primary (504 KB)
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* 0x000E_8000 Non-secure storage, used when built with NRF_NS_STORAGE=ON,
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* otherwise unused (32 KB)
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*/
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/* This header file is included from linker scatter file as well, where only a
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* limited C constructs are allowed. Therefore it is not possible to include
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* here the platform_base_address.h to access flash related defines. To resolve
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* this some of the values are redefined here with different names, these are
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* marked with comment.
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*/
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/* Use Flash memory to store Code data */
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#define FLASH_BASE_ADDRESS (0x0)
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/* nRF54L10 has 1022 kB of non volatile memory (RRAM) but the last 62kB are reserved
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* for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along
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* with TF-M later FLPR non volatile memory is not used by TF-M. */
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#define FLASH_TOTAL_SIZE (0xF0000) /* 960 kB since the last 62kB are reserved for FLPR */
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#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE
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/* nRF54L10 has 192 kB of volatile memory (SRAM) but the last 48kB are reserved
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* for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along
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* with TF-M later FLPR volatile memory is not used by TF-M. */
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#define SRAM_BASE_ADDRESS (0x20000000)
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#define TOTAL_RAM_SIZE (0x00024000) /* 144 kB since the last 48kB are reserved for FLPR */
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#define FLASH_S_PARTITION_SIZE (0x60000) /* S partition: 384 kB*/
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#define FLASH_NS_PARTITION_SIZE (0x7E000) /* NS partition: 504 kB*/
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#define S_ROM_ALIAS_BASE FLASH_BASE_ADDRESS
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#define NS_ROM_ALIAS_BASE FLASH_BASE_ADDRESS
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/* Use SRAM memory to store RW data */
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#define S_RAM_ALIAS_BASE SRAM_BASE_ADDRESS
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#define NS_RAM_ALIAS_BASE SRAM_BASE_ADDRESS
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/* Sector size of the embedded flash hardware (erase/program) */
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#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB. Flash memory program/erase operations have a page granularity. */
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#if (FLASH_S_PARTITION_SIZE > FLASH_NS_PARTITION_SIZE)
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#define FLASH_MAX_PARTITION_SIZE FLASH_S_PARTITION_SIZE
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#else
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#define FLASH_MAX_PARTITION_SIZE FLASH_NS_PARTITION_SIZE
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#endif
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/* Offset and size definition in flash area used by assemble.py */
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#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE
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#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE
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#define SECURE_STORAGE_PARTITIONS_START (FLASH_BASE_ADDRESS + FLASH_S_PARTITION_SIZE)
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/* Protected Storage (PS) Service definitions */
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#define FLASH_PS_AREA_OFFSET (SECURE_STORAGE_PARTITIONS_START)
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#define FLASH_PS_AREA_SIZE (0x4000) /* 16 KB */
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/* Internal Trusted Storage (ITS) Service definitions */
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#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + FLASH_PS_AREA_SIZE)
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#define FLASH_ITS_AREA_SIZE (0x4000) /* 16 KB */
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/* OTP_definitions */
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#define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + FLASH_ITS_AREA_SIZE)
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#define FLASH_OTP_NV_COUNTERS_AREA_SIZE (0x2000) /* 8KB */
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#define FLASH_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE
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#define SECURE_STORAGE_PARTITIONS_END (FLASH_OTP_NV_COUNTERS_AREA_OFFSET + FLASH_OTP_NV_COUNTERS_AREA_SIZE)
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/* END OF PARTITIONS LAYOUT */
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#define SECURE_IMAGE_OFFSET (0x0)
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#define NON_SECURE_IMAGE_OFFSET (SECURE_STORAGE_PARTITIONS_END)
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/* Non-secure storage region */
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#define NRF_FLASH_NS_STORAGE_AREA_SIZE (0x8000) /* 32 KB */
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#define NRF_FLASH_NS_STORAGE_AREA_OFFSET (FLASH_TOTAL_SIZE - \
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NRF_FLASH_NS_STORAGE_AREA_SIZE)
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/* Flash device name used by BL2
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* Name is defined in flash driver file: Driver_Flash.c
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*/
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//#define FLASH_DEV_NAME Driver_FLASH0
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/* Smallest flash programmable unit in bytes */
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#define TFM_HAL_FLASH_PROGRAM_UNIT (0x4)
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/* Protected Storage (PS) Service definitions
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* Note: Further documentation of these definitions can be found in the
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* TF-M PS Integration Guide.
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*/
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#define TFM_HAL_PS_FLASH_DRIVER Driver_FLASH0
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/* In this target the CMSIS driver requires only the offset from the base
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* address instead of the full memory address.
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*/
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/* Base address of dedicated flash area for PS */
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#define TFM_HAL_PS_FLASH_AREA_ADDR FLASH_PS_AREA_OFFSET
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/* Size of dedicated flash area for PS */
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#define TFM_HAL_PS_FLASH_AREA_SIZE FLASH_PS_AREA_SIZE
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#define PS_RAM_FS_SIZE TFM_HAL_PS_FLASH_AREA_SIZE
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/* Number of physical erase sectors per logical FS block */
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#define TFM_HAL_PS_SECTORS_PER_BLOCK (1)
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/* Smallest flash programmable unit in bytes */
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#define TFM_HAL_PS_PROGRAM_UNIT (0x4)
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/* Internal Trusted Storage (ITS) Service definitions
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* Note: Further documentation of these definitions can be found in the
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* TF-M ITS Integration Guide. The ITS should be in the internal flash, but is
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* allocated in the external flash just for development platforms that don't
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* have internal flash available.
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*/
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#define TFM_HAL_ITS_FLASH_DRIVER Driver_FLASH0
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/* In this target the CMSIS driver requires only the offset from the base
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* address instead of the full memory address.
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*/
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/* Base address of dedicated flash area for ITS */
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#define TFM_HAL_ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET
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/* Size of dedicated flash area for ITS */
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#define TFM_HAL_ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE
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#define ITS_RAM_FS_SIZE TFM_HAL_ITS_FLASH_AREA_SIZE
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/* Number of physical erase sectors per logical FS block */
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#define TFM_HAL_ITS_SECTORS_PER_BLOCK (1)
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/* Smallest flash programmable unit in bytes */
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#define TFM_HAL_ITS_PROGRAM_UNIT (0x4)
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/* OTP / NV counter definitions */
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#define TFM_OTP_NV_COUNTERS_AREA_SIZE (FLASH_OTP_NV_COUNTERS_AREA_SIZE / 2)
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#define TFM_OTP_NV_COUNTERS_AREA_ADDR FLASH_OTP_NV_COUNTERS_AREA_OFFSET
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#define TFM_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_OTP_NV_COUNTERS_SECTOR_SIZE
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#define TFM_OTP_NV_COUNTERS_BACKUP_AREA_ADDR (TFM_OTP_NV_COUNTERS_AREA_ADDR + \
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TFM_OTP_NV_COUNTERS_AREA_SIZE)
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#endif /* __FLASH_LAYOUT_H__ */

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