We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
1 parent 388fa47 commit f93a1ceCopy full SHA for f93a1ce
README.md
@@ -18,5 +18,5 @@ The goal of this project is to demonstrate a SystemVerilog project with:
18
* Code coverage published in CodeCov.
19
20
Support:
21
- * [wsnyder](https://github.com/wsnyder)
+ * [Verilator Forum](https://verilator.org/forum)
22
* [Codecov community boards](https://community.codecov.io)
0 commit comments