-
Notifications
You must be signed in to change notification settings - Fork 297
/
Copy pathpixel-a.asm
16583 lines (14948 loc) · 412 KB
/
pixel-a.asm
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
;*****************************************************************************
;* pixel.asm: x86 pixel metrics
;*****************************************************************************
;* Copyright (C) 2003-2013 x264 project
;* Copyright (C) 2013-2020 MulticoreWare, Inc
;*
;* Authors: Loren Merritt <[email protected]>
;* Holger Lubitz <[email protected]>
;* Laurent Aimar <[email protected]>
;* Alex Izvorski <[email protected]>
;* Fiona Glaser <[email protected]>
;* Oskar Arvidsson <[email protected]>
;* Min Chen <[email protected]>
;*
;* This program is free software; you can redistribute it and/or modify
;* it under the terms of the GNU General Public License as published by
;* the Free Software Foundation; either version 2 of the License, or
;* (at your option) any later version.
;*
;* This program is distributed in the hope that it will be useful,
;* but WITHOUT ANY WARRANTY; without even the implied warranty of
;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;* GNU General Public License for more details.
;*
;* You should have received a copy of the GNU General Public License
;* along with this program; if not, write to the Free Software
;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111, USA.
;*
;* This program is also available under a commercial proprietary license.
;* For more information, contact us at license @ x265.com.
;*****************************************************************************
%include "x86inc.asm"
%include "x86util.asm"
SECTION_RODATA 32
hmul_8p: times 8 db 1
times 4 db 1, -1
times 8 db 1
times 4 db 1, -1
hmul_4p: times 4 db 1, 1, 1, 1, 1, -1, 1, -1
mask_10: times 4 dw 0, -1
mask_1100: times 2 dd 0, -1
hmul_8w: times 4 dw 1
times 2 dw 1, -1
times 4 dw 1
times 2 dw 1, -1
psy_pp_shuff1: dq 0, 1, 8, 9, 4, 5, 12, 13
psy_pp_shuff2: dq 2, 3, 10, 11, 6, 7, 14, 15
psy_pp_shuff3: dq 0, 0, 8, 8, 1, 1, 9, 9
ALIGN 32
transd_shuf1: SHUFFLE_MASK_W 0, 8, 2, 10, 4, 12, 6, 14
transd_shuf2: SHUFFLE_MASK_W 1, 9, 3, 11, 5, 13, 7, 15
SECTION .text
cextern pb_0
cextern pb_1
cextern pw_1
cextern pw_8
cextern pw_16
cextern pw_32
cextern pw_00ff
cextern pw_ppppmmmm
cextern pw_ppmmppmm
cextern pw_pmpmpmpm
cextern pw_pmmpzzzz
cextern pd_1
cextern pd_2
cextern hmul_16p
cextern pb_movemask
cextern pb_movemask_32
cextern pw_pixel_max
%if BIT_DEPTH == 12
%define SSIMRD_SHIFT 4
%elif BIT_DEPTH == 10
%define SSIMRD_SHIFT 2
%elif BIT_DEPTH == 8
%define SSIMRD_SHIFT 0
%else
%error Unsupported BIT_DEPTH!
%endif
;=============================================================================
; SATD
;=============================================================================
%macro JDUP 2
%if cpuflag(sse4)
; just use shufps on anything post conroe
shufps %1, %2, 0
%elif cpuflag(ssse3) && notcpuflag(atom)
; join 2x 32 bit and duplicate them
; emulating shufps is faster on conroe
punpcklqdq %1, %2
movsldup %1, %1
%else
; doesn't need to dup. sse2 does things by zero extending to words and full h_2d
punpckldq %1, %2
%endif
%endmacro
%macro HSUMSUB 5
pmaddubsw m%2, m%5
pmaddubsw m%1, m%5
pmaddubsw m%4, m%5
pmaddubsw m%3, m%5
%endmacro
%macro DIFF_UNPACK_SSE2 5
punpcklbw m%1, m%5
punpcklbw m%2, m%5
punpcklbw m%3, m%5
punpcklbw m%4, m%5
psubw m%1, m%2
psubw m%3, m%4
%endmacro
%macro DIFF_SUMSUB_SSSE3 5
HSUMSUB %1, %2, %3, %4, %5
psubw m%1, m%2
psubw m%3, m%4
%endmacro
%macro LOAD_DUP_2x4P 4 ; dst, tmp, 2* pointer
movd %1, %3
movd %2, %4
JDUP %1, %2
%endmacro
%macro LOAD_DUP_4x8P_CONROE 8 ; 4*dst, 4*pointer
movddup m%3, %6
movddup m%4, %8
movddup m%1, %5
movddup m%2, %7
%endmacro
%macro LOAD_DUP_4x8P_PENRYN 8
; penryn and nehalem run punpcklqdq and movddup in different units
movh m%3, %6
movh m%4, %8
punpcklqdq m%3, m%3
movddup m%1, %5
punpcklqdq m%4, m%4
movddup m%2, %7
%endmacro
%macro LOAD_SUMSUB_8x2P 9
LOAD_DUP_4x8P %1, %2, %3, %4, %6, %7, %8, %9
DIFF_SUMSUB_SSSE3 %1, %3, %2, %4, %5
%endmacro
%macro LOAD_SUMSUB_8x4P_SSSE3 7-11 r0, r2, 0, 0
; 4x dest, 2x tmp, 1x mul, [2* ptr], [increment?]
LOAD_SUMSUB_8x2P %1, %2, %5, %6, %7, [%8], [%9], [%8+r1], [%9+r3]
LOAD_SUMSUB_8x2P %3, %4, %5, %6, %7, [%8+2*r1], [%9+2*r3], [%8+r4], [%9+r5]
%if %10
lea %8, [%8+4*r1]
lea %9, [%9+4*r3]
%endif
%endmacro
%macro LOAD_SUMSUB_16P_SSSE3 7 ; 2*dst, 2*tmp, mul, 2*ptr
movddup m%1, [%7]
movddup m%2, [%7+8]
mova m%4, [%6]
movddup m%3, m%4
punpckhqdq m%4, m%4
DIFF_SUMSUB_SSSE3 %1, %3, %2, %4, %5
%endmacro
%macro LOAD_SUMSUB_16P_SSE2 7 ; 2*dst, 2*tmp, mask, 2*ptr
movu m%4, [%7]
mova m%2, [%6]
DEINTB %1, %2, %3, %4, %5
psubw m%1, m%3
psubw m%2, m%4
SUMSUB_BA w, %1, %2, %3
%endmacro
%macro LOAD_SUMSUB_16x4P 10-13 r0, r2, none
; 8x dest, 1x tmp, 1x mul, [2* ptr] [2nd tmp]
LOAD_SUMSUB_16P %1, %5, %2, %3, %10, %11, %12
LOAD_SUMSUB_16P %2, %6, %3, %4, %10, %11+r1, %12+r3
LOAD_SUMSUB_16P %3, %7, %4, %9, %10, %11+2*r1, %12+2*r3
LOAD_SUMSUB_16P %4, %8, %13, %9, %10, %11+r4, %12+r5
%endmacro
%macro LOAD_SUMSUB_16x2P_AVX2 9
; 2*dst, 2*tmp, mul, 4*ptr
vbroadcasti128 m%1, [%6]
vbroadcasti128 m%3, [%7]
vbroadcasti128 m%2, [%8]
vbroadcasti128 m%4, [%9]
DIFF_SUMSUB_SSSE3 %1, %3, %2, %4, %5
%endmacro
%macro LOAD_SUMSUB_16x4P_AVX2 7-11 r0, r2, 0, 0
; 4x dest, 2x tmp, 1x mul, [2* ptr], [increment?]
LOAD_SUMSUB_16x2P_AVX2 %1, %2, %5, %6, %7, %8, %9, %8+r1, %9+r3
LOAD_SUMSUB_16x2P_AVX2 %3, %4, %5, %6, %7, %8+2*r1, %9+2*r3, %8+r4, %9+r5
%if %10
lea %8, [%8+4*r1]
lea %9, [%9+4*r3]
%endif
%endmacro
%macro LOAD_DUP_4x16P_AVX2 8 ; 4*dst, 4*pointer
mova xm%3, %6
mova xm%4, %8
mova xm%1, %5
mova xm%2, %7
vpermq m%3, m%3, q0011
vpermq m%4, m%4, q0011
vpermq m%1, m%1, q0011
vpermq m%2, m%2, q0011
%endmacro
%macro LOAD_SUMSUB8_16x2P_AVX2 9
; 2*dst, 2*tmp, mul, 4*ptr
LOAD_DUP_4x16P_AVX2 %1, %2, %3, %4, %6, %7, %8, %9
DIFF_SUMSUB_SSSE3 %1, %3, %2, %4, %5
%endmacro
%macro LOAD_SUMSUB8_16x4P_AVX2 7-11 r0, r2, 0, 0
; 4x dest, 2x tmp, 1x mul, [2* ptr], [increment?]
LOAD_SUMSUB8_16x2P_AVX2 %1, %2, %5, %6, %7, [%8], [%9], [%8+r1], [%9+r3]
LOAD_SUMSUB8_16x2P_AVX2 %3, %4, %5, %6, %7, [%8+2*r1], [%9+2*r3], [%8+r4], [%9+r5]
%if %10
lea %8, [%8+4*r1]
lea %9, [%9+4*r3]
%endif
%endmacro
; in: r4=3*stride1, r5=3*stride2
; in: %2 = horizontal offset
; in: %3 = whether we need to increment pix1 and pix2
; clobber: m3..m7
; out: %1 = satd
%macro SATD_4x4_MMX 3
%xdefine %%n nn%1
%assign offset %2*SIZEOF_PIXEL
LOAD_DIFF m4, m3, none, [r0+ offset], [r2+ offset]
LOAD_DIFF m5, m3, none, [r0+ r1+offset], [r2+ r3+offset]
LOAD_DIFF m6, m3, none, [r0+2*r1+offset], [r2+2*r3+offset]
LOAD_DIFF m7, m3, none, [r0+ r4+offset], [r2+ r5+offset]
%if %3
lea r0, [r0+4*r1]
lea r2, [r2+4*r3]
%endif
HADAMARD4_2D 4, 5, 6, 7, 3, %%n
paddw m4, m6
;%if HIGH_BIT_DEPTH && (BIT_DEPTH == 12)
; pxor m5, m5
; punpcklwd m6, m4, m5
; punpckhwd m4, m5
; paddd m4, m6
;%endif
SWAP %%n, 4
%endmacro
; in: %1 = horizontal if 0, vertical if 1
%macro SATD_8x4_SSE 8-9
%if %1
HADAMARD4_2D_SSE %2, %3, %4, %5, %6, amax
%else
HADAMARD4_V %2, %3, %4, %5, %6
; doing the abs first is a slight advantage
ABSW2 m%2, m%4, m%2, m%4, m%6, m%7
ABSW2 m%3, m%5, m%3, m%5, m%6, m%7
HADAMARD 1, max, %2, %4, %6, %7
%endif
%ifnidn %9, swap
%if (BIT_DEPTH == 12)
pxor m%6, m%6
punpcklwd m%7, m%2, m%6
punpckhwd m%2, m%6
paddd m%8, m%7
paddd m%8, m%2
%else
paddw m%8, m%2
%endif
%else
SWAP %8, %2
%if (BIT_DEPTH == 12)
pxor m%6, m%6
punpcklwd m%7, m%8, m%6
punpckhwd m%8, m%6
paddd m%8, m%7
%endif
%endif
%if %1
%if (BIT_DEPTH == 12)
pxor m%6, m%6
punpcklwd m%7, m%4, m%6
punpckhwd m%4, m%6
paddd m%8, m%7
paddd m%8, m%4
%else
paddw m%8, m%4
%endif
%else
HADAMARD 1, max, %3, %5, %6, %7
%if (BIT_DEPTH == 12)
pxor m%6, m%6
punpcklwd m%7, m%3, m%6
punpckhwd m%3, m%6
paddd m%8, m%7
paddd m%8, m%3
%else
paddw m%8, m%3
%endif
%endif
%endmacro
%macro SATD_8x4_1_SSE 10
%if %1
HADAMARD4_2D_SSE %2, %3, %4, %5, %6, amax
%else
HADAMARD4_V %2, %3, %4, %5, %6
; doing the abs first is a slight advantage
ABSW2 m%2, m%4, m%2, m%4, m%6, m%7
ABSW2 m%3, m%5, m%3, m%5, m%6, m%7
HADAMARD 1, max, %2, %4, %6, %7
%endif
pxor m%10, m%10
punpcklwd m%9, m%2, m%10
paddd m%8, m%9
punpckhwd m%9, m%2, m%10
paddd m%8, m%9
%if %1
pxor m%10, m%10
punpcklwd m%9, m%4, m%10
paddd m%8, m%9
punpckhwd m%9, m%4, m%10
paddd m%8, m%9
%else
HADAMARD 1, max, %3, %5, %6, %7
pxor m%10, m%10
punpcklwd m%9, m%3, m%10
paddd m%8, m%9
punpckhwd m%9, m%3, m%10
paddd m%8, m%9
%endif
%endmacro
%macro SATD_START_MMX 0
FIX_STRIDES r1, r3
lea r4, [3*r1] ; 3*stride1
lea r5, [3*r3] ; 3*stride2
%endmacro
%macro SATD_END_MMX 0
%if HIGH_BIT_DEPTH
HADDUW m0, m1
movd eax, m0
%else ; !HIGH_BIT_DEPTH
pshufw m1, m0, q1032
paddw m0, m1
pshufw m1, m0, q2301
paddw m0, m1
movd eax, m0
and eax, 0xffff
%endif ; HIGH_BIT_DEPTH
EMMS
RET
%endmacro
%macro SSIM_DIST_HIGH 2
vpsrld m6, m0, SSIMRD_SHIFT
vpsubd m0, m1
vpmuldq m2, m0, m0
vpsrldq m0, m0, 4
vpmuldq m0, m0, m0
vpaddq m0, m2
vpmuldq m2, m6, m6
vpsrldq m6, m6, 4
vpmuldq m6, m6, m6
vpaddq m6, m2
vpaddq m4, m0
vpaddq m7, m6
%endmacro
%macro NORM_FACT_HIGH 1
vpsrld m1, m0, SSIMRD_SHIFT
vpmuldq m2, m1, m1
vpsrldq m1, m1, 4
vpmuldq m1, m1, m1
vpaddq m1, m2
vpaddq m3, m1
%endmacro
%macro SSIM_DIST_LOW 2
vpsrlw m6, m0, SSIMRD_SHIFT
vpsubw m0, m1
vpmaddwd m0, m0, m0
vpmaddwd m6, m6, m6
vpaddd m4, m0
vpaddd m7, m6
%endmacro
%macro NORM_FACT_LOW 1
vpsrlw m1, m0, SSIMRD_SHIFT
vpmaddwd m1, m1, m1
vpaddd m3, m1
%endmacro
; FIXME avoid the spilling of regs to hold 3*stride.
; for small blocks on x86_32, modify pixel pointer instead.
;-----------------------------------------------------------------------------
; int pixel_satd_16x16( uint8_t *, intptr_t, uint8_t *, intptr_t )
;-----------------------------------------------------------------------------
INIT_MMX mmx2
cglobal pixel_satd_4x4, 4,6
SATD_START_MMX
SATD_4x4_MMX m0, 0, 0
SATD_END_MMX
%macro SATD_START_SSE2 2-3 0
FIX_STRIDES r1, r3
%if HIGH_BIT_DEPTH && %3
pxor %2, %2
%elif cpuflag(ssse3) && notcpuflag(atom)
%if mmsize==32
mova %2, [hmul_16p]
%else
mova %2, [hmul_8p]
%endif
%endif
lea r4, [3*r1]
lea r5, [3*r3]
pxor %1, %1
%endmacro
%macro SATD_END_SSE2 1-2
%if HIGH_BIT_DEPTH
%if BIT_DEPTH == 12
HADDD %1, xm0
%else ; BIT_DEPTH == 12
HADDUW %1, xm0
%endif ; BIT_DEPTH == 12
%if %0 == 2
paddd %1, %2
%endif
%else
HADDW %1, xm7
%endif
movd eax, %1
RET
%endmacro
%macro SATD_ACCUM 3
%if HIGH_BIT_DEPTH
HADDUW %1, %2
paddd %3, %1
pxor %1, %1
%endif
%endmacro
%macro BACKUP_POINTERS 0
%if ARCH_X86_64
%if WIN64
PUSH r7
%endif
mov r6, r0
mov r7, r2
%endif
%endmacro
%macro RESTORE_AND_INC_POINTERS 0
%if ARCH_X86_64
lea r0, [r6+8*SIZEOF_PIXEL]
lea r2, [r7+8*SIZEOF_PIXEL]
%if WIN64
POP r7
%endif
%else
mov r0, r0mp
mov r2, r2mp
add r0, 8*SIZEOF_PIXEL
add r2, 8*SIZEOF_PIXEL
%endif
%endmacro
%macro SATD_4x8_SSE 3-4
%if HIGH_BIT_DEPTH
movh m0, [r0+0*r1]
movh m4, [r2+0*r3]
movh m1, [r0+1*r1]
movh m5, [r2+1*r3]
movhps m0, [r0+4*r1]
movhps m4, [r2+4*r3]
movh m2, [r0+2*r1]
movh m6, [r2+2*r3]
psubw m0, m4
movh m3, [r0+r4]
movh m4, [r2+r5]
lea r0, [r0+4*r1]
lea r2, [r2+4*r3]
movhps m1, [r0+1*r1]
movhps m5, [r2+1*r3]
movhps m2, [r0+2*r1]
movhps m6, [r2+2*r3]
psubw m1, m5
movhps m3, [r0+r4]
movhps m4, [r2+r5]
psubw m2, m6
psubw m3, m4
%else ; !HIGH_BIT_DEPTH
movd m4, [r2]
movd m5, [r2+r3]
movd m6, [r2+2*r3]
add r2, r5
movd m0, [r0]
movd m1, [r0+r1]
movd m2, [r0+2*r1]
add r0, r4
movd m3, [r2+r3]
JDUP m4, m3
movd m3, [r0+r1]
JDUP m0, m3
movd m3, [r2+2*r3]
JDUP m5, m3
movd m3, [r0+2*r1]
JDUP m1, m3
%if %1==0 && %2==1
mova m3, [hmul_4p]
DIFFOP 0, 4, 1, 5, 3
%else
DIFFOP 0, 4, 1, 5, 7
%endif
movd m5, [r2]
add r2, r5
movd m3, [r0]
add r0, r4
movd m4, [r2]
JDUP m6, m4
movd m4, [r0]
JDUP m2, m4
movd m4, [r2+r3]
JDUP m5, m4
movd m4, [r0+r1]
JDUP m3, m4
%if %1==0 && %2==1
mova m4, [hmul_4p]
DIFFOP 2, 6, 3, 5, 4
%else
DIFFOP 2, 6, 3, 5, 7
%endif
%endif ; HIGH_BIT_DEPTH
%if %0 == 4
SATD_8x4_1_SSE %1, 0, 1, 2, 3, 4, 5, 7, %3, %4
%else
SATD_8x4_SSE %1, 0, 1, 2, 3, 4, 5, 7, %3
%endif
%endmacro
;-----------------------------------------------------------------------------
; int pixel_satd_8x4( uint8_t *, intptr_t, uint8_t *, intptr_t )
;-----------------------------------------------------------------------------
%macro SATDS_SSE2 0
%define vertical ((notcpuflag(ssse3) || cpuflag(atom)) || HIGH_BIT_DEPTH)
%if cpuflag(ssse3) && (vertical==0 || HIGH_BIT_DEPTH)
cglobal pixel_satd_4x4, 4, 6, 6
SATD_START_MMX
mova m4, [hmul_4p]
LOAD_DUP_2x4P m2, m5, [r2], [r2+r3]
LOAD_DUP_2x4P m3, m5, [r2+2*r3], [r2+r5]
LOAD_DUP_2x4P m0, m5, [r0], [r0+r1]
LOAD_DUP_2x4P m1, m5, [r0+2*r1], [r0+r4]
DIFF_SUMSUB_SSSE3 0, 2, 1, 3, 4
HADAMARD 0, sumsub, 0, 1, 2, 3
HADAMARD 4, sumsub, 0, 1, 2, 3
HADAMARD 1, amax, 0, 1, 2, 3
HADDW m0, m1
movd eax, m0
RET
%endif
cglobal pixel_satd_4x8, 4, 6, 8
SATD_START_MMX
%if vertical==0
mova m7, [hmul_4p]
%endif
SATD_4x8_SSE vertical, 0, swap
%if BIT_DEPTH == 12
HADDD m7, m1
%else
HADDUW m7, m1
%endif
movd eax, m7
RET
cglobal pixel_satd_4x16, 4, 6, 8
SATD_START_MMX
%if vertical==0
mova m7, [hmul_4p]
%endif
SATD_4x8_SSE vertical, 0, swap
lea r0, [r0+r1*2*SIZEOF_PIXEL]
lea r2, [r2+r3*2*SIZEOF_PIXEL]
SATD_4x8_SSE vertical, 1, add
%if BIT_DEPTH == 12
HADDD m7, m1
%else
HADDUW m7, m1
%endif
movd eax, m7
RET
cglobal pixel_satd_8x8_internal
LOAD_SUMSUB_8x4P 0, 1, 2, 3, 4, 5, 7, r0, r2, 1, 0
SATD_8x4_SSE vertical, 0, 1, 2, 3, 4, 5, 6
%%pixel_satd_8x4_internal:
LOAD_SUMSUB_8x4P 0, 1, 2, 3, 4, 5, 7, r0, r2, 1, 0
SATD_8x4_SSE vertical, 0, 1, 2, 3, 4, 5, 6
ret
cglobal pixel_satd_8x8_internal2
%if WIN64
LOAD_SUMSUB_8x4P 0, 1, 2, 3, 4, 5, 7, r0, r2, 1, 0
SATD_8x4_1_SSE vertical, 0, 1, 2, 3, 4, 5, 6, 12, 13
%%pixel_satd_8x4_internal2:
LOAD_SUMSUB_8x4P 0, 1, 2, 3, 4, 5, 7, r0, r2, 1, 0
SATD_8x4_1_SSE vertical, 0, 1, 2, 3, 4, 5, 6, 12, 13
%else
LOAD_SUMSUB_8x4P 0, 1, 2, 3, 4, 5, 7, r0, r2, 1, 0
SATD_8x4_1_SSE vertical, 0, 1, 2, 3, 4, 5, 6, 4, 5
%%pixel_satd_8x4_internal2:
LOAD_SUMSUB_8x4P 0, 1, 2, 3, 4, 5, 7, r0, r2, 1, 0
SATD_8x4_1_SSE vertical, 0, 1, 2, 3, 4, 5, 6, 4, 5
%endif
ret
; 16x8 regresses on phenom win64, 16x16 is almost the same (too many spilled registers)
; These aren't any faster on AVX systems with fast movddup (Bulldozer, Sandy Bridge)
%if HIGH_BIT_DEPTH == 0 && (WIN64 || UNIX64) && notcpuflag(avx)
cglobal pixel_satd_16x4_internal2
LOAD_SUMSUB_16x4P 0, 1, 2, 3, 4, 8, 5, 9, 6, 7, r0, r2, 11
lea r2, [r2+4*r3]
lea r0, [r0+4*r1]
SATD_8x4_1_SSE 0, 0, 1, 2, 3, 6, 11, 10, 12, 13
SATD_8x4_1_SSE 0, 4, 8, 5, 9, 6, 3, 10, 12, 13
ret
cglobal pixel_satd_16x4, 4,6,14
SATD_START_SSE2 m10, m7
%if vertical
mova m7, [pw_00ff]
%endif
call pixel_satd_16x4_internal2
HADDD m10, m0
movd eax, m10
RET
cglobal pixel_satd_16x8, 4,6,14
SATD_START_SSE2 m10, m7
%if vertical
mova m7, [pw_00ff]
%endif
jmp %%pixel_satd_16x8_internal
cglobal pixel_satd_16x12, 4,6,14
SATD_START_SSE2 m10, m7
%if vertical
mova m7, [pw_00ff]
%endif
call pixel_satd_16x4_internal2
jmp %%pixel_satd_16x8_internal
cglobal pixel_satd_16x32, 4,6,14
SATD_START_SSE2 m10, m7
%if vertical
mova m7, [pw_00ff]
%endif
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
jmp %%pixel_satd_16x8_internal
cglobal pixel_satd_16x64, 4,6,14
SATD_START_SSE2 m10, m7
%if vertical
mova m7, [pw_00ff]
%endif
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
jmp %%pixel_satd_16x8_internal
cglobal pixel_satd_16x16, 4,6,14
SATD_START_SSE2 m10, m7
%if vertical
mova m7, [pw_00ff]
%endif
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
%%pixel_satd_16x8_internal:
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
HADDD m10, m0
movd eax, m10
RET
cglobal pixel_satd_32x8, 4,8,14 ;if WIN64 && notcpuflag(avx)
SATD_START_SSE2 m10, m7
mov r6, r0
mov r7, r2
%if vertical
mova m7, [pw_00ff]
%endif
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
lea r0, [r6 + 16]
lea r2, [r7 + 16]
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
HADDD m10, m0
movd eax, m10
RET
cglobal pixel_satd_32x16, 4,8,14 ;if WIN64 && notcpuflag(avx)
SATD_START_SSE2 m10, m7
mov r6, r0
mov r7, r2
%if vertical
mova m7, [pw_00ff]
%endif
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
lea r0, [r6 + 16]
lea r2, [r7 + 16]
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
HADDD m10, m0
movd eax, m10
RET
cglobal pixel_satd_32x24, 4,8,14 ;if WIN64 && notcpuflag(avx)
SATD_START_SSE2 m10, m7
mov r6, r0
mov r7, r2
%if vertical
mova m7, [pw_00ff]
%endif
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
lea r0, [r6 + 16]
lea r2, [r7 + 16]
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
HADDD m10, m0
movd eax, m10
RET
cglobal pixel_satd_32x32, 4,8,14 ;if WIN64 && notcpuflag(avx)
SATD_START_SSE2 m10, m7
mov r6, r0
mov r7, r2
%if vertical
mova m7, [pw_00ff]
%endif
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
lea r0, [r6 + 16]
lea r2, [r7 + 16]
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
HADDD m10, m0
movd eax, m10
RET
cglobal pixel_satd_32x64, 4,8,14 ;if WIN64 && notcpuflag(avx)
SATD_START_SSE2 m10, m7
mov r6, r0
mov r7, r2
%if vertical
mova m7, [pw_00ff]
%endif
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
lea r0, [r6 + 16]
lea r2, [r7 + 16]
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
HADDD m10, m0
movd eax, m10
RET
cglobal pixel_satd_48x64, 4,8,14 ;if WIN64 && notcpuflag(avx)
SATD_START_SSE2 m10, m7
mov r6, r0
mov r7, r2
%if vertical
mova m7, [pw_00ff]
%endif
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
lea r0, [r6 + 16]
lea r2, [r7 + 16]
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
lea r0, [r6 + 32]
lea r2, [r7 + 32]
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
HADDD m10, m0
movd eax, m10
RET
cglobal pixel_satd_64x16, 4,8,14 ;if WIN64 && notcpuflag(avx)
SATD_START_SSE2 m10, m7
mov r6, r0
mov r7, r2
%if vertical
mova m7, [pw_00ff]
%endif
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
lea r0, [r6 + 16]
lea r2, [r7 + 16]
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
lea r0, [r6 + 32]
lea r2, [r7 + 32]
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
lea r0, [r6 + 48]
lea r2, [r7 + 48]
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
HADDD m10, m0
movd eax, m10
RET
cglobal pixel_satd_64x32, 4,8,14 ;if WIN64 && notcpuflag(avx)
SATD_START_SSE2 m10, m7
mov r6, r0
mov r7, r2
%if vertical
mova m7, [pw_00ff]
%endif
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
lea r0, [r6 + 16]
lea r2, [r7 + 16]
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
lea r0, [r6 + 32]
lea r2, [r7 + 32]
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
call pixel_satd_16x4_internal2
lea r0, [r6 + 48]