Merge from 'sycl' to 'sycl-web'

Author: iclsrc

README.md

@@ -1,37 +1,30 @@
 # Intel Project for LLVM\* technology
 
-## Introduction
+Intel staging area for llvm.org contribution. Home for Intel LLVM-based projects:
 
-Intel staging area for llvm.org contribution.
-Home for Intel LLVM-based projects:
+## oneAPI Data Parallel C++ compiler
 
-* oneAPI Data Parallel C++ compiler - see
-  [sycl](https://github.com/intel/llvm/tree/sycl) branch. More information on
-  oneAPI and DPC++ is available at
-  [https://www.oneapi.com/](https://www.oneapi.com/)
-  * [![Linux Post Commit Checks](https://github.com/intel/llvm/workflows/Linux%20Post%20Commit%20Checks/badge.svg)](https://github.com/intel/llvm/actions?query=workflow%3A%22Linux+Post+Commit+Checks%22)
-    [![Generate Doxygen documentation](https://github.com/intel/llvm/workflows/Generate%20Doxygen%20documentation/badge.svg)](https://github.com/intel/llvm/actions?query=workflow%3A%22Generate+Doxygen+documentation%22)
-* Late-outline OpenMP\* and OpenMP\* Offload - see
-  [openmp](https://github.com/intel/llvm/tree/openmp) branch.
+[![](https://spec.oneapi.io/oneapi-logo-white-scaled.jpg)](https://www.oneapi.io/)
 
-## License
+See [sycl](https://github.com/intel/llvm/tree/sycl) branch and
+[DPC++ Documentation](https://intel.github.io/llvm-docs/).
 
-See [LICENSE.txt](sycl/LICENSE.TXT) for details.
+[![Linux Post Commit Checks](https://github.com/intel/llvm/workflows/Linux%20Post%20Commit%20Checks/badge.svg)](https://github.com/intel/llvm/actions?query=workflow%3A%22Linux+Post+Commit+Checks%22)
+[![Generate Doxygen documentation](https://github.com/intel/llvm/workflows/Generate%20Doxygen%20documentation/badge.svg)](https://github.com/intel/llvm/actions?query=workflow%3A%22Generate+Doxygen+documentation%22)
 
-## Contributing
+DPC++ is an open, cross-architecture language built upon the ISO C++ and Khronos
+SYCL\* standards. DPC++ extends these standards with a number of extensions,
+which can be found in [sycl/doc/extensions](sycl/doc/extensions) directory.
 
-See [CONTRIBUTING.md](CONTRIBUTING.md) for details.
+## Late-outline OpenMP\* and OpenMP\* Offload
+See [openmp](https://github.com/intel/llvm/tree/openmp) branch.
 
-## Sub-projects Documentation
+# License
 
-* oneAPI Data Parallel C++ compiler - See
-  [DPC++ Documentation](https://intel.github.io/llvm-docs/)
-* Late-outline OpenMP\* and OpenMP\* Offload - TBD
+See [LICENSE.txt](sycl/LICENSE.TXT) for details.
 
-## DPC++ extensions
+# Contributing
 
-DPC++ is an open, cross-architecture language built upon the ISO C++ and Khronos
-SYCL\* standards. DPC++ extends these standards with a number of extensions,
-which can be found in [sycl/doc/extensions](sycl/doc/extensions) directory.
+See [CONTRIBUTING.md](CONTRIBUTING.md) for details.
 
 *\*Other names and brands may be claimed as the property of others.*

buildbot/configure.py

@@ -61,6 +61,9 @@ def do_configure(args):
         if args.rocm_platform == 'AMD':
             llvm_targets_to_build += ';AMDGPU'
             libclc_targets_to_build += ';amdgcn--;amdgcn--amdhsa'
+
+            # The ROCm plugin for AMD uses lld for linking
+            llvm_enable_projects += ';lld'
         elif args.rocm_platform == 'NVIDIA' and not args.cuda:
             llvm_targets_to_build += ';NVPTX'
             libclc_targets_to_build += ';nvptx64--;nvptx64--nvidiacl'

buildbot/dependency.conf

@@ -7,9 +7,8 @@ ocl_cpu_rt_ver_win=2021.12.6.0.19
 # https://github.com/intel/compute-runtime/releases/tag/21.33.20678
 ocl_gpu_rt_ver=21.33.20678
 # Same GPU driver supports Level Zero and OpenCL
-# https://downloadmirror.intel.com/30579/a08/igfx_win_100.9684.zip
-# https://downloadmirror.intel.com/30381/a08/igfx_win10_100.9466.zip
-ocl_gpu_rt_ver_win=30.0.100.9684
+# https://downloadmirror.intel.com/646152/igfx_win_100.9805.zip
+ocl_gpu_rt_ver_win=30.0.100.9805
 intel_sycl_ver=build
 
 # TBB binaries can be built from sources following instructions under
@@ -32,7 +31,7 @@ ocloc_ver_win=27.20.100.9168
 cpu_driver_lin=2021.12.6.0.19
 cpu_driver_win=2021.12.6.0.19
 gpu_driver_lin=21.33.20678
-gpu_driver_win=30.0.100.9684
+gpu_driver_win=30.0.100.9805
 fpga_driver_lin=2021.12.6.0.19
 fpga_driver_win=2021.12.6.0.19
 # NVidia CUDA driver

clang/lib/Driver/Driver.cpp

@@ -2932,6 +2932,18 @@ bool Driver::checkForSYCLDefaultDevice(Compilation &C,
   if (Args.hasArg(options::OPT_fno_sycl_link_spirv))
     return false;
 
+  // Do not do the check if the default device is passed in -fsycl-targets
+  // or if -fsycl-targets isn't passed (that implies default device)
+  if (const Arg *A = Args.getLastArg(options::OPT_fsycl_targets_EQ)) {
+    for (const char *Val : A->getValues()) {
+      llvm::Triple TT(C.getDriver().MakeSYCLDeviceTriple(Val));
+      if (TT.isSPIR() && TT.getSubArch() == llvm::Triple::NoSubArch)
+        // Default triple found
+        return false;
+    }
+  } else if (!Args.hasArg(options::OPT_fintelfpga))
+    return false;
+
   SmallVector<const char *, 16> AllArgs(getLinkerArgs(C, Args, true));
   for (StringRef Arg : AllArgs) {
     if (hasSYCLDefaultSection(C, Arg))
@@ -4388,12 +4400,15 @@ class OffloadingActionBuilder final {
                           TT.getSubArch() == llvm::Triple::SPIRSubArch_gen ||
                           TT.getSubArch() == llvm::Triple::SPIRSubArch_x86_64;
         for (const auto &Input : LI) {
-          // FPGA aoco does not go through the link, everything else does.
-          if (Input->getType() == types::TY_FPGA_AOCO)
-            DeviceLibObjects.push_back(Input);
-          // FPGA aocr/aocx does not go through the link and is passed
-          // directly to the backend compilation step (aocr) or wrapper (aocx)
-          else if (types::isFPGA(Input->getType())) {
+          if (TT.getSubArch() == llvm::Triple::SPIRSubArch_fpga &&
+              types::isFPGA(Input->getType())) {
+            // FPGA aoco does not go through the link, everything else does.
+            if (Input->getType() == types::TY_FPGA_AOCO) {
+              DeviceLibObjects.push_back(Input);
+              continue;
+            }
+            // FPGA aocr/aocx does not go through the link and is passed
+            // directly to the backend compilation step (aocr) or wrapper (aocx)
             Action *FPGAAOTAction;
             if (Input->getType() == types::TY_FPGA_AOCR ||
                 Input->getType() == types::TY_FPGA_AOCR_EMU)
@@ -4413,7 +4428,8 @@ class OffloadingActionBuilder final {
                 RenameAction, types::TY_Object);
             DA.add(*DeviceWrappingAction, **TC, /*BoundArch=*/nullptr,
                    Action::OFK_SYCL);
-          } else
+            continue;
+          } else if (!types::isFPGA(Input->getType()))
             LinkObjects.push_back(Input);
         }
         if (LinkObjects.empty())
@@ -5488,6 +5504,16 @@ void Driver::BuildActions(Compilation &C, DerivedArgList &Args,
         break;
       }
 
+      // When performing -fsycl based compilations and generating dependency
+      // information, perform a specific dependency generation compilation which
+      // is not based on the source + footer compilation.
+      if (Phase == phases::Preprocess && Args.hasArg(options::OPT_fsycl) &&
+          Args.hasArg(options::OPT_M_Group) &&
+          !Args.hasArg(options::OPT_fno_sycl_use_footer)) {
+        Actions.push_back(
+            C.MakeAction<PreprocessJobAction>(Current, types::TY_Dependencies));
+      }
+
       // FIXME: Should we include any prior module file outputs as inputs of
       // later actions in the same command line?
 
@@ -5852,6 +5878,9 @@ void Driver::BuildJobs(Compilation &C) const {
   // we are also generating .o files. So we allow more than one output file in
   // this case as well.
   //
+  // Preprocessing job performed for -fsycl enabled compilation specifically
+  // for dependency generation (TY_Dependencies)
+  //
   if (FinalOutput) {
     unsigned NumOutputs = 0;
     unsigned NumIfsOutputs = 0;
@@ -5862,7 +5891,10 @@ void Driver::BuildJobs(Compilation &C) const {
              A->getKind() == clang::driver::Action::CompileJobClass &&
              0 == NumIfsOutputs++) ||
             (A->getKind() == Action::BindArchClass && A->getInputs().size() &&
-             A->getInputs().front()->getKind() == Action::IfsMergeJobClass)))
+             A->getInputs().front()->getKind() == Action::IfsMergeJobClass) ||
+            (A->getKind() == Action::PreprocessJobClass &&
+             A->getType() == types::TY_Dependencies &&
+             C.getArgs().hasArg(options::OPT_fsycl))))
         ++NumOutputs;
 
     if (NumOutputs > 1) {
@@ -6649,7 +6681,9 @@ InputInfo Driver::BuildJobsForActionNoCache(
       } else if (types::isFPGA(JA->getType())) {
         std::string Ext(types::getTypeTempSuffix(JA->getType()));
         types::ID TI = types::TY_Object;
-        if (EffectiveTriple.getSubArch() == llvm::Triple::SPIRSubArch_fpga) {
+        if (EffectiveTriple.isSPIR()) {
+          if (!UI.DependentToolChain->getTriple().isSPIR())
+            continue;
           // Output file from unbundle is FPGA device. Name the file
           // accordingly.
           if (UI.DependentOffloadKind == Action::OFK_Host) {
@@ -6665,13 +6699,11 @@ InputInfo Driver::BuildJobsForActionNoCache(
               JA->getType() == types::TY_FPGA_AOCR_EMU)
             // AOCR files are always unbundled into a list file.
             TI = types::TY_Tempfilelist;
-        } else if (EffectiveTriple.getSubArch() !=
-                   llvm::Triple::SPIRSubArch_fpga) {
-          if (UI.DependentOffloadKind == Action::OFK_SYCL) {
+        } else {
+          if (UI.DependentOffloadKind == Action::OFK_SYCL)
             // Do not add the current info for device with FPGA device.  The
             // device side isn't used
             continue;
-          }
           TI = types::TY_Tempfilelist;
           Ext = "txt";
         }

clang/lib/Driver/ToolChains/Clang.cpp

@@ -1203,6 +1203,12 @@ void Clang::AddPreprocessingOptions(Compilation &C, const JobAction &JA,
     C.getDriver().addFPGATempDepFile(DepFile, BaseName);
   };
 
+  // Do not add dependency generation information when compiling the source +
+  // footer combination.  The dependency generation is done in a separate
+  // compile step so we can retain original source information.
+  if (ContainsAppendFooterAction(&JA))
+    ArgM = nullptr;
+
   if (ArgM) {
     // Determine the output location.
     const char *DepFile;
@@ -1216,6 +1222,12 @@ void Clang::AddPreprocessingOptions(Compilation &C, const JobAction &JA,
             DepFile, Clang::getBaseInputName(Args, Inputs[0]));
     } else if (Output.getType() == types::TY_Dependencies) {
       DepFile = Output.getFilename();
+      if (!ContainsAppendFooterAction(&JA) && Args.hasArg(options::OPT_fsycl) &&
+          !Args.hasArg(options::OPT_fno_sycl_use_footer) &&
+          !JA.isDeviceOffloading(Action::OFK_SYCL))
+        // Name the dependency file for the specific dependency generation
+        // step created for the integration footer enabled compilation.
+        DepFile = getDependencyFileName(Args, Inputs);
     } else if (!ArgMD) {
       DepFile = "-";
     } else if (IsIntelFPGA && JA.isDeviceOffloading(Action::OFK_SYCL)) {
@@ -8303,10 +8315,8 @@ void OffloadBundler::ConstructJobMultipleOutputs(
     // types (aocx/aocr) are always list files.  We should represent this
     // better in the output extension and type for improved understanding
     // of file contents and debuggability.
-    if (getToolChain().getTriple().getSubArch() ==
-        llvm::Triple::SPIRSubArch_fpga)
-      TypeArg = (InputType == types::TY_FPGA_AOCX) ? "aocx" : "aocr";
-    else
+    TypeArg = (InputType == types::TY_FPGA_AOCX) ? "aocx" : "aocr";
+    if (!getToolChain().getTriple().isSPIR())
       TypeArg = "aoo";
   }
   if (InputType == types::TY_FPGA_AOCO || IsFPGADepLibUnbundle)
@@ -8327,28 +8337,25 @@ void OffloadBundler::ConstructJobMultipleOutputs(
     // aocx or aocr type bundles.  Also, we only do a specific target
     // unbundling, skipping the host side or device side.
     if (types::isFPGA(InputType)) {
-      if (getToolChain().getTriple().getSubArch() ==
-              llvm::Triple::SPIRSubArch_fpga &&
-          Dep.DependentOffloadKind == Action::OFK_SYCL) {
-        if (J++)
-          Triples += ',';
-        llvm::Triple TT;
-        TT.setArchName(types::getTypeName(InputType));
-        TT.setVendorName("intel");
-        TT.setOS(getToolChain().getTriple().getOS());
-        TT.setEnvironment(llvm::Triple::SYCLDevice);
-        Triples += "sycl-";
-        Triples += TT.normalize();
-      } else if (getToolChain().getTriple().getSubArch() !=
-                     llvm::Triple::SPIRSubArch_fpga &&
-                 Dep.DependentOffloadKind == Action::OFK_Host) {
-        if (J++)
-          Triples += ',';
-        Triples += Action::GetOffloadKindName(Dep.DependentOffloadKind);
-        Triples += '-';
-        Triples += Dep.DependentToolChain->getTriple().normalize();
-      }
-      continue;
+      if (getToolChain().getTriple().isSPIR()) {
+        if (Dep.DependentToolChain->getTriple().getSubArch() ==
+            llvm::Triple::SPIRSubArch_fpga) {
+          if (J++)
+            Triples += ',';
+          llvm::Triple TT;
+          TT.setArchName(types::getTypeName(InputType));
+          TT.setVendorName("intel");
+          TT.setOS(getToolChain().getTriple().getOS());
+          TT.setEnvironment(llvm::Triple::SYCLDevice);
+          Triples += "sycl-";
+          Triples += TT.normalize();
+          continue;
+        } else if (Dep.DependentOffloadKind == Action::OFK_Host) {
+          // No host unbundle for FPGA binaries.
+          continue;
+        }
+      } else if (Dep.DependentOffloadKind == Action::OFK_SYCL)
+        continue;
     } else if (InputType == types::TY_Archive ||
                (getToolChain().getTriple().getSubArch() ==
                     llvm::Triple::SPIRSubArch_fpga &&

clang/test/Driver/sycl-int-footer.cpp

@@ -67,3 +67,35 @@
 // FOOTER_PATH: append-file{{.*}} "--append=dummy_dir{{(/|\\\\)}}{{.*}}-footer-{{.*}}.h"
 // FOOTER_PATH-SAME: "--output=dummy_dir{{(/|\\\\)}}[[APPENDEDSRC:.+\.cpp]]"
 // FOOTER_PATH: clang{{.*}} "-x" "c++" "dummy_dir{{(/|\\\\)}}[[APPENDEDSRC]]"
+
+/// Check behaviors for dependency generation
+// RUN:  %clangxx -fsycl -MD -c %s -### 2>&1 \
+// RUN:   | FileCheck -check-prefix DEP_GEN %s
+// DEP_GEN:  clang{{.*}} "-Eonly"
+// DEP_GEN-SAME: "-dependency-file"
+// DEP_GEN-SAME: "-MT"
+// DEP_GEN-SAME: "-x" "c++" "[[INPUTFILE:.+\.cpp]]"
+// DEP_GEN: append-file{{.*}} "[[INPUTFILE]]"
+// DEP_GEN-NOT: clang{{.*}} "-dependency-file"
+
+/// Dependency generation phases
+// RUN:  %clangxx -target x86_64-unknown-linux-gnu -fsycl -MD -c %s -ccc-print-phases 2>&1 \
+// RUN:   | FileCheck -check-prefix DEP_GEN_PHASES %s
+// DEP_GEN_PHASES: 0: input, "[[INPUTFILE:.+\.cpp]]", c++, (host-sycl)
+// DEP_GEN_PHASES: 1: preprocessor, {0}, dependencies
+// DEP_GEN_PHASES: 2: input, "[[INPUTFILE]]", c++, (device-sycl)
+// DEP_GEN_PHASES: 3: preprocessor, {2}, c++-cpp-output, (device-sycl)
+// DEP_GEN_PHASES: 4: compiler, {3}, ir, (device-sycl)
+// DEP_GEN_PHASES: 5: offload, "device-sycl (spir64-unknown-unknown-sycldevice)" {4}, ir
+// DEP_GEN_PHASES: 6: append-footer, {0}, c++, (host-sycl)
+// DEP_GEN_PHASES: 7: preprocessor, {6}, c++-cpp-output, (host-sycl)
+// DEP_GEN_PHASES: 8: offload, "host-sycl (x86_64-unknown-linux-gnu)" {7}, "device-sycl (spir64-unknown-unknown-sycldevice)" {4}, c++-cpp-output
+// DEP_GEN_PHASES: 9: compiler, {8}, ir, (host-sycl)
+// DEP_GEN_PHASES: 10: backend, {9}, assembler, (host-sycl)
+// DEP_GEN_PHASES: 11: assembler, {10}, object, (host-sycl)
+// DEP_GEN_PHASES: 12: clang-offload-bundler, {5, 11}, object, (host-sycl)
+
+/// Allow for -o and preprocessing
+// RUN:  %clangxx -fsycl -MD -c %s -o dummy -### 2>&1 \
+// RUN:   | FileCheck -check-prefix DEP_GEN_OUT_ERROR %s
+// DEP_GEN_OUT_ERROR-NOT: cannot specify -o when generating multiple output files