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[RISCV] Add SiFive cores to the CPU option
Add the SiFive cores E76 and U74 using the SiFive 7 series microarchitecture. Differential Revision: https://reviews.llvm.org/D88759
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‎clang/test/Driver/riscv-cpus.c

+19-5
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,12 @@
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// MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64"
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// MCPU-ROCKET64: "-target-feature" "+64bit"
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10-
// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=bullet-rv32 | FileCheck -check-prefix=MCPU-BULLET32 %s
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// MCPU-BULLET32: "-nostdsysteminc" "-target-cpu" "bullet-rv32"
10+
// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-7-rv32 | FileCheck -check-prefix=MCPU-SIFIVE7-32 %s
11+
// MCPU-SIFIVE7-32: "-nostdsysteminc" "-target-cpu" "sifive-7-rv32"
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// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=bullet-rv64 | FileCheck -check-prefix=MCPU-BULLET64 %s
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// MCPU-BULLET64: "-nostdsysteminc" "-target-cpu" "bullet-rv64"
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// MCPU-BULLET64: "-target-feature" "+64bit"
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// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-7-rv64 | FileCheck -check-prefix=MCPU-SIFIVE7-64 %s
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// MCPU-SIFIVE7-64: "-nostdsysteminc" "-target-cpu" "sifive-7-rv64"
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// MCPU-SIFIVE7-64: "-target-feature" "+64bit"
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// mcpu with default march
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// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck -check-prefix=MCPU-SIFIVE-U54 %s
@@ -28,6 +28,20 @@
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// MCPU-ABI-SIFIVE-U54: "-target-feature" "+c" "-target-feature" "+64bit"
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// MCPU-ABI-SIFIVE-U54: "-target-abi" "lp64"
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// mcpu with default march
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// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e76 | FileCheck -check-prefix=MCPU-SIFIVE-E76 %s
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// MCPU-SIFIVE-E76: "-nostdsysteminc" "-target-cpu" "sifive-e76"
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// MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
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// MCPU-SIFIVE-E76: "-target-feature" "+c"
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// MCPU-SIFIVE-E76: "-target-abi" "lp64d"
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// mcpu with mabi option
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// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s
40+
// MCPU-ABI-SIFIVE-U74: "-nostdsysteminc" "-target-cpu" "sifive-u74"
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// MCPU-ABI-SIFIVE-U74: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
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// MCPU-ABI-SIFIVE-U74: "-target-feature" "+c" "-target-feature" "+64bit"
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// MCPU-ABI-SIFIVE-U74: "-target-abi" "lp64"
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// march overwrite mcpu's default march
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// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -march=rv32imc | FileCheck -check-prefix=MCPU-MARCH %s
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// MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" "+m" "-target-feature" "+c"

‎clang/test/Misc/target-invalid-cpu-note.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -191,8 +191,8 @@
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// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
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// RISCV32: error: unknown target CPU 'not-a-cpu'
194-
// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, bullet-rv32, sifive-e31
194+
// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e31, sifive-e76
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// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
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// RISCV64: error: unknown target CPU 'not-a-cpu'
198-
// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, bullet-rv64, sifive-u54
198+
// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-u54, sifive-u74

‎llvm/include/llvm/Support/RISCVTargetParser.def

+4-2
Original file line numberDiff line numberDiff line change
@@ -7,9 +7,11 @@ PROC(GENERIC_RV32, {"generic-rv32"}, FK_NONE, {""})
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PROC(GENERIC_RV64, {"generic-rv64"}, FK_64BIT, {""})
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PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {""})
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PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""})
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PROC(BULLET_RV32, {"bullet-rv32"}, FK_NONE, {""})
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PROC(BULLET_RV64, {"bullet-rv64"}, FK_64BIT, {""})
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PROC(BULLET_RV32, {"sifive-7-rv32"}, FK_NONE, {""})
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PROC(BULLET_RV64, {"sifive-7-rv64"}, FK_64BIT, {""})
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PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
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PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
14+
PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
15+
PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
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#undef PROC

‎llvm/lib/Target/RISCV/RISCV.td

+14-2
Original file line numberDiff line numberDiff line change
@@ -228,8 +228,8 @@ def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
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def : ProcessorModel<"rocket-rv32", RocketModel, []>;
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def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
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def : ProcessorModel<"bullet-rv32", BulletModel, []>;
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def : ProcessorModel<"bullet-rv64", BulletModel, [Feature64Bit]>;
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def : ProcessorModel<"sifive-7-rv32", BulletModel, []>;
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def : ProcessorModel<"sifive-7-rv64", BulletModel, [Feature64Bit]>;
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def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM,
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FeatureStdExtA,
@@ -242,6 +242,18 @@ def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
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FeatureStdExtD,
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FeatureStdExtC]>;
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245+
def : ProcessorModel<"sifive-e76", BulletModel, [FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtC]>;
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250+
def : ProcessorModel<"sifive-u74", BulletModel, [Feature64Bit,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC]>;
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//===----------------------------------------------------------------------===//
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// Define the RISC-V target.
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//===----------------------------------------------------------------------===//

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