diff --git a/README.txt b/README.txt index 185432f..29f1099 100644 --- a/README.txt +++ b/README.txt @@ -9,8 +9,10 @@ to MCHP_MEC1701.h Field EOF was renamed to PEOF as it was collapsing with EOF defined in stdio.h Microchip HAL contianing the above MEC1701 single header and the -MEC1501 component style is located at: +MEC1501 and MEC172x component style are located at: https://github.com/MicrochipTech/hal_microchip -Version: 1.2.0 +Version: 1.3.0 +Add MEC172x + diff --git a/mec/CMakeLists.txt b/mec/CMakeLists.txt index 5cca6b0..3d8cd66 100644 --- a/mec/CMakeLists.txt +++ b/mec/CMakeLists.txt @@ -8,3 +8,6 @@ zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_MEC1701X .) zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_MEC1501X common) zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_MEC1501X mec1501) + +zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_MEC172X common) +zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_MEC172X mec172x) diff --git a/mec/mec172x/MEC172XNSZ.h b/mec/mec172x/MEC172XNSZ.h new file mode 100644 index 0000000..1201e84 --- /dev/null +++ b/mec/mec172x/MEC172XNSZ.h @@ -0,0 +1,2550 @@ +/************************************************************************** + * @file MEC172XNSZ.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for + * Device Microchip MEC172X-N-SZ + * @version V5.00 + * @date 18. Febuary 2021 + * Copyright (c) 2021 Microchip Technology Inc. + ***************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2021 Microchip Technology Incorporated. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MEC172XNSZ_H +#define MEC172XNSZ_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup MCHP + * @{ + */ + +/** @addtogroup MEC172XNSZ + * @{ + */ + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* ====================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/*======================================================================= */ + +/** @brief ARM Cortex-M4 NVIC Interrupt Numbers + * CM4 NVIC implements 16 internal interrupt sources. CMSIS macros use + * negative numbers [-15, -1]. Lower numerical value indicates higher + * priority. + * -15 = Reset Vector invoked on POR or any CPU reset. + * -14 = NMI + * -13 = Hard Fault. At POR or CPU reset all faults map to Hard Fault. + * -12 = Memory Management Fault. If enabled Hard Faults caused by access + * violations, no address match, or MPU mismatch. + * -11 = Bus Fault. If enabled pre-fetch, AHB access faults. + * -10 = Usage Fault. If enabled Undefined instructions, illegal state + * transition (Thumb -> ARM mode), unaligned, etc. + * -9 through -6 are not implemented (reserved). + * -5 System call via SVC instruction. + * -4 Debug Monitor. + * -3 not implemented (reserved). + * -2 PendSV for system service. + * -1 SysTick NVIC system timer. + * Numbers >= 0 are external peripheral interrupts. + */ +typedef enum IRQn { + /* ========== ARM Cortex-M4 Specific Interrupt Numbers ============ */ + + Reset_IRQn = -15, /*!< POR/CPU Reset Vector */ + NonMaskableInt_IRQn = -14, /*!< NMI */ + HardFault_IRQn = -13, /*!< Hard Faults */ + MemoryManagement_IRQn = -12, /*!< Memory Management faults */ + BusFault_IRQn = -11, /*!< Bus Access faults */ + UsageFault_IRQn = -10, /*!< Usage/instruction faults */ + SVCall_IRQn = -5, /*!< SVC */ + DebugMonitor_IRQn = -4, /*!< Debug Monitor */ + PendSV_IRQn = -2, /*!< PendSV */ + SysTick_IRQn = -1, /*!< SysTick */ + + /* ============== MEC172x Specific Interrupt Numbers ============ */ + + GIRQ08_IRQn = 0, /*!< GPIO 0140 - 0176 */ + GIRQ09_IRQn = 1, /*!< GPIO 0100 - 0136 */ + GIRQ10_IRQn = 2, /*!< GPIO 0040 - 0076 */ + GIRQ11_IRQn = 3, /*!< GPIO 0000 - 0036 */ + GIRQ12_IRQn = 4, /*!< GPIO 0200 - 0236 */ + GIRQ13_IRQn = 5, /*!< SMBus Aggregated */ + GIRQ14_IRQn = 6, /*!< DMA Aggregated */ + GIRQ15_IRQn = 7, + GIRQ16_IRQn = 8, + GIRQ17_IRQn = 9, + GIRQ18_IRQn = 10, + GIRQ19_IRQn = 11, + GIRQ20_IRQn = 12, + GIRQ21_IRQn = 13, + /* GIRQ22(peripheral clock wake) is not connected to NVIC */ + GIRQ23_IRQn = 14, + GIRQ24_IRQn = 15, + GIRQ25_IRQn = 16, + GIRQ26_IRQn = 17, /*!< GPIO 0240 - 0276 */ + /* Reserved 18-19 */ + /* GIRQ's 8 - 12, 24 - 26 no direct connections */ + I2C_SMB_0_IRQn = 20, /*!< GIRQ13 b[0] */ + I2C_SMB_1_IRQn = 21, /*!< GIRQ13 b[1] */ + I2C_SMB_2_IRQn = 22, /*!< GIRQ13 b[2] */ + I2C_SMB_3_IRQn = 23, /*!< GIRQ13 b[3] */ + DMA0_IRQn = 24, /*!< GIRQ14 b[0] */ + DMA1_IRQn = 25, /*!< GIRQ14 b[1] */ + DMA2_IRQn = 26, /*!< GIRQ14 b[2] */ + DMA3_IRQn = 27, /*!< GIRQ14 b[3] */ + DMA4_IRQn = 28, /*!< GIRQ14 b[4] */ + DMA5_IRQn = 29, /*!< GIRQ14 b[5] */ + DMA6_IRQn = 30, /*!< GIRQ14 b[6] */ + DMA7_IRQn = 31, /*!< GIRQ14 b[7] */ + DMA8_IRQn = 32, /*!< GIRQ14 b[8] */ + DMA9_IRQn = 33, /*!< GIRQ14 b[9] */ + DMA10_IRQn = 34, /*!< GIRQ14 b[10] */ + DMA11_IRQn = 35, /*!< GIRQ14 b[11] */ + DMA12_IRQn = 36, /*!< GIRQ14 b[12] */ + DMA13_IRQn = 37, /*!< GIRQ14 b[13] */ + DMA14_IRQn = 38, /*!< GIRQ14 b[14] */ + DMA15_IRQn = 39, /*!< GIRQ14 b[15] */ + UART0_IRQn = 40, /*!< GIRQ15 b[0] */ + UART1_IRQn = 41, /*!< GIRQ15 b[1] */ + EMI0_IRQn = 42, /*!< GIRQ15 b[2] */ + EMI1_IRQn = 43, /*!< GIRQ15 b[3] */ + EMI2_IRQn = 44, /*!< GIRQ15 b[4] */ + ACPI_EC0_IBF_IRQn = 45, /*!< GIRQ15 b[5] */ + ACPI_EC0_OBE_IRQn = 46, /*!< GIRQ15 b[6] */ + ACPI_EC1_IBF_IRQn = 47, /*!< GIRQ15 b[7] */ + ACPI_EC1_OBE_IRQn = 48, /*!< GIRQ15 b[8] */ + ACPI_EC2_IBF_IRQn = 49, /*!< GIRQ15 b[9] */ + ACPI_EC2_OBE_IRQn = 50, /*!< GIRQ15 b[10] */ + ACPI_EC3_IBF_IRQn = 51, /*!< GIRQ15 b[11] */ + ACPI_EC3_OBE_IRQn = 52, /*!< GIRQ15 b[12] */ + ACPI_EC4_IBF_IRQn = 53, /*!< GIRQ15 b[13] */ + ACPI_EC4_OBE_IRQn = 54, /*!< GIRQ15 b[14] */ + ACPI_PM1_CTL_IRQn = 55, /*!< GIRQ15 b[15] */ + ACPI_PM1_EN_IRQn = 56, /*!< GIRQ15 b[16] */ + ACPI_PM1_STS_IRQn = 57, /*!< GIRQ15 b[17] */ + KBC_OBE_IRQn = 58, /*!< GIRQ15 b[18] */ + KBC_IBF_IRQn = 59, /*!< GIRQ15 b[19] */ + MBOX_IRQn = 60, /*!< GIRQ15 b[20] */ + /* reserved 61 */ + P80BD_0_IRQn = 62, /*!< GIRQ15 b[22] */ + /* reserved 63-64 */ + PKE_IRQn = 65, /*!< GIRQ16 b[0] */ + /* reserved 66 */ + RNG_IRQn = 67, /*!< GIRQ16 b[2] */ + AESH_IRQn = 68, /*!< GIRQ16 b[3] */ + /* reserved 69 */ + PECI_IRQn = 70, /*!< GIRQ17 b[0] */ + TACH_0_IRQn = 71, /*!< GIRQ17 b[1] */ + TACH_1_IRQn = 72, /*!< GIRQ17 b[2] */ + TACH_2_IRQn = 73, /*!< GIRQ17 b[3] */ + RPMFAN_0_FAIL_IRQn = 74, /*!< GIRQ17 b[20] */ + RPMFAN_0_STALL_IRQn = 75, /*!< GIRQ17 b[21] */ + RPMFAN_1_FAIL_IRQn = 76, /*!< GIRQ17 b[22] */ + RPMFAN_1_STALL_IRQn = 77, /*!< GIRQ17 b[23] */ + ADC_SNGL_IRQn = 78, /*!< GIRQ17 b[8] */ + ADC_RPT_IRQn = 79, /*!< GIRQ17 b[9] */ + RCID_0_IRQn = 80, /*!< GIRQ17 b[10] */ + RCID_1_IRQn = 81, /*!< GIRQ17 b[11] */ + RCID_2_IRQn = 82, /*!< GIRQ17 b[12] */ + LED_0_IRQn = 83, /*!< GIRQ17 b[13] */ + LED_1_IRQn = 84, /*!< GIRQ17 b[14] */ + LED_2_IRQn = 85, /*!< GIRQ17 b[15] */ + LED_3_IRQn = 86, /*!< GIRQ17 b[16] */ + PHOT_IRQn = 87, /*!< GIRQ17 b[17] */ + /* reserved 88-89 */ + SPIP_0_IRQn = 90, /*!< GIRQ18 b[0] */ + QMSPI_0_IRQn = 91, /*!< GIRQ18 b[1] */ + GPSPI_0_TXBE_IRQn = 92, /*!< GIRQ18 b[2] */ + GPSPI_0_RXBF_IRQn = 93, /*!< GIRQ18 b[3] */ + GPSPI_1_TXBE_IRQn = 94, /*!< GIRQ18 b[4] */ + GPSPI_1_RXBF_IRQn = 95, /*!< GIRQ18 b[5] */ + BCL_0_ERR_IRQn = 96, /*!< GIRQ18 b[7] */ + BCL_0_BCLR_IRQn = 97, /*!< GIRQ18 b[6] */ + /* reserved 98-99 */ + PS2_0_ACT_IRQn = 100, /*!< GIRQ18 b[10] */ + /* reserved 101-102 */ + ESPI_PC_IRQn = 103, /*!< GIRQ19 b[0] */ + ESPI_BM1_IRQn = 104, /*!< GIRQ19 b[1] */ + ESPI_BM2_IRQn = 105, /*!< GIRQ19 b[2] */ + ESPI_LTR_IRQn = 106, /*!< GIRQ19 b[3] */ + ESPI_OOB_UP_IRQn = 107, /*!< GIRQ19 b[4] */ + ESPI_OOB_DN_IRQn = 108, /*!< GIRQ19 b[5] */ + ESPI_FLASH_IRQn = 109, /*!< GIRQ19 b[6] */ + ESPI_RESET_IRQn = 110, /*!< GIRQ19 b[7] */ + RTMR_IRQn = 111, /*!< GIRQ23 b[10] */ + HTMR_0_IRQn = 112, /*!< GIRQ23 b[16] */ + HTMR_1_IRQn = 113, /*!< GIRQ23 b[17] */ + WK_IRQn = 114, /*!< GIRQ21 b[3] */ + WKSUB_IRQn = 115, /*!< GIRQ21 b[4] */ + WKSEC_IRQn = 116, /*!< GIRQ21 b[5] */ + WKSUBSEC_IRQn = 117, /*!< GIRQ21 b[6] */ + WKSYSPWR_IRQn = 118, /*!< GIRQ21 b[7] */ + RTC_IRQn = 119, /*!< GIRQ21 b[8] */ + RTC_ALARM_IRQn = 120, /*!< GIRQ21 b[9] */ + VCI_OVRD_IN_IRQn = 121, /*!< GIRQ21 b[10] */ + VCI_IN0_IRQn = 122, /*!< GIRQ21 b[11] */ + VCI_IN1_IRQn = 123, /*!< GIRQ21 b[12] */ + VCI_IN2_IRQn = 124, /*!< GIRQ21 b[13] */ + VCI_IN3_IRQn = 125, /*!< GIRQ21 b[14] */ + VCI_IN4_IRQn = 126, /*!< GIRQ21 b[15] */ + /* reserved 127-128 */ + PS2_0A_WAKE_IRQn = 129, /*!< GIRQ21 b[18] */ + PS2_0B_WAKE_IRQn = 130, /*!< GIRQ21 b[19] */ + /* reserved 131-134 */ + KEYSCAN_IRQn = 135, /*!< GIRQ21 b[25] */ + B16TMR_0_IRQn = 136, /*!< GIRQ23 b[0] */ + B16TMR_1_IRQn = 137, /*!< GIRQ23 b[1] */ + B16TMR_2_IRQn = 138, /*!< GIRQ23 b[2] */ + B16TMR_3_IRQn = 139, /*!< GIRQ23 b[3] */ + B32TMR_0_IRQn = 140, /*!< GIRQ23 b[4] */ + B32TMR_1_IRQn = 141, /*!< GIRQ23 b[5] */ + CTMR_0_IRQn = 142, /*!< GIRQ23 b[6] */ + CTMR_1_IRQn = 143, /*!< GIRQ23 b[7] */ + CTMR_2_IRQn = 144, /*!< GIRQ23 b[8] */ + CTMR_3_IRQn = 145, /*!< GIRQ23 b[9] */ + CCT_IRQn = 146, /*!< GIRQ18 b[20] */ + CCT_CAP0_IRQn = 147, /*!< GIRQ18 b[21] */ + CCT_CAP1_IRQn = 148, /*!< GIRQ18 b[22] */ + CCT_CAP2_IRQn = 149, /*!< GIRQ18 b[23] */ + CCT_CAP3_IRQn = 150, /*!< GIRQ18 b[24] */ + CCT_CAP4_IRQn = 151, /*!< GIRQ18 b[25] */ + CCT_CAP5_IRQn = 152, /*!< GIRQ18 b[26] */ + CCT_CMP0_IRQn = 153, /*!< GIRQ18 b[27] */ + CCT_CMP1_IRQn = 154, /*!< GIRQ18 b[28] */ + EEPROMC_IRQn = 155, /*!< GIRQ18 b[13] */ + ESPI_VWIRE_IRQn = 156, /*!< GIRQ19 b[8] */ + /* reserved 157 */ + I2C_SMB_4_IRQn = 158, /*!< GIRQ13 b[4] */ + TACH_3_IRQn = 159, /*!< GIRQ17 b[4] */ + /* reserved 160-165 */ + SAF_DONE_IRQn = 166, /*!< GIRQ19 b[9] */ + SAF_ERR_IRQn = 167, /*!< GIRQ19 b[10] */ + /* reserved 168 */ + SAF_CACHE_IRQn = 169, /*!< GIRQ19 b[11] */ + /* reserved 170 */ + WDT_0_IRQn = 171, /*!< GIRQ21 b[2] */ + GLUE_IRQn = 172, /*!< GIRQ21 b[26] */ + OTP_RDY_IRQn = 173, /*!< GIRQ20 b[3] */ + CLK32K_MON_IRQn = 174, /*!< GIRQ20 b[9] */ + ACPI_EC0_IRQn = 175, /* ACPI EC OBE and IBF combined into one */ + ACPI_EC1_IRQn = 176, /* No GIRQ connection. Status in ACPI blocks */ + ACPI_EC2_IRQn = 177, /* Code uses level bits and NVIC bits */ + ACPI_EC3_IRQn = 178, + ACPI_EC4_IRQn = 179, + ACPI_PM1_IRQn = 180, + MAX_IRQn +} IRQn_Type; + +/* ========================================================================= */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ========================================================================= */ + +/* == Configuration of the Arm Cortex-M4 Processor and Core Peripherals == */ + +#define __CM4_REV 0x0201 /*!< Core Revision r2p1 */ + +#define __MPU_PRESENT 1 /*!< Set to 1 if MPU is present */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if VTOR is present */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< 0 use default SysTick HW */ +#define __FPU_PRESENT 1 /*!< Set to 1 if FPU is present */ +#define __FPU_DP 0 /*!< Set to 1 if FPU is double precision */ +#define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */ +#define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */ +#define __DTCM_PRESENT 0 /*!< Set to 1 if DTCM is present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< Arm Cortex-M4 processor and core peripherals */ + +/* == Start of section using anonymous unions ========================= */ +#if defined(__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined(__ICCARM__) +#pragma language = extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) +#pragma warning 586 +#elif defined(__CSMC__) +/* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif + +/* ====================================================================== */ +/* ================ Device Specific Peripheral Section ============== */ +/* ====================================================================== */ + +/** @addtogroup MEC172x_Peripheral_peripherals + * @{ + */ + +/** @brief GIRQ registers. Total size = 20(0x14) bytes */ +typedef struct girq_regs { + __IOM uint32_t SRC; /*! (@ 0x0000) GIRQ Source(RW/1C) */ + __IOM uint32_t EN_SET; /*! (@ 0x0004) GIRQ Enable Set(RW) */ + __IOM uint32_t RESULT; /*! (@ 0x0008) GIRQ Result(RO) */ + __IOM uint32_t EN_CLR; /*! (@ 0x000C) GIRQ Enable Clear(RW) */ + uint32_t RSVD1[1]; +} GIRQ_Type; + +/** @brief ECIA registers with each GIRQ elucidated */ +typedef struct ecia_regs { + GIRQ_Type GIRQ08; /*!< (@ 0x0000) GIRQ08 */ + GIRQ_Type GIRQ09; /*!< (@ 0x0014) GIRQ09 */ + GIRQ_Type GIRQ10; /*!< (@ 0x0028) GIRQ10 */ + GIRQ_Type GIRQ11; /*!< (@ 0x003C) GIRQ11 */ + GIRQ_Type GIRQ12; /*!< (@ 0x0050) GIRQ12 */ + GIRQ_Type GIRQ13; /*!< (@ 0x0064) GIRQ13 */ + GIRQ_Type GIRQ14; /*!< (@ 0x0078) GIRQ14 */ + GIRQ_Type GIRQ15; /*!< (@ 0x008C) GIRQ15 */ + GIRQ_Type GIRQ16; /*!< (@ 0x00A0) GIRQ16 */ + GIRQ_Type GIRQ17; /*!< (@ 0x00B4) GIRQ17 */ + GIRQ_Type GIRQ18; /*!< (@ 0x00C8) GIRQ18 */ + GIRQ_Type GIRQ19; /*!< (@ 0x00DC) GIRQ19 */ + GIRQ_Type GIRQ20; /*!< (@ 0x00F0) GIRQ20 */ + GIRQ_Type GIRQ21; /*!< (@ 0x0104) GIRQ21 */ + GIRQ_Type GIRQ22; /*!< (@ 0x0118) GIRQ22 */ + GIRQ_Type GIRQ23; /*!< (@ 0x012C) GIRQ23 */ + GIRQ_Type GIRQ24; /*!< (@ 0x0140) GIRQ24 */ + GIRQ_Type GIRQ25; /*!< (@ 0x0154) GIRQ25 */ + GIRQ_Type GIRQ26; /*!< (@ 0x0168) GIRQ26 */ + uint8_t RSVD2[(0x0200ul - 0x017Cul)]; /* offsets 0x017C - 0x1FF */ + __IOM uint32_t BLK_EN_SET; /*! (@ 0x0200) Aggregated GIRQ output + Enable Set */ + __IOM uint32_t BLK_EN_CLR; /*! (@ 0x0204) Aggregated GIRQ output + Enable Clear */ + __IM uint32_t BLK_ACTIVE; /*! (@ 0x0204) GIRQ Active bitmap (RO) */ +} ECIA_Type; + +/** @brief ECIA registers with array of GIRQ's */ +typedef struct ecia_ar_regs { + GIRQ_Type GIRQ[19]; /*!< (@ 0x0000 - 0x17b GIRQ 8-26 */ + uint8_t RSVD2[(0x200ul - 0x17Cul)]; /* offsets 0x017C - 0x1FF */ + __IOM uint32_t BLK_EN_SET; /*! (@ 0x0200) Aggregated GIRQ output + Enable Set */ + __IOM uint32_t BLK_EN_CLR; /*! (@ 0x0204) Aggregated GIRQ output + Enable Clear */ + __IM uint32_t BLK_ACTIVE; /*! (@ 0x0204) GIRQ Active bitmap (RO) */ +} ECIA_AR_Type; + +/* ---------------- Timers ---------------- */ + +/** @brief Watch Dog Timer (WDT) */ +typedef struct wdt_regs { + __IOM uint16_t LOAD; /*!< (@ 0x0000) WDT Load */ + uint8_t RSVD1[2]; + __IOM uint16_t CTRL; /*!< (@ 0x0004) WDT Control */ + uint8_t RSVD2[2]; + __OM uint8_t KICK; /*!< (@ 0x0008) WDT Kick (WO) */ + uint8_t RSVD3[3]; + __IM uint16_t CNT; /*!< (@ 0x000C) WDT Count (RO) */ + uint8_t RSVD4[2]; + __IOM uint16_t STS; /*!< (@ 0x0010) WDT Status */ + uint8_t RSVD5[2]; + __IOM uint8_t IEN; /*!< (@ 0x0014) WDT Interrupt Enable */ +} WDT_Type; + +/** @brief 16-bit Basic Timer */ +typedef struct btmr16_regs { + __IOM uint16_t CNT; /*!< (@ 0x0000) BTMR Count */ + uint16_t RSVD1[1]; + __IOM uint16_t PRLD; /*!< (@ 0x0004) BTMR Preload */ + uint16_t RSVD2[1]; + __IOM uint8_t STS; /*!< (@ 0x0008) BTMR Status */ + uint8_t RSVDC[3]; + __IOM uint8_t IEN; /*!< (@ 0x000C) BTMR Interrupt Enable */ + uint8_t RSVDD[3]; + __IOM uint32_t CTRL; /*!< (@ 0x0010) BTMR Control */ +} BTMR16_Type; + +/** @brief 32-bit Basic Timer */ +typedef struct btmr32_regs { + __IOM uint32_t CNT; /*!< (@ 0x0000) BTMR Count */ + __IOM uint32_t PRLD; /*!< (@ 0x0004) BTMR Preload */ + __IOM uint8_t STS; /*!< (@ 0x0008) BTMR Status */ + uint8_t RSVDC[3]; + __IOM uint8_t IEN; /*!< (@ 0x000C) BTMR Interrupt Enable */ + uint8_t RSVDD[3]; + __IOM uint32_t CTRL; /*!< (@ 0x0010) BTMR Control */ +} BTMR32_Type; + +/** @brief 16-bit Counter Timer */ +typedef struct ctmr_regs { + __IOM uint32_t CTRL; /*!< (@ 0x0000) CTMR Control */ + __IOM uint32_t CEV_CTRL; /*!< (@ 0x0004) CTMR Clock Event Control */ + __IOM uint32_t RELOAD; /*!< (@ 0x0008) CTMR Reload */ + __IOM uint32_t COUNT; /*!< (@ 0x000C) CTMR Count (RO) */ +} CTMR_Type; + +/** @brief Capture/Compare Timer */ +typedef struct cct_regs { + __IOM uint32_t CTRL; /*!< (@ 0x0000) CCT Control */ + __IOM uint32_t CAP0_CTRL; /*!< (@ 0x0004) CCT Capture 0 Control */ + __IOM uint32_t CAP1_CTRL; /*!< (@ 0x0008) CCT Capture 1 Control */ + __IOM uint32_t FREE_RUN; /*!< (@ 0x000C) CCT Free run counter */ + __IOM uint32_t CAP0; /*!< (@ 0x0010) CCT Capture 0 */ + __IOM uint32_t CAP1; /*!< (@ 0x0014) CCT Capture 1 */ + __IOM uint32_t CAP2; /*!< (@ 0x0018) CCT Capture 2 */ + __IOM uint32_t CAP3; /*!< (@ 0x001C) CCT Capture 3 */ + __IOM uint32_t CAP4; /*!< (@ 0x0020) CCT Capture 4 */ + __IOM uint32_t CAP5; /*!< (@ 0x0024) CCT Capture 5 */ + __IOM uint32_t COMP0; /*!< (@ 0x0028) CCT Compare 0 */ + __IOM uint32_t COMP1; /*!< (@ 0x002C) CCT Compare 1 */ +} CCT_Type; + +/** @brief Hibernation Timer (HTMR) */ +typedef struct htmr_regs { + __IOM uint16_t PRLD; /*!< (@ 0x0000) HTMR Preload */ + uint16_t RSVD1[1]; + __IOM uint16_t CTRL; /*!< (@ 0x0004) HTMR Control */ + uint16_t RSVD2[1]; + __IM uint16_t CNT; /*!< (@ 0x0008) HTMR Count (RO) */ + uint16_t RSVD3[1]; +} HTMR_Type; + +/** @brief RTOS Timer (RTMR) */ +typedef struct rtmr_regs { + __IOM uint32_t CNT; /*!< (@ 0x0000) RTMR Counter */ + __IOM uint32_t PRLD; /*!< (@ 0x0004) RTMR Preload */ + __IOM uint32_t CTRL; /*!< (@ 0x0008) RTMR Control */ + __IOM uint32_t SOFTIRQ; /*!< (@ 0x000C) RTMR Soft IRQ */ +} RTMR_Type; + +/** @brief Week Timer (WKTMR) */ +typedef struct wktmr_regs { + __IOM uint32_t CTRL; /*! (@ 0x0000) WKTMR control */ + __IOM uint32_t ALARM_CNT; /*! (@ 0x0004) WKTMR Week alarm counter */ + __IOM uint32_t TMR_COMP; /*! (@ 0x0008) WKTMR Week timer compare */ + __IM uint32_t CLKDIV; /*! (@ 0x000C) WKTMR Clock Divider (RO) */ + __IOM uint32_t SS_INTR_SEL; /*! (@ 0x0010) WKTMR Sub-second + interrupt select */ + __IOM uint32_t SWK_CTRL; /*! (@ 0x0014) WKTMR Sub-week control */ + __IOM uint32_t SWK_ALARM; /*! (@ 0x0018) WKTMR Sub-week alarm */ + __IOM uint32_t BGPO_DATA; /*! (@ 0x001C) WKTMR BGPO data */ + __IOM uint32_t BGPO_PWR; /*! (@ 0x0020) WKTMR BGPO power */ + __IOM uint32_t BGPO_RST; /*! (@ 0x0024) WKTMR BGPO reset */ +} WKTMR_Type; + +/** @brief Real Time Clock (RTC) */ +typedef struct rtc_regs { + __IOM uint8_t SECONDS; /*! (@ 0x0000) RTC seconds */ + __IOM uint8_t SEC_ALARM; /*! (@ 0x0001) RTC seconds alarm */ + __IOM uint8_t MINUTES; /*! (@ 0x0002) RTC minutes */ + __IOM uint8_t MIN_ALARM; /*! (@ 0x0003) RTC minutes alarm */ + __IOM uint8_t HOURS; /*! (@ 0x0004) RTC hours */ + __IOM uint8_t HOURS_ALARM; /*! (@ 0x0005) RTC hours alarm */ + __IOM uint8_t DAY_OF_WEEK; /*! (@ 0x0006) RTC day of week */ + __IOM uint8_t DAY_OF_MONTH; /*! (@ 0x0007) RTC day of month */ + __IOM uint8_t MONTH; /*! (@ 0x0008) RTC month */ + __IOM uint8_t YEAR; /*! (@ 0x0009) RTC year */ + __IOM uint8_t REGA; /*! (@ 0x000A) RTC Reg A */ + __IOM uint8_t REGB; /*! (@ 0x000B) RTC Reg B */ + __IOM uint8_t REGC; /*! (@ 0x000C) RTC Reg C */ + __IOM uint8_t REGD; /*! (@ 0x000D) RTC Reg D */ + uint8_t RSVD1[2]; + __IOM uint8_t CONTROL; /*! (@ 0x0010) RTC Control */ + uint8_t RSVD2[3]; + __IOM uint8_t WEEK_ALARM; /*! (@ 0x0014) RTC Alarm day of week */ + uint8_t RSVD3[3]; + __IOM uint32_t DLSF; /*! (@ 0x0018) RTC Daylight savings forward */ + __IOM uint32_t DLSB; /*! (@ 0x001C) RTC Daylight savings backward */ +} RTC_Type; + +/* ---------------- Legacy DMA ---------------- */ + +/** @brief DMA Main (DMAM) */ +typedef struct dma_main_regs { + __IOM uint8_t ACTRST; /*!< (@ 0x0000) DMA block activate/reset */ + uint8_t RSVDA[3]; + __IM uint32_t DATA_PKT; /*!< (@ 0x0004) DMA data packet (RO) */ + __IM uint32_t ARB_FSM; /*!< (@ 0x0008) DMA Arbiter FSM (RO) */ +} DMAM_Type; + +/* + * NOTE: structure size is 0x40 (64) bytes as each channel + * is spaced every 0x40 bytes from DMA block base address. + * Channel 0 starts at offset 0x40 from DMA Main base address. + * Channels 0 and 1 include an ALU for special operations on data + * they transfer. + * Channel 0 ALU is specialized for CRC-32 calculations. + * Channel 1 ALU is specialized for memory fill. + */ + +/** @brief DMA Channels 0 and 1 with ALU + * ACTV !< (@ 0x0000) DMA channel activate + * MSTART !< (@ 0x0004) DMA channel memory start address + * MEND !< (@ 0x0008) DMA channel memory end address + * DSTART !< (@ 0x000C) DMA channel device start address + * CTRL !< (@ 0x0010) DMA channel control + * ISTS !< (@ 0x0014) DMA channel interrupt status + * IEN !< (@ 0x0018) DMA channel interrupt enable + * FSM !< (@ 0x001C) DMA channel FSM (RO) + * ALU_EN !< (@ 0x0020) DMA chan[0-1] ALU Enable + * ALU_DATA !< (@ 0x0024) DMA chan[0-1] ALU Data + * ALU_STS !< (@ 0x0028) DMA chan[0-1] ALU post status (RO) + * ALU_FSM !< (@ 0x002C) DMA chan[0-1] ALU FSM (RO) + */ +typedef struct dma_chan_alu_regs { + __IOM uint32_t ACTV; + __IOM uint32_t MSTART; + __IOM uint32_t MEND; + __IOM uint32_t DSTART; + __IOM uint32_t CTRL; + __IOM uint32_t ISTS; + __IOM uint32_t IEN; + __IM uint32_t FSM; + __IOM uint32_t ALU_EN; + __IOM uint32_t ALU_DATA; + __IOM uint32_t ALU_STS; + __IM uint32_t ALU_FSM; + uint32_t RSVD6[4]; +} DMA_CHAN_ALU_Type; + +/** @brief DMA Channels 2 through 11 no ALU */ +typedef struct dma_chan_regs { + __IOM uint32_t ACTV; + __IOM uint32_t MSTART; + __IOM uint32_t MEND; + __IOM uint32_t DSTART; + __IOM uint32_t CTRL; + __IOM uint32_t ISTS; + __IOM uint32_t IEN; + __IM uint32_t FSM; + uint32_t RSVD4[8]; /* pad to 0x40(64) byte size */ +} DMA_CHAN_Type; + +/** @brief DMA block: main and channels */ +typedef struct dma_regs { + __IOM uint32_t ACTRST; /*!< (@ 0x0000) DMA block activate/reset */ + __IM uint32_t DATA_PKT; /*!< (@ 0x0004) DMA data packet (RO) */ + __IM uint32_t ARB_FSM; /*!< (@ 0x0008) DMA Arbiter FSM (RO) */ + uint32_t RSVD2[13]; + DMA_CHAN_ALU_Type CHAN[16]; /*!< (@ 0x0040) DMA Channels 0 - 15 */ +} DMA_Type; + +/* ---------------- I2C/SMBus ---------------- */ +/** @brief I2C with SMBus Network Layer (SNL) */ +typedef struct i2c_smb_regs { + __IOM uint8_t CTRLSTS; /*!< (@ 0x0000) I2C Status(RO), Control(WO) */ + uint8_t RSVD1[3]; + __IOM uint32_t OWN_ADDR; /*!< (@ 000004) I2C Own address 1 */ + __IOM uint8_t I2CDATA; /*!< (@ 0x0008) I2C Data */ + uint8_t RSVD2[3]; + __IOM uint32_t MCMD; /*!< (@ 0x000C) I2C SNL leader command */ + __IOM uint32_t SCMD; /*!< (@ 0x0010) I2C SNL follower command */ + __IOM uint8_t PEC; /*!< (@ 0x0014) I2C PEC value */ + uint8_t RSVD3[3]; + __IOM uint32_t RSHTM; /*!< (@ 0x0018) I2C Repeated-Start hold time */ + __IOM uint32_t EXTLEN; /*!< (@ 0x001C) I2C Extended length */ + __IOM uint32_t COMPL; /*!< (@ 0x0020) I2C Completion */ + __IOM uint32_t IDLSC; /*!< (@ 0x0024) I2C Idle scaling */ + __IOM uint32_t CFG; /*!< (@ 0x0028) I2C Configuration */ + __IOM uint32_t BUSCLK; /*!< (@ 0x002C) I2C Bus Clock */ + __IOM uint32_t BLKID; /*!< (@ 0x0030) I2C Block ID */ + __IOM uint32_t BLKREV; /*!< (@ 0x0034) I2C Block revision */ + __IOM uint8_t BBCTRL; /*!< (@ 0x0038) I2C Bit-Bang control */ + uint8_t RSVD7[3]; + __IOM uint32_t CLKSYNC; /*!< (@ 0x003C) I2C Clock Sync */ + __IOM uint32_t DATATM; /*!< (@ 0x0040) I2C Data timing */ + __IOM uint32_t TMOUTSC; /*!< (@ 0x0044) I2C Time-out scaling */ + __IOM uint8_t SLV_TXB; /*!< (@ 0x0048) I2C SNL follower TX buffer */ + uint8_t RSVD8[3]; + __IOM uint8_t SLV_RXB; /*!< (@ 0x004C) I2C SNL follower RX buffer */ + uint8_t RSVD9[3]; + __IOM uint8_t MTR_TXB; /*!< (@ 0x0050) I2C SNL leader TX buffer */ + uint8_t RSVD10[3]; + __IOM uint8_t MTR_RXB; /*!< (@ 0x0054) I2C SNL leader RX buffer */ + uint8_t RSVD11[3]; + __IOM uint32_t FSM; /*!< (@ 0x0058) I2C FSM (RO) */ + __IOM uint32_t FSM_SMB; /*!< (@ 0x005C) I2C FSM SMB (RO) */ + __IOM uint8_t WAKE_STS; /*!< (@ 0x0060) I2C Wake status */ + uint8_t RSVD12[3]; + __IOM uint8_t WAKE_EN; /*!< (@ 0x0064) I2C Wake enable */ + uint32_t RSVD13[2]; + __IOM uint32_t PROM_ISTS; /*!< (@ 0x0070) I2C Promiscuous + interrupt status */ + __IOM uint32_t PROM_IEN; /*!< (@ 0x0074) I2C Promiscuous + interrupt enable */ + __IOM uint32_t PROM_CTRL; /*!< (@ 0x0078) I2C Promiscuous control */ + __IOM uint32_t SHADOW_DATA; /*!< (@ 0x007C) I2C Shadow Data. + Last received or transmitted data */ +} I2C_SMB_Type; + +/* ---------------- SPI ---------------------- */ + +/** @brief EEPROM Controller (EEPROMC) */ +typedef struct eepromc_regs { + __IOM uint32_t MODE; /*!< (@ 0x0000) EEPROMC Mode */ + __IOM uint32_t EXE; /*!< (@ 0x0004) EEPROMC Execute */ + __IOM uint32_t STATUS; /*!< (@ 0x0008) EEPROMC Status */ + __IOM uint32_t IEN; /*!< (@ 0x000C) EEPROMC Interrupt enable */ + __IOM uint32_t PSWD; /*!< (@ 0x0010) EEPROMC Password */ + __IOM uint32_t UNLOCK; /*!< (@ 0x0014) EEPROMC Unlock */ + __IOM uint32_t LOCK; /*!< (@ 0x0018) EEPROMC Lock */ + uint32_t RSVD1[1]; + union { + __IOM uint32_t DATA32[8]; + __IOM uint16_t DATA16[16]; + __IOM uint8_t DATA8[32]; + }; /*!< (@ 0x0020) EEPROM 32 byte data array */ +} EEPROMC_Type; + +/** @brief SPI Peripheral registers (SPIP) */ +typedef struct spip_regs { + __IOM uint32_t CONFIG; /*!< (@ 0x0000) SPIP Control */ + __IOM uint32_t SLV_STATUS; /*!< (@ 0x0004) SPIP Slave Status */ + __IOM uint32_t EC_STATUS; /*!< (@ 0x0008) SPIP EC Status */ + __IOM uint32_t SPI_INT_EN; /*!< (@ 0x000C) SPIP SPI Interrupt Enable */ + __IOM uint32_t EC_INT_EN; /*!< (@ 0x0010) SPIP EC Interrupt Enable */ + __IOM uint32_t MCONFIG; /*!< (@ 0x0014) SPIP Memory Config */ + __IOM uint32_t MBA0; /*!< (@ 0x0018) SPIP Memory BAR 0 */ + __IOM uint32_t MBA0_WLIM; /*!< (@ 0x001C) SPIP Memory BAR 0 + Write Limit */ + __IOM uint32_t MBA0_RLIM; /*!< (@ 0x0020) SPIP Memory BAR 0 + Read Limit */ + __IOM uint32_t MBA1; /*!< (@ 0x0024) SPIP Memory BAR 1 */ + __IOM uint32_t MBA1_WLIM; /*!< (@ 0x0028) SPIP Memory BAR 1 + Write Limit */ + __IOM uint32_t MBA1_RLIM; /*!< (@ 0x002C) SPIP Memory BAR 1 + Read Limit */ + __IOM uint32_t RXF_HBAR; /*!< (@ 0x0030) SPIP RX FIFO Host BAR */ + __IOM uint32_t RXF_BCNT; /*!< (@ 0x0034) SPIP RX FIFO Byte Counter */ + __IOM uint32_t TXF_HBAR; /*!< (@ 0x0038) SPIP RX FIFO Host BAR */ + __IOM uint32_t TXF_BCNT; /*!< (@ 0x003C) SPIP TX FIFO Byte Counter */ + __IOM uint32_t SYS_CONFIG; /*!< (@ 0x0040) SPIP System Config */ + __IOM uint32_t MBOX_S2EC; /*!< (@ 0x0044) SPIP external SPI controller + to EC Mailbox */ + __IOM uint32_t MBOX_EC2S; /*!< (@ 0x0048) SPIP EC to external SPI + Controller Mailbox */ +} SPIP_Type; + +/** @brief General Purpose SPI Controller (GPSPI) + * Offset 0x00 GPSPI Activate + * Offset 0x04 GPSPI Control + * Offset 0x08 GPSPI Status + * Offset 0x0C GPSPI TX DATA 8-bit + * Offset 0x10 GPSPI RX DATA 8-bit + * Offset 0x14 GPSPI Clock Control + * Offset 0x18 GPSPI Clock Generator + */ +typedef struct gpspi_regs { + __IOM uint32_t BLOCK_EN; + __IOM uint32_t CONTROL; + __IOM uint32_t STATUS; + __IOM uint8_t TX_DATA; + uint8_t RSVD1[3]; + __IOM uint8_t RX_DATA; + uint8_t RSVD2[3]; + __IOM uint32_t CLK_CTRL; + __IOM uint32_t CLK_GEN; +} GPSPI_Type; + +/** @brief QMSPI Local DMA channel */ +typedef struct qldma_chan { + __IOM uint32_t CTRL; /*!< (@ 0x0000) QMSPI Local DMA channel control */ + __IOM uint32_t MSTART; /*!< (@ 0x0004) QMSPI Local DMA channel memory + start address */ + __IOM uint32_t LEN; /*!< (@ 0x0008) QMSPI Local DMA channel transfer + byte length */ + uint32_t RSVD1[1]; +} QLDCH; + +/** + * @brief Quad Master SPI (QMSPI_LDMA_Type) + * @note Version of QMSPI with local DMA (LDMA) channels. + * MODE (@ 0x0000) Mode: frequency, chip select, signal sampling + * CTRL (@ 0x0004) Control + * EXE (@ 0x0008) Execute, write-only + * IFCTRL (@ 0x000C) Interface control + * STS (@ 0x0010) Status, RW/1C and RO + * BCNT_STS (@ 0x0014) Buffer Count Status, RO + * IEN (@ 0x0018) Interrupt Enable + * BCNT_TRIG (@ 0x001C) Buffer Count Trigger + * TX_FIFO (@ 0x0020) Transmit FIFO + * RX_FIFO (@ 0x0024) Receive FIFO + * CSTM (@ 0x0028) Chip select timing + * DESCR[16] (@ 0x0030 - 0x006F) 32-bit descriptors + * ALIAS_CTRL (@ 0x00B0) eSPI ? + * MODE_ALT1 (@ 0x00C0) Mode Alternate 1 + * TM_TAPS (@ 0x00D0) Timing taps select + * TM_TAPS_ADJ (@ 0x00D4) Timing taps adjust + * TM_TAPS_CTRL (@ 0x00D8) Timing taps control + * LDMA_RX_DESCR_BM (@ 0x100) Local DMA RX Descriptor bit map + * LDMA_TX_DESCR_BM (@ 0x104) Local DMA TX Descriptor bit map + * LDRX[3] (@ 0x110) Local DMA RX channels 0 - 3 + * LDRX[3] (@ 0x140) Local DMA TX channels 0 - 3 + */ +typedef struct qmspi_ldma_regs { + __IOM uint32_t MODE; + __IOM uint32_t CTRL; + __IOM uint32_t EXE; + __IOM uint32_t IFCTRL; + __IOM uint32_t STS; + __IOM uint32_t BCNT_STS; + __IOM uint32_t IEN; + __IOM uint32_t BCNT_TRIG; + __IOM uint32_t TX_FIFO; + __IOM uint32_t RX_FIFO; + __IOM uint32_t CSTM; + uint32_t RSVD1[1]; + __IOM uint32_t DESCR[16]; + uint32_t RSVD2[16]; + __IOM uint32_t ALIAS_CTRL; + uint32_t RSVD3[3]; + __IOM uint32_t MODE_ALT1; + uint32_t RSVD4[3]; + __IOM uint32_t TM_TAPS; + __IOM uint32_t TM_TAPS_ADJ; + __IOM uint32_t TM_TAPS_CTRL; + uint32_t RSVD5[9]; + __IOM uint32_t LDMA_RX_DESCR_BM; + __IOM uint32_t LDMA_TX_DESCR_BM; + uint32_t RSVD6[2]; + QLDCH LDRX[3]; + QLDCH LDTX[3]; +} QMSPI_Type; + +/* ---------------- Host CPU Monitoring ---------------- */ + +/** @brief Processor Hot Interface (PROCHOT) */ +typedef struct prochot_regs { + __IOM uint32_t CUMUL_COUNT; /*!< (@ 0x0000) PROCHOT Cumulative Count */ + __IOM uint32_t DUTY_COUNT; /*!< (@ 0x0004) PROCHOT Duty cycle count */ + __IOM uint32_t DUTY_PERIOD; /*!< (@ 0x0008) PROCHOT Duty cycle period */ + __IOM uint32_t CTRL_STS; /*!< (@ 0x000C) PROCHOT Control and Status */ + __IOM uint32_t ASSERT_COUNT; /*!< (@ 0x0010) PROCHOT Assertion counter */ + __IOM uint32_t ASSERT_LIMIT; /*!< (@ 0x0014) PROCHOT Assertion limit */ +} PROCHOT_Type; + +/** @brief Platform Enviroment Control Interface Registers (PECI) + * !< (@ 0x0000) PECI Write Data + * !< (@ 0x0004) PECI Read data + * !< (@ 0x0008) PECI Control + * !< (@ 0x000C) PECI Status 1 + * !< (@ 0x0010) PECI Status 2 + * !< (@ 0x0014) PECI Error + * !< (@ 0x0018) PECI Interrupt Enable 1 + * !< (@ 0x001C) PECI Interrupt Enable 2 + * !< (@ 0x0020) PECI Optimal Bit Time LSB + * !< (@ 0x0024) PECI Optimal Bit Time MSB + */ +typedef struct peci_regs { + __IOM uint8_t WR_DATA; + uint8_t RSVD1[3]; + __IOM uint8_t RD_DATA; + uint8_t RSVD2[3]; + __IOM uint8_t CONTROL; + uint8_t RSVD3[3]; + __IOM uint8_t STATUS1; + uint8_t RSVD4[3]; + __IOM uint8_t STATUS2; + uint8_t RSVD5[3]; + __IOM uint8_t ERROR; + uint8_t RSVD6[3]; + __IOM uint8_t INT_EN1; + uint8_t RSVD7[3]; + __IOM uint8_t INT_EN2; + uint8_t RSVD8[3]; + __IOM uint8_t OPT_BIT_TIME_LSB; + uint8_t RSVD9[3]; + __IOM uint8_t OPT_BIT_TIME_MSB; + uint8_t RSVD10[87]; /* 0x25 - 0x7C */ +} PECI_Type; + +/* ---------------- Fan Control -------------------- */ + +/** @brief Pulse Width Modulator Registers (PWM) + * !< (@ 0x0000) PWM Counter ON b[15:0] + * !< (@ 0x0004) PWM Counter OFF b[15:0] + * !< (@ 0x0008) PWM Configuration b[7:0] + */ +typedef struct pwm_regs { + __IOM uint32_t COUNT_ON; + __IOM uint32_t COUNT_OFF; + __IOM uint32_t CONFIG; +} PWM_Type; + +/** @brief Tachometer Registers (TACH) + * !< (@ 0x0000) TACH Control b[31:0] + * !< (@ 0x0004) TACH Status b[7:0] + * !< (@ 0x0008) TACH High LImit b[15:0] + * !< (@ 0x000C) TACH Low Limit b[15:0] + */ +typedef struct tach_regs { + __IOM uint32_t CONTROL; + __IOM uint32_t STATUS; + __IOM uint32_t LIMIT_HI; + __IOM uint32_t LIMIT_LO; +} TACH_Type; + +/** @brief RPM to PWM Fan Registers (RPMFAN) */ +typedef struct rpmfan_regs { + __IOM uint16_t FAN_SETTING; /*!< (@ 0x0000) RPMFAN Fan Settings */ + __IOM uint16_t FAN_CONFIG; /*!< (@ 0x0002) RPMFAN Fan Config */ + __IOM uint8_t PWM_DIVIDE; /*!< (@ 0x0004) RPMFAN PWM Divider */ + __IOM uint8_t GAIN; /*!< (@ 0x0005) RPMFAN Gain */ + __IOM uint8_t FSPU_CFG; /*!< (@ 0x0006) RPMFAN Fan Spin-up config */ + __IOM uint8_t FAN_STEP; /*!< (@ 0x0007) RPMFAN Fan Step */ + __IOM uint8_t FAN_MIN_DRV; /*!< (@ 0x0008) RPMFAN Fan Minimum drive */ + __IOM uint8_t VALID_TACH_CNT; /*!< (@ 0x0009) RPMFAN Valid TACH count */ + __IOM uint16_t FAN_DFB; /*!< (@ 0x000A) RPMFAN Fan driver fail band */ + __IOM uint16_t TACH_TARGET; /*!< (@ 0x000C) RPMFAN TACH target */ + __IOM uint16_t TACH_READING; /*!< (@ 0x000E) RPMFAN TACH reading */ + __IOM uint8_t PWM_DBF; /*!< (@ 0x0010) RPMFAN PWM driver base freq. */ + __IOM uint8_t FAN_STATUS; /*!< (@ 0x0011) RPMFAN PWM driver base freq. */ + uint8_t RSVD1[6]; +} RPMFAN_Type; + +/* ---------------- Keyboard, PS/2, Key scan matrix -------------------- */ + +/** @brief Keyboard Scan Matrix Registers (KSCAN) */ +typedef struct kscan_regs { + uint32_t RSVD[1]; + __IOM uint32_t KSO_SEL; /*!< (@ 0x0004) KSO Select */ + __IOM uint32_t KSI_IN; /*!< (@ 0x0008) KSI Input States */ + __IOM uint32_t KSI_STS; /*!< (@ 0x000C) KSI Status */ + __IOM uint32_t KSI_IEN; /*!< (@ 0x0010) KSI Interrupt Enable */ + __IOM uint32_t EXT_CTRL; /*!< (@ 0x0014) Extended Control */ +} KSCAN_Type; + +/** @brief Emulated 8042 Keyboard Controller Registers (KBC) */ +typedef struct kbc_regs { + __IOM uint32_t HOST_AUX_DATA; /*!< (@ 0x0000) EC_HOST and AUX Data */ + __IOM uint32_t KBC_STS_RD; /*!< (@ 0x0004) Keyboard Status Read */ + uint8_t RSVD1[0x100u - 0x08u]; + __IOM uint32_t EC_DATA; /*!< (@ 0x0100) EC Data */ + __IOM uint32_t EC_KBC_STS; /*!< (@ 0x0104) EC KBC Status */ + __IOM uint32_t KBC_CTRL; /*!< (@ 0x0108) KBC Control */ + __IOM uint32_t EC_AUX_DATA; /*!< (@ 0x010C) EC Aux Data */ + uint32_t RSVD2[1]; + __IOM uint32_t PCOBF; /*!< (@ 0x0114) PCOBF register */ + uint8_t RSVD3[0x0330ul - 0x0118ul]; + __IOM uint32_t KBC_PORT92_EN; /*!< (@ 0x0330) Port92h enable */ +} KBC_Type; + +/** @brief Fast Port92h Registers (PORT92) */ +typedef struct port92_regs { + __IOM uint32_t HOST_P92; /*!< (@ 0x0000) HOST Port92h register */ + uint8_t RSVD1[0x100u - 0x04u]; + __IOM uint32_t GATEA20_CTRL; /*!< (@ 0x0100) Gate A20 Control */ + uint32_t RSVD2[1]; + __IOM uint32_t SETGA20L; /*!< (@ 0x0108) Set Gate A20 */ + __IOM uint32_t RSTGA20L; /*!< (@ 0x010C) Reset Gate A20 */ + uint8_t RSVD3[0x0330ul - 0x0110ul]; + __IOM uint32_t ACTV; /*!< (@ 0x0330) Logical device Activate */ +} PORT92_Type; + +/** @brief PS/2 Controller Registers (PS2) */ +typedef struct ps2_regs { + __IOM uint32_t TRX_BUFF; /*!< (@ 0x0000) PS/2 Transmit buffer(WO), + Receive buffer(RO) */ + __IOM uint32_t CTRL; /*!< (@ 0x0004) PS/2 Control */ + __IOM uint32_t STATUS; /*!< (@ 0x0008) PS/2 Status */ +} PS2_Type; + +/* ---------------- VBAT Powered Features ---------------- */ +/** @brief VBAT Register Bank (VBATR) */ +typedef struct vbatr_regs { + __IOM uint32_t PFRS; /*! (@ 0x0000) VBATR Power Fail Reset Status */ + uint32_t RSVD1[1]; + __IOM uint32_t CLK32_SRC; /*! (@ 0x0008) VBATR 32K clock source */ + uint32_t RSVD2[5]; + __IOM uint32_t MCNT_LO; /*! (@ 0x0020) VBATR monotonic count lo */ + __IOM uint32_t MCNT_HI; /*! (@ 0x0024) VBATR monotonic count hi */ + uint32_t RSVD3[3]; + __IOM uint32_t EMBRD_EN; /*! (@ 0x0034) VBATR Embedded Reset + De-bounce Enable */ +} VBATR_Type; + +/** @brief VBAT Memory (VBATM) */ +typedef struct vbatm_regs { + union vbmem_u { + uint32_t u32[128U / 4U]; + uint16_t u16[128U / 2U]; + uint8_t u8[128U]; + } MEM; +} VBATM_Type; + +/** @brief VBAT powered control interface (VCI) */ +typedef struct vci_regs { + __IOM uint32_t CONFIG; /*! (@ 0x0000) VCI Config register */ + __IOM uint32_t LATCH_EN; /*! (@ 0x0004) VCI Latch enable register */ + __IOM uint32_t LATCH_RST; /*! (@ 0x0008) VCI Latch resets register */ + __IOM uint32_t INPUT_EN; /*! (@ 0x000C) VCI Input enable register */ + __IOM uint32_t HOLD_OFF; /*! (@ 0x0010) VCI Hold off count register */ + __IOM uint32_t POLARITY; /*! (@ 0x0014) VCI Polarity register */ + __IOM uint32_t + PEDGE_DET; /*! (@ 0x0018) VCI Positive edge detect register */ + __IOM uint32_t + NEDGE_DET; /*! (@ 0x001C) VCI Negative edge detect register */ + __IOM uint32_t BUFFER_EN; /*! (@ 0x0020) VCI Buffer enable register */ +} VCI_Type; + +/* ---------------- Miscellaneous Interfaces ---------------- */ + +/** @brief Breathing-Blinking LED (LED) */ +typedef struct led_regs { + __IOM uint32_t CFG; /*!< (@ 0x0000) LED configuration */ + __IOM uint32_t LIMIT; /*!< (@ 0x0004) LED limits */ + __IOM uint32_t DLY; /*!< (@ 0x0008) LED delay */ + __IOM uint32_t STEP; /*!< (@ 0x000C) LED update step size */ + __IOM uint32_t INTRVL; /*!< (@ 0x0010) LED update interval */ + __IOM uint32_t OUTDLY; /*!< (@ 0x0014) LED output delay */ +} LED_Type; + +/** @brief BC-Link Controller (BCL) */ +typedef struct bcl_regs { + __IOM uint32_t STATUS; /*!< (@ 0x0000) BCL Status */ + __IOM uint32_t TADDR; /*!< (@ 0x0004) BCL Target address */ + __IOM uint32_t DATA; /*!< (@ 0x0008) BCL Data */ + __IOM uint32_t CLKSEL; /*!< (@ 0x000C) BCL Clock select */ +} BCL_Type; + +/** @brief Glue Logic registers (GLUE) */ +typedef struct glue_regs { + uint32_t RSVD1[1]; + __IOM uint32_t S0IX_DET_EN; /*!< (@ 0x0004) S0ix detect enable */ + uint32_t RSVD2[(0x10Cu - 0x008u) / 4]; + __IOM uint32_t PWRGD_SRC_CFG; /*!< (@ 0x010C) PWRGD Source Config */ + __IOM uint32_t S0IX_DET_CFG; /*!< (@ 0x0110) S0ix detect config */ + uint32_t RSVD3[5]; + __IOM uint32_t MON_STATE; /*!< (@ 0x0128) Monitor state */ + __IOM uint32_t MON_IPEND; /*!< (@ 0x012C) Monitor Interrupt pending */ + __IOM uint32_t MON_IEN; /*!< (@ 0x0130) Monitor Intrrupt enable */ +} GLUE_Type; + +/* ---------------- Analog Interfaces ---------------- */ +/** @brief Analog to Digital Converter Registers (ADC) */ +typedef struct adc_regs { + __IOM uint32_t CONTROL; /*!< (@ 0x0000) ADC Control */ + __IOM uint32_t DELAY; /*!< (@ 0x0004) ADC Delay */ + __IOM uint32_t STATUS; /*!< (@ 0x0008) ADC Status */ + __IOM uint32_t SINGLE; /*!< (@ 0x000C) ADC Single */ + __IOM uint32_t REPEAT; /*!< (@ 0x0010) ADC Repeat */ + __IOM uint32_t RD[8]; /*!< (@ 0x0014 - 0x0033 ADC Chan 0-7 reading */ + uint8_t RSVD1[0x7C - 0x34]; + __IOM uint32_t CONFIG; /*!< (@ 0x007C) ADC Configuration */ + __IOM uint32_t VREF_CHAN_SEL; /*!< (@ 0x0080) ADC Vref Channel Sel. */ + __IOM uint32_t VREF_CTRL; /*!< (@ 0x0084) ADC Vref Control */ + __IOM uint32_t SARADC_CTRL; /*!< (@ 0x0088) SAR ARD Control */ +} ADC_Type; + +/** @brief RC-ID */ +typedef struct rcid_regs { + __IOM uint32_t CTRL; /*!< (@ 0x0000) RCID Control */ + __IOM uint32_t DATA; /*!< (@ 0x0004) RCID Data */ +} RCID_Type; + +/* ---------------- Chip Configuration/Control ---------------- */ +/** @brief Glocal Configuration Registers (GLOBAL_CFG) + * !< (@ 0x0002) MCHP Test + * !< (@ 0x0007) Global Config Logical Device Number + * !< (@ 0x001C) Device and revision ID + * !< (@ 0x0020) Legacy Device ID + */ +typedef struct global_cfg_regs { + __IOM uint8_t RSVD0[2]; + __IOM uint8_t TEST02; + __IOM uint8_t RSVD1[4]; + __IOM uint8_t LOG_DEV_NUM; + __IOM uint8_t RSVD2[20]; + __IOM uint32_t DEV_REV_ID; + __IOM uint8_t LEGACY_DEV_ID; + __IOM uint8_t RSVD3[14]; +} GLOBAL_CFG_Type; + +/** @brief EC Subsystem (ECS) */ +typedef struct ecs_regs { + uint32_t RSVD1[1]; + __IOM uint32_t AHB_ERR_ADDR; /*!< (@ 0x0004) ECS AHB Error Address */ + uint32_t RSVD2[2]; + __IOM uint32_t OSC_ID; /*!< (@ 0x0010) ECS ID register */ + __IOM uint32_t AHB_ERR_CTRL; /*!< (@ 0x0014) ECS AHB Error Control */ + __IOM uint32_t INTR_CTRL; /*!< (@ 0x0018) ECS Interupt Control */ + __IOM uint32_t ETM_CTRL; /*!< (@ 0x001C) ECS ETM Trace Control */ + __IOM uint32_t DEBUG_CTRL; /*!< (@ 0x0020) ECS Debug Control */ + __IOM uint32_t OTP_LOCK; /*!< (@ 0x0024) ECS OTP Lock Enable */ + __IOM uint32_t WDT_CNT; /*!< (@ 0x0028) ECS WDT Event Count */ + uint32_t RSVD3[5]; + __IOM uint32_t PECI_DIS; /*!< (@ 0x0040) ECS PECI Disable */ + uint32_t RSVD4[3]; + __IOM uint32_t VCI_FW_OVR; /*!< (@ 0x0050) ECS VCI FW Override */ + uint32_t RSVD5[1]; + __IOM uint32_t CRYPTO_CFG; /*!< (@ 0x0058) ECS Crypto Config */ + uint32_t RSVD6[5]; + __IOM uint32_t JTAG_MCFG; /*!< (@ 0x0070) ECS JTAG Master Config */ + __IOM uint32_t JTAG_MSTS; /*!< (@ 0x0074) ECS JTAG Master Status */ + __IOM uint32_t JTAG_MTDO; /*!< (@ 0x0078) ECS JTAG Master TDO */ + __IOM uint32_t JTAG_MTDI; /*!< (@ 0x007C) ECS JTAG Master TDI */ + __IOM uint32_t JTAG_MTMS; /*!< (@ 0x0080) ECS JTAG Master TMS */ + __IOM uint32_t JTAG_MCMD; /*!< (@ 0x0084) ECS JTAG Master Command */ + uint32_t RSVD7[2]; + __IOM uint32_t VW_FW_OVR; /*!< (@ 0x0090) ECS VWire Source Config */ + __IOM uint32_t CMP_CTRL; /*!< (@ 0x0094) ECS Analog Comparator Control */ + __IOM uint32_t CMP_SLP_CTRL; /*!< (@ 0x0098) ECS Analog Comparator + Sleep Control */ + uint32_t RSVD8[(0x144 - 0x9C) / 4]; + __IOM uint32_t SLP_STS_MIRROR; /*!< (@ 0x0144) ECS Sleep Status + Mirror (RO) */ +} ECS_Type; + +/** @brief Power Control Reset (PCR) + * SYS_SLP_CTRL (@ 0x0000) System Sleep Control + * PROC_CLK_CTRL (@ 0x0004) CPU Clock Control + * SLOW_CLK_CTRL (@ 0x0008) Slow Clock Control + * OSC_ID (@ 0x000C) Processor Clock Control + * PWR_RST_STS (@ 0x0010) Power Reset Status + * PWR_RST_CTRL (@ 0x0014) Power Reset Control + * SYS_RST (@ 0x0018) System Reset + * TURBO_CLK (@ 0x001C) Fast clock: CPU, SRAM, PMC, CacheCtrl, + * QMSPI, Crypto + * SLP_EN[5] (@ 0x0030) Sleep Enable 0 - 4 + * CLK_REQ[5] (@ 0x0050) PCR Clock Req 0-4 (RO) + * RST_EN[5] (@ 0x0070) PCR Peripheral Reset 0 - 4 + * RST_EN_LOCK (@ 0x0084) PCR Peripheral Lock + * VBAT_SRST (@ 0x0088) PCR VBAT Soft Reset + * CLK32K_SRC_VTR (@ 0x008C) PCR 32K Clock Source + * CNT32K_PER (@ 0x00C0) PCR 32K period counter + * CNT32K_PULSE_HI (@ 0x00C4) PCR 32K pulse hi counter + * CNT32K_PER_MIN (@ 0x00C8) PCR 32K mininum period count + * CNT32K_PER_MAX (@ 0x00CC) PCR 32K maximum period count + * CNT32K_DV (@ 0x00D0) PCR 32K Duty variation + * CNT32K_DV_MAX (@ 0x00D4 PCR 32K Duty variation maximum + * CNT32K_VALID (@ 0x00D8) PCR 32K Counter valid + * CNT32K_VALID_MIN (@ 0x00DC) PCR 32K counter valid minimum + * CNT32K_CTRL (@ 0x00E0) PCR 32K counter control + * CLK32K_MON_ISTS (@ 0x00E4) PCR 32K Monitor interrupt status + * CLK32K_MON_IEN (@ 0x00E8) PCR 32K Monitor interrupt enable + */ +typedef struct pcr_regs { + __IOM uint32_t SYS_SLP_CTRL; + __IOM uint32_t PROC_CLK_CTRL; + __IOM uint32_t SLOW_CLK_CTRL; + __IOM uint32_t OSC_ID; + __IOM uint32_t PWR_RST_STS; + __IOM uint32_t PWR_RST_CTRL; + __IOM uint32_t SYS_RST; + __IOM uint32_t TURBO_CLK; + __IOM uint32_t TEST20; + uint32_t RSVD1[3]; + __IOM uint32_t SLP_EN[5]; + uint32_t RSVD2[3]; + __IOM uint32_t CLK_REQ[5]; + uint32_t RSVD3[3]; + __IOM uint32_t RST_EN[5]; + __IOM uint32_t RST_EN_LOCK; + __IOM uint32_t VBAT_SRST; + __IOM uint32_t CLK32K_SRC_VTR; + __IOM uint32_t TEST90; + uint32_t RSVD4[(0x00C0 - 0x0094) / 4]; + __IOM uint32_t CNT32K_PER; + __IOM uint32_t CNT32K_PULSE_HI; + __IOM uint32_t CNT32K_PER_MIN; + __IOM uint32_t CNT32K_PER_MAX; + __IOM uint32_t CNT32K_DV; + __IOM uint32_t CNT32K_DV_MAX; + __IOM uint32_t CNT32K_VALID; + __IOM uint32_t CNT32K_VALID_MIN; + __IOM uint32_t CNT32K_CTRL; + __IOM uint32_t CLK32K_MON_ISTS; + __IOM uint32_t CLK32K_MON_IEN; +} PCR_Type; + +/* -------------------- GPIO -------------------- */ + +/** @brief All GPIO register as arrays of registers + * CTRL (@ 0x000 - 0x2FF) Sparse array of GPIO 32-bit Control registers + * PARIN (@ 0x300 - 0x317) Array of GPIO Parallel input 32-bit registers + * PAROUT (@ 0x380 - 0x397) Array of GPIO Parallel output 32-bit registers + * LOCK (@ 0x3EC - 0x3FF) Array of GPIO Lock 32-bit registers (write-once) + * CTRL2 (@ 0x500 - 0x7FF) Sparse array of GPIO 32-bit Control 2 registers + */ +typedef struct gpio_regs { + __IOM uint32_t CTRL[192]; + __IOM uint32_t PARIN[6]; + uint32_t RSVD1[(0x380u - 0x318u) / 4]; + __IOM uint32_t PAROUT[6]; + uint32_t RSVD2[(0x3ECu - 0x398u) / 4u]; + __IOM uint32_t LOCK[6]; + uint32_t RSVD3[(0x500u - 0x400u) / 4u]; + __IOM uint32_t CTRL2[192]; +} GPIO_Type; + +/** @brief GPIO control registers by pin name */ +typedef struct gpio_ctrl_regs { + __IOM uint32_t CTRL_0000; /*!< (@ 0x0000) GPIO_0000 Control */ + uint32_t RSVD1[1]; + __IOM uint32_t CTRL_0002; /*!< (@ 0x0008) GPIO_0002 Control */ + __IOM uint32_t CTRL_0003; /*!< (@ 0x000C) GPIO_0003 Control */ + __IOM uint32_t CTRL_0004; /*!< (@ 0x0010) GPIO_0004 Control */ + uint32_t RSVD2[2]; + __IOM uint32_t CTRL_0007; /*!< (@ 0x001C) GPIO_0007 Control */ + __IOM uint32_t CTRL_0010; /*!< (@ 0x0020) GPIO_0010 Control */ + __IOM uint32_t CTRL_0011; + __IOM uint32_t CTRL_0012; + __IOM uint32_t CTRL_0013; + __IOM uint32_t CTRL_0014; /*!< (@ 0x0030) GPIO_0014 Control */ + __IOM uint32_t CTRL_0015; + __IOM uint32_t CTRL_0016; + __IOM uint32_t CTRL_0017; + __IOM uint32_t CTRL_0020; /*!< (@ 0x0040) GPIO_0020 Control */ + __IOM uint32_t CTRL_0021; + __IOM uint32_t CTRL_0022; + __IOM uint32_t CTRL_0023; + __IOM uint32_t CTRL_0024; /*!< (@ 0x0050) GPIO_0024 Control */ + __IOM uint32_t CTRL_0025; + __IOM uint32_t CTRL_0026; + __IOM uint32_t CTRL_0027; + __IOM uint32_t CTRL_0030; /*!< (@ 0x0060) GPIO_0030 Control */ + __IOM uint32_t CTRL_0031; + __IOM uint32_t CTRL_0032; + __IOM uint32_t CTRL_0033; + __IOM uint32_t CTRL_0034; + __IOM uint32_t CTRL_0035; + __IOM uint32_t CTRL_0036; /*!< (@ 0x0078) GPIO_0036 Control */ + uint32_t RSVD3[1]; + __IOM uint32_t CTRL_0040; /*!< (@ 0x0080) GPIO_0040 Control */ + uint32_t RSVD4[1]; + __IOM uint32_t CTRL_0042; /*!< (@ 0x0088) GPIO_0042 Control */ + __IOM uint32_t CTRL_0043; /*!< (@ 0x008C) GPIO_0043 Control */ + __IOM uint32_t CTRL_0044; /*!< (@ 0x0090) GPIO_0044 Control */ + __IOM uint32_t CTRL_0045; + __IOM uint32_t CTRL_0046; + __IOM uint32_t CTRL_0047; + __IOM uint32_t CTRL_0050; /*!< (@ 0x00A0) GPIO_0050 Control */ + __IOM uint32_t CTRL_0051; + __IOM uint32_t CTRL_0052; + __IOM uint32_t CTRL_0053; + __IOM uint32_t CTRL_0054; /*!< (@ 0x00B0) GPIO_0054 Control */ + __IOM uint32_t CTRL_0055; + __IOM uint32_t CTRL_0056; + __IOM uint32_t CTRL_0057; + __IOM uint32_t CTRL_0060; /*!< (@ 0x00C0) GPIO_0060 Control */ + __IOM uint32_t CTRL_0061; + __IOM uint32_t CTRL_0062; + __IOM uint32_t CTRL_0063; + __IOM uint32_t CTRL_0064; /*!< (@ 0x00D0) GPIO_0064 Control */ + __IOM uint32_t CTRL_0065; + __IOM uint32_t CTRL_0066; + __IOM uint32_t CTRL_0067; + __IOM uint32_t CTRL_0070; /*!< (@ 0x00E0) GPIO_0070 Control */ + __IOM uint32_t CTRL_0071; + __IOM uint32_t CTRL_0072; + __IOM uint32_t CTRL_0073; /*!< (@ 0x00EC) GPIO_0073 Control */ + uint32_t RSVD5[4]; + __IOM uint32_t CTRL_0100; /*!< (@ 0x0100) GPIO_0100 Control */ + __IOM uint32_t CTRL_0101; + __IOM uint32_t CTRL_0102; + uint32_t RSVD6[1]; + __IOM uint32_t CTRL_0104; /*!< (@ 0x0110) GPIO_0104 Control */ + __IOM uint32_t CTRL_0105; + __IOM uint32_t CTRL_0106; + __IOM uint32_t CTRL_0107; /*!< (@ 0x011C) GPIO_0107 Control */ + uint32_t RSVD7[2]; + __IOM uint32_t CTRL_0112; /*!< (@ 0x0128) GPIO_0112 Control */ + __IOM uint32_t CTRL_0113; + __IOM uint32_t CTRL_0114; + __IOM uint32_t CTRL_0115; /*!< (@ 0x0134) GPIO_0115 Control */ + uint32_t RSVD8[2]; + __IOM uint32_t CTRL_0120; /*!< (@ 0x0140) GPIO_0120 Control */ + __IOM uint32_t CTRL_0121; + __IOM uint32_t CTRL_0122; + __IOM uint32_t CTRL_0123; + __IOM uint32_t CTRL_0124; /*!< (@ 0x0150) GPIO_0124 Control */ + __IOM uint32_t CTRL_0125; + __IOM uint32_t CTRL_0126; + __IOM uint32_t CTRL_0127; /*!< (@ 0x015C) GPIO_0127 Control */ + __IOM uint32_t CTRL_0130; /*!< (@ 0x0160) GPIO_0130 Control */ + __IOM uint32_t CTRL_0131; /*!< (@ 0x0164) GPIO_0131 Control */ + __IOM uint32_t CTRL_0132; /*!< (@ 0x0168) GPIO_0132 Control */ + uint32_t RSVD9[5]; + __IOM uint32_t CTRL_0140; /*!< (@ 0x0180) GPIO_0140 Control */ + __IOM uint32_t CTRL_0141; + __IOM uint32_t CTRL_0142; + __IOM uint32_t CTRL_0143; + __IOM uint32_t CTRL_0144; /*!< (@ 0x0190) GPIO_0144 Control */ + __IOM uint32_t CTRL_0145; + __IOM uint32_t CTRL_0146; + __IOM uint32_t CTRL_0147; /*!< (@ 0x019C) GPIO_0147 Control */ + __IOM uint32_t CTRL_0150; /*!< (@ 0x01A0) GPIO_0150 Control */ + __IOM uint32_t CTRL_0151; + __IOM uint32_t CTRL_0152; + __IOM uint32_t CTRL_0153; + __IOM uint32_t CTRL_0154; /*!< (@ 0x01B0) GPIO_0154 Control */ + __IOM uint32_t CTRL_0155; + __IOM uint32_t CTRL_0156; + __IOM uint32_t CTRL_0157; /*!< (@ 0x01BC) GPIO_0157 Control */ + uint32_t RSVD10[1]; + __IOM uint32_t CTRL_0161; /*!< (@ 0x01C4) GPIO_0161 Control */ + __IOM uint32_t CTRL_0162; + uint32_t RSVD11[2]; + __IOM uint32_t CTRL_0165; /*!< (@ 0x01D4) GPIO_0165 Control */ + uint32_t RSVD12[2]; + __IOM uint32_t CTRL_0170; /*!< (@ 0x01E0) GPIO_0170 Control */ + __IOM uint32_t CTRL_0171; /*!< (@ 0x01E4) GPIO_0171 Control */ + uint32_t RSVD13[3]; + __IOM uint32_t CTRL_0175; /*!< (@ 0x01F4) GPIO_0175 Control */ + uint32_t RSVD14[2]; + __IOM uint32_t CTRL_0200; /*!< (@ 0x0200) GPIO_0200 Control */ + __IOM uint32_t CTRL_0201; + __IOM uint32_t CTRL_0202; + __IOM uint32_t CTRL_0203; + __IOM uint32_t CTRL_0204; /*!< (@ 0x0210) GPIO_0204 Control */ + __IOM uint32_t CTRL_0205; + __IOM uint32_t CTRL_0206; + __IOM uint32_t CTRL_0207; /*!< (@ 0x021C) GPIO_0207 Control */ + uint32_t RSVD15[9]; + __IOM uint32_t CTRL_0221; /*!< (@ 0x0244) GPIO_0221 Control */ + __IOM uint32_t CTRL_0222; + __IOM uint32_t CTRL_0223; + __IOM uint32_t CTRL_0224; /*!< (@ 0x0250) GPIO_0224 Control */ + uint32_t RSVD16[1]; + __IOM uint32_t CTRL_0226; + __IOM uint32_t CTRL_0227; /*!< (@ 0x025C) GPIO_0227 Control */ + uint32_t RSVD17[8]; + __IOM uint32_t CTRL_0240; /*!< (@ 0x0280) GPIO_0240 Control */ + __IOM uint32_t CTRL_0241; + __IOM uint32_t CTRL_0242; + __IOM uint32_t CTRL_0243; /*!< (@ 0x028C) GPIO_0243 Control */ + __IOM uint32_t CTRL_0244; /*!< (@ 0x0290) GPIO_0244 Control */ + __IOM uint32_t CTRL_0245; /*!< (@ 0x0294) GPIO_0245 Control */ + __IOM uint32_t CTRL_0246; /*!< (@ 0x0298) GPIO_0246 Control */ + uint32_t RSVD18[5]; + __IOM uint32_t CTRL_0254; /*!< (@ 0x02B0) GPIO_0254 Control */ + __IOM uint32_t CTRL_0255; /*!< (@ 0x02B4) GPIO_0255 Control */ +} GPIO_CTRL_Type; + +/** @brief GPIO Control 2 registers by pin name */ +typedef struct gpio_ctrl2_regs { + __IOM uint32_t CTRL2_0000; /*!< (@ 0x0000) GPIO_0000 Control 2 */ + uint32_t RSVD1[1]; + __IOM uint32_t CTRL2_0002; /*!< (@ 0x0008) GPIO_0002 Control 2 */ + __IOM uint32_t CTRL2_0003; /*!< (@ 0x000C) GPIO_0003 Control 2 */ + __IOM uint32_t CTRL2_0004; /*!< (@ 0x0010) GPIO_0004 Control 2 */ + uint32_t RSVD2[2]; + __IOM uint32_t CTRL2_0007; /*!< (@ 0x001C) GPIO_0007 Control 2 */ + __IOM uint32_t CTRL2_0010; /*!< (@ 0x0020) GPIO_0010 Control 2 */ + __IOM uint32_t CTRL2_0011; + __IOM uint32_t CTRL2_0012; + __IOM uint32_t CTRL2_0013; + __IOM uint32_t CTRL2_0014; /*!< (@ 0x0030) GPIO_0014 Control 2 */ + __IOM uint32_t CTRL2_0015; + __IOM uint32_t CTRL2_0016; + __IOM uint32_t CTRL2_0017; + __IOM uint32_t CTRL2_0020; /*!< (@ 0x0040) GPIO_0020 Control 2 */ + __IOM uint32_t CTRL2_0021; + __IOM uint32_t CTRL2_0022; + __IOM uint32_t CTRL2_0023; + __IOM uint32_t CTRL2_0024; /*!< (@ 0x0050) GPIO_0024 Control 2 */ + __IOM uint32_t CTRL2_0025; + __IOM uint32_t CTRL2_0026; + __IOM uint32_t CTRL2_0027; + __IOM uint32_t CTRL2_0030; /*!< (@ 0x0060) GPIO_0030 Control 2 */ + __IOM uint32_t CTRL2_0031; + __IOM uint32_t CTRL2_0032; + __IOM uint32_t CTRL2_0033; + __IOM uint32_t CTRL2_0034; + __IOM uint32_t CTRL2_0035; + __IOM uint32_t CTRL2_0036; /*!< (@ 0x0078) GPIO_0036 Control 2 */ + uint32_t RSVD3[1]; + __IOM uint32_t CTRL2_0040; /*!< (@ 0x0080) GPIO_0040 Control 2 */ + uint32_t RSVD4[1]; + __IOM uint32_t CTRL2_0042; /*!< (@ 0x0088) GPIO_0042 Control 2 */ + __IOM uint32_t CTRL2_0043; /*!< (@ 0x008C) GPIO_0043 Control 2 */ + __IOM uint32_t CTRL2_0044; /*!< (@ 0x0090) GPIO_0044 Control 2 */ + __IOM uint32_t CTRL2_0045; + __IOM uint32_t CTRL2_0046; + __IOM uint32_t CTRL2_0047; + __IOM uint32_t CTRL2_0050; /*!< (@ 0x00A0) GPIO_0050 Control 2 */ + __IOM uint32_t CTRL2_0051; + __IOM uint32_t CTRL2_0052; + __IOM uint32_t CTRL2_0053; + __IOM uint32_t CTRL2_0054; /*!< (@ 0x00B0) GPIO_0054 Control 2 */ + __IOM uint32_t CTRL2_0055; + __IOM uint32_t CTRL2_0056; + __IOM uint32_t CTRL2_0057; + __IOM uint32_t CTRL2_0060; /*!< (@ 0x00C0) GPIO_0060 Control 2 */ + __IOM uint32_t CTRL2_0061; + __IOM uint32_t CTRL2_0062; + __IOM uint32_t CTRL2_0063; + __IOM uint32_t CTRL2_0064; /*!< (@ 0x00D0) GPIO_0064 Control 2 */ + __IOM uint32_t CTRL2_0065; + __IOM uint32_t CTRL2_0066; + __IOM uint32_t CTRL2_0067; + __IOM uint32_t CTRL2_0070; /*!< (@ 0x00E0) GPIO_0070 Control 2 */ + __IOM uint32_t CTRL2_0071; + __IOM uint32_t CTRL2_0072; + __IOM uint32_t CTRL2_0073; /*!< (@ 0x00EC) GPIO_0073 Control 2 */ + uint32_t RSVD5[4]; + __IOM uint32_t CTRL2_0100; /*!< (@ 0x0100) GPIO_0100 Control 2 */ + __IOM uint32_t CTRL2_0101; + __IOM uint32_t CTRL2_0102; + uint32_t RSVD6[1]; + __IOM uint32_t CTRL2_0104; /*!< (@ 0x0110) GPIO_0104 Control 2 */ + __IOM uint32_t CTRL2_0105; + __IOM uint32_t CTRL2_0106; + __IOM uint32_t CTRL2_0107; /*!< (@ 0x011C) GPIO_0107 Control 2 */ + uint32_t RSVD7[2]; + __IOM uint32_t CTRL2_0112; /*!< (@ 0x0128) GPIO_0112 Control 2 */ + __IOM uint32_t CTRL2_0113; + __IOM uint32_t CTRL2_0114; + __IOM uint32_t CTRL2_0115; /*!< (@ 0x0134) GPIO_0115 Control 2 */ + uint32_t RSVD8[2]; + __IOM uint32_t CTRL2_0120; /*!< (@ 0x0140) GPIO_0120 Control 2 */ + __IOM uint32_t CTRL2_0121; + __IOM uint32_t CTRL2_0122; + __IOM uint32_t CTRL2_0123; + __IOM uint32_t CTRL2_0124; /*!< (@ 0x0150) GPIO_0124 Control 2 */ + __IOM uint32_t CTRL2_0125; + __IOM uint32_t CTRL2_0126; + __IOM uint32_t CTRL2_0127; /*!< (@ 0x015C) GPIO_0127 Control 2 */ + __IOM uint32_t CTRL2_0130; /*!< (@ 0x0160) GPIO_0130 Control 2 */ + __IOM uint32_t CTRL2_0131; /*!< (@ 0x0164) GPIO_0131 Control 2 */ + __IOM uint32_t CTRL2_0132; /*!< (@ 0x0168) GPIO_0132 Control 2 */ + uint32_t RSVD9[5]; + __IOM uint32_t CTRL2_0140; /*!< (@ 0x0180) GPIO_0140 Control 2 */ + __IOM uint32_t CTRL2_0141; + __IOM uint32_t CTRL2_0142; + __IOM uint32_t CTRL2_0143; + __IOM uint32_t CTRL2_0144; /*!< (@ 0x0190) GPIO_0144 Control 2 */ + __IOM uint32_t CTRL2_0145; + __IOM uint32_t CTRL2_0146; + __IOM uint32_t CTRL2_0147; /*!< (@ 0x019C) GPIO_0147 Control 2 */ + __IOM uint32_t CTRL2_0150; /*!< (@ 0x01A0) GPIO_0150 Control 2 */ + __IOM uint32_t CTRL2_0151; + __IOM uint32_t CTRL2_0152; + __IOM uint32_t CTRL2_0153; + __IOM uint32_t CTRL2_0154; /*!< (@ 0x01B0) GPIO_0154 Control 2 */ + __IOM uint32_t CTRL2_0155; + __IOM uint32_t CTRL2_0156; + __IOM uint32_t CTRL2_0157; /*!< (@ 0x01BC) GPIO_0157 Control 2 */ + uint32_t RSVD10[1]; + __IOM uint32_t CTRL2_0161; /*!< (@ 0x01C4) GPIO_0161 Control 2 */ + __IOM uint32_t CTRL2_0162; + uint32_t RSVD11[2]; + __IOM uint32_t CTRL2_0165; /*!< (@ 0x01D4) GPIO_0165 Control 2 */ + uint32_t RSVD12[2]; + __IOM uint32_t CTRL2_0170; /*!< (@ 0x01E0) GPIO_0170 Control 2 */ + __IOM uint32_t CTRL2_0171; /*!< (@ 0x01E4) GPIO_0171 Control 2 */ + uint32_t RSVD13[3]; + __IOM uint32_t CTRL2_0175; /*!< (@ 0x01F4) GPIO_0175 Control 2 */ + uint32_t RSVD14[2]; + __IOM uint32_t CTRL2_0200; /*!< (@ 0x0200) GPIO_0200 Control 2 */ + __IOM uint32_t CTRL2_0201; + __IOM uint32_t CTRL2_0202; + __IOM uint32_t CTRL2_0203; + __IOM uint32_t CTRL2_0204; /*!< (@ 0x0210) GPIO_0204 Control 2 */ + __IOM uint32_t CTRL2_0205; + __IOM uint32_t CTRL2_0206; + __IOM uint32_t CTRL2_0207; /*!< (@ 0x021C) GPIO_0207 Control 2 */ + uint32_t RSVD15[9]; + __IOM uint32_t CTRL2_0221; /*!< (@ 0x0244) GPIO_0221 Control 2 */ + __IOM uint32_t CTRL2_0222; + __IOM uint32_t CTRL2_0223; + __IOM uint32_t CTRL2_0224; /*!< (@ 0x0250) GPIO_0224 Control 2 */ + uint32_t RSVD16[1]; + __IOM uint32_t CTRL2_0226; + __IOM uint32_t CTRL2_0227; /*!< (@ 0x025C) GPIO_0227 Control 2 */ + uint32_t RSVD17[8]; + __IOM uint32_t CTRL2_0240; /*!< (@ 0x0280) GPIO_0240 Control 2 */ + __IOM uint32_t CTRL2_0241; + __IOM uint32_t CTRL2_0242; + __IOM uint32_t CTRL2_0243; /*!< (@ 0x028C) GPIO_0243 Control 2 */ + __IOM uint32_t CTRL2_0244; /*!< (@ 0x0290) GPIO_0244 Control 2 */ + __IOM uint32_t CTRL2_0245; /*!< (@ 0x0294) GPIO_0245 Control 2 */ + __IOM uint32_t CTRL2_0246; /*!< (@ 0x0298) GPIO_0246 Control 2 */ + uint32_t RSVD18[5]; + __IOM uint32_t CTRL2_0254; /*!< (@ 0x02B0) GPIO_0254 Control 2 */ + __IOM uint32_t CTRL2_0255; /*!< (@ 0x02B4) GPIO_0255 Control 2 */ +} GPIO_CTRL2_Type; + +/** @brief GPIO Parallel Input register. 32 GPIO pins per bank */ +typedef struct gpio_parin_regs { + __IOM uint32_t PARIN0; /*!< (@ 0x000) GPIO Parallel In [0000:0036] */ + __IOM uint32_t PARIN1; /*!< (@ 0x004) GPIO Parallel In [0040:0076] */ + __IOM uint32_t PARIN2; /*!< (@ 0x008) GPIO Parallel In [0100:0136] */ + __IOM uint32_t PARIN3; /*!< (@ 0x00C) GPIO Parallel In [0140:0176] */ + __IOM uint32_t PARIN4; /*!< (@ 0x010) GPIO Parallel In [0200:0236] */ + __IOM uint32_t PARIN5; /*!< (@ 0x014) GPIO Parallel In [0240:0276] */ +} GPIO_PARIN_Type; + +/** @brief GPIO Parallel Output register. 32 GPIO pins per bank */ +typedef struct gpio_parout_regs { + __IOM uint32_t PAROUT0; /*!< (@ 0x000) GPIO Parallel Out [0000:0036] */ + __IOM uint32_t PAROUT1; /*!< (@ 0x004) GPIO Parallel Out [0040:0076] */ + __IOM uint32_t PAROUT2; /*!< (@ 0x008) GPIO Parallel Out [0100:0136] */ + __IOM uint32_t PAROUT3; /*!< (@ 0x00C) GPIO Parallel Out [0140:0176] */ + __IOM uint32_t PAROUT4; /*!< (@ 0x010) GPIO Parallel Out [0200:0236] */ + __IOM uint32_t PAROUT5; /*!< (@ 0x014) GPIO Parallel Out [0240:0276] */ +} GPIO_PAROUT_Type; + +/** @brief GPIO Lock registers. 32 GPIO pins per bank. Write-once bits */ +typedef struct gpio_lock_regs { + __IOM uint32_t LOCK5; /*!< (@ 0x0000) GPIO Lock 5 */ + __IOM uint32_t LOCK4; /*!< (@ 0x0004) GPIO Lock 4 */ + __IOM uint32_t LOCK3; /*!< (@ 0x0008) GPIO Lock 3 */ + __IOM uint32_t LOCK2; /*!< (@ 0x000C) GPIO Lock 2 */ + __IOM uint32_t LOCK1; /*!< (@ 0x0010) GPIO Lock 1 */ + __IOM uint32_t LOCK0; /*!< (@ 0x0014) GPIO Lock 0 */ +} GPIO_LOCK_Type; + +/* ---------------- Debug ------------ */ + +/** @brief Trace FIFO Debug Port Registers (TFDP) */ +typedef struct tfdp_regs { + __IOM uint8_t DATA_OUT; /*!< (@ 0x0000) Data out shift register */ + uint8_t RSVD1[3]; + __IOM uint32_t CTRL; /*!< (@ 0x0004) Control register */ +} TFDP_Type; + +/*-------- Peripherals with Host interfaces --------*/ + +/** @brief Mailbox Registers (MBOX) */ +typedef struct mbox_regs { + __IOM uint8_t OS_IDX; /*!< (@ 0x0000) OS Index */ + __IOM uint8_t OS_DATA; /*!< (@ 0x0001) OS Data */ + uint8_t RSVD1[0x100u - 0x02u]; + __IOM uint32_t HOST_TO_EC; /*!< (@ 0x0100) Host to EC */ + __IOM uint32_t EC_TO_HOST; /*!< (@ 0x0104) EC to Host */ + __IOM uint32_t SMI_SRC; /*!< (@ 0x0108) SMI Source */ + __IOM uint32_t SMI_MASK; /*!< (@ 0x010C) SMI Mask */ + union { /*!< (@ 0x0110 - 0x12F) Mailboxes 0-31 */ + __IOM uint32_t MBX32[8]; + __IOM uint8_t MBX8[32]; + }; +} MBOX_Type; + +/** @brief ACPI EC Registers (ACPI_EC) */ +typedef struct acpi_ec_regs { + __IOM uint32_t OS_DATA; /*!< (@ 0x0000) OS Data */ + __IOM uint8_t OS_CMD_STS; /*!< (@ 0x0004) OS Command(WO), Status(RO) */ + __IOM uint8_t OS_BYTE_CTRL; /*!< (@ 0x0005) OS Byte Control */ + uint8_t RSVD1[0x100u - 0x06u]; + __IOM uint32_t EC2OS_DATA; /*!< (@ 0x0100) EC to OS Data */ + __IOM uint8_t EC_STS; /*!< (@ 0x0104) EC Status */ + __IOM uint8_t EC_BYTE_CTRL; /*!< (@ 0x0105) EC Byte Control */ + uint8_t RSVD2[2]; + __IOM uint32_t OS2EC_DATA; /*!< (@ 0x0108) OS to EC Data */ +} ACPI_EC_Type; + +/** @brief ACPI PM1 Registers (ACPI_PM1) */ +typedef struct acpi_pm1_regs { + __IOM uint8_t RT_STS1; /*!< (@ 0x0000) ACPI PM1 run time status 1 */ + __IOM uint8_t RT_STS2; /*!< (@ 0x0001) ACPI PM1 run time status 2 */ + __IOM uint8_t RT_EN1; /*!< (@ 0x0002) ACPI PM1 run time enable 1 */ + __IOM uint8_t RT_EN2; /*!< (@ 0x0003) ACPI PM1 run time enable 2 */ + __IOM uint8_t RT_CTRL1; /*!< (@ 0x0004) ACPI PM1 run time ctrl 1 */ + __IOM uint8_t RT_CTRL2; /*!< (@ 0x0005) ACPI PM1 run time ctrl 2 */ + __IOM uint8_t RT_CTRL21; /*!< (@ 0x0006) ACPI PM1 run time ctrl 21 */ + __IOM uint8_t RT_CTRL22; /*!< (@ 0x0007) ACPI PM1 run time ctrl 22 */ + uint8_t RSVD1[(0x100u - 0x008u)]; + __IOM uint8_t EC_STS1; /*!< (@ 0x0100) ACPI PM1 EC-only status 1 */ + __IOM uint8_t EC_STS2; /*!< (@ 0x0101) ACPI PM1 EC-only status 2 */ + __IOM uint8_t EC_EN1; /*!< (@ 0x0102) ACPI PM1 EC-only enable 1 */ + __IOM uint8_t EC_EN2; /*!< (@ 0x0103) ACPI PM1 EC-only enable 2 */ + __IOM uint8_t EC_CTRL1; /*!< (@ 0x0104) ACPI PM1 EC-only ctrl 1 */ + __IOM uint8_t EC_CTRL2; /*!< (@ 0x0105) ACPI PM1 EC-only ctrl 2 */ + __IOM uint8_t EC_CTRL21; /*!< (@ 0x0106) ACPI PM1 EC-only ctrl 21 */ + __IOM uint8_t EC_CTRL22; /*!< (@ 0x0107) ACPI PM1 EC-only ctrl 22 */ + uint8_t RSVD2[(0x0110u - 0x0108u)]; + __IOM uint8_t EC_PM_STS; /*!< (@ 0x0110) ACPI PM1 EC-only PM status */ + uint8_t RSVD3[3]; +} ACPI_PM1_Type; + +/** @brief UART interface (UART) */ +typedef struct uart_regs { + __IOM uint8_t RTXB; /*!< (@ 0x0000) UART RXB(RO), TXB(WO), + BRGD_LSB(RW LCR.DLAB=1) */ + __IOM uint8_t IER; /*!< (@ 0x0001) UART IER(RW), + BRGD_MSB(RW LCR.DLAB=1) */ + __IOM uint8_t IIR_FCR; /*!< (@ 0x0002) UART IIR(RO), FCR(WO) */ + __IOM uint8_t LCR; /*!< (@ 0x0003) UART Line Control(RW) */ + __IOM uint8_t MCR; /*!< (@ 0x0004) UART Modem Control(RW) */ + __IOM uint8_t LSR; /*!< (@ 0x0005) UART Line Status(RO) */ + __IOM uint8_t MSR; /*!< (@ 0x0006) UART Modem Status(RO) */ + __IOM uint8_t SCR; /*!< (@ 0x0007) UART Scratch(RW) */ + uint8_t RSVDA[0x330u - 0x08u]; + __IOM uint8_t ACTV; /*!< (@ 0x0330) UART Activate(RW) */ + uint8_t RSVDB[0x3F0u - 0x331u]; + __IOM uint8_t CFG_SEL; /*!< (@ 0x03F0) UART Configuration Select(RW) */ +} UART_Type; + +/** @brief EMI Registers (EMI) + * !< (@ 0x0000) OS space Host to EC mailbox register + * !< (@ 0x0001) OS space EC to Host mailbox register + * !< (@ 0x0002) OS space EC memory address LSB register + * !< (@ 0x0003) OS space EC memory address LSB register + * !< (@ 0x0004) OS space EC Data register + * !< (@ 0x0008) OS space Interrupt Source LSB register + * !< (@ 0x0009) OS space Interrupt Source MSB register + * !< (@ 0x000A) OS space Interrupt Mask LSB register + * !< (@ 0x000B) OS space Interrupt Mask MSB register + * !< (@ 0x000C) OS space Application ID register + * !< (@ 0x0100) Host to EC mailbox + * !< (@ 0x0101) EC Data + * !< (@ 0x0104) EC memory region 0 base address + * !< (@ 0x0108) EC memory region 0 read/write limits + * !< (@ 0x010C) EC memory region 1 base address + * !< (@ 0x0110) EC memory region 1 read/write limits + * !< (@ 0x0114) Set OS interrupt source + * !< (@ 0x0116) OS interrupt source clear enable + */ +typedef struct emi_regs { + __IOM uint8_t OS_H2E_MBOX; + __IOM uint8_t OS_E2H_MBOX; + __IOM uint8_t OS_EC_ADDR_LSB; + __IOM uint8_t OS_EC_ADDR_MSB; + __IOM uint32_t OS_EC_DATA; + __IOM uint8_t OS_INT_SRC_LSB; + __IOM uint8_t OS_INT_SRC_MSB; + __IOM uint8_t OS_INT_MASK_LSB; + __IOM uint8_t OS_INT_MASK_MSB; + __IOM uint32_t OS_APP_ID; + uint8_t RSVD1[0x100u - 0x10u]; + __IOM uint8_t H2E_MBOX; + __IOM uint8_t E2H_MBOX; + uint8_t RSVD2[2]; + __IOM uint32_t MEM_BASE_0; + __IOM uint32_t MEM_LIMIT_0; + __IOM uint32_t MEM_BASE_1; + __IOM uint32_t MEM_LIMIT_1; + __IOM uint16_t EC_OS_INT_SET; + __IOM uint16_t EC_OS_INT_CLR_EN; +} EMI_Type; + +/** @brief BIOS Debug Port 80h and Alias port capture registers. + * HDATA !< (@ 0x0000) Host Data b[7:0] write-only + * EC_DA !< (@ 0x0100) P80BD EC-only Data/attributes b[15:0] + * CONFIG !< (@ 0x0104) P80BD EC-only configuration + * STS_IEN !< (@ 0x0108) P80BD EC-only status + * SNAPSHOT !< (@ 0x010C) P80BD EC-only snapshot + * CAPTURE !< (@ 0x0110) P80BD EC-only current value of 4-byte capture + * ACTV !< (@ 0x0330) P80BD logical device Activate + * ALIAS_HDATA !< (@ 0x0400) P80BD Alias Port Host Data + * ALIAS_ACTV !< (@ 0x0730) P80BD Alias Port Activate + * ALIAS_BLS !< (@ 0x0730) P80BD Alias Byte Lane Select + */ +typedef struct p80bd_regs { + __OM uint32_t HDATA; + uint8_t RSVD1[0x100u - 0x04u]; + __IM uint32_t EC_DA; + __IOM uint32_t CONFIG; + __IOM uint32_t STS_IEN; + __IM uint32_t SNAPSHOT; + __IM uint32_t CAPTURE; + uint8_t RSVD2[0x330ul - 0x114ul]; + __IOM uint32_t ACTV; + uint8_t RSVD3[0x400ul - 0x334ul]; + __IOM uint8_t ALIAS_HDATA; + uint8_t RSVD4[0x730ul - 0x401ul]; + __IOM uint32_t ALIAS_ACTV; + uint8_t RSVD5[0x7F0ul - 0x734ul]; + __IOM uint32_t ALIAS_BLS; +} P80BD_Type; + +/* --------------- eSPI End Point Devices ----------------- */ + +/** + * @brief ESPI Host interface IO Component (MCHP_ESPI_IO) @ 0x400f36b0 + * ESPI_IO_CAP - eSPI IO capabilities, channel ready, activate, + * VW_EN_STS (@ 0x0000) Virtual Wire Enable Status + * CAP_ID (@ 0x0030) Capabilities ID + * GLB_CAP0 (@ 0x0031) Global Capabilities 0 + * GLB_CAP1 (@ 0x0032) Global Capabilities 1 + * PC_CAP (@ 0x0033) Periph Chan Capabilities + * VW_CAP (@ 0x0034) Virtual Wire Chan Capabilities + * OOB_CAP (@ 0x0035) OOB Chan Capabilities + * FC_CAP (@ 0x0036) Flash Chan Capabilities + * PC_RDY (@ 0x0037) PC ready + * OOB_RDY (@ 0x0038) OOB ready + * FC_RDY (@ 0x0039) OOB ready + * ERST_STS (@ 0x003A) eSPI Reset interrupt status + * ERST_IEN (@ 0x003B) eSPI Reset interrupt enable + * PLTRST_SRC (@ 0x003C) Platform Reset Source + * VW_RDY (@ 0x003D) VW ready + * FC_SERBZ (@ 0x003E) S-Erase Block Size + * VW_ERR_STS (@ 0x0140) IO Virtual Wire Error + */ +typedef struct espi_io_cap_regs { + __IOM uint32_t VW_EN_STS; + uint8_t RSVD1[0x36E0 - 0x36B4]; + __IOM uint8_t CAP_ID; + __IOM uint8_t GLB_CAP0; + __IOM uint8_t GLB_CAP1; + __IOM uint8_t PC_CAP; + __IOM uint8_t VW_CAP; + __IOM uint8_t OOB_CAP; + __IOM uint8_t FC_CAP; + __IOM uint8_t PC_RDY; + __IOM uint8_t OOB_RDY; + __IOM uint8_t FC_RDY; + __IOM uint8_t ERST_STS; + __IOM uint8_t ERST_IEN; + __IOM uint8_t PLTRST_SRC; + __IOM uint8_t VW_RDY; + __IOM uint8_t FC_SERBZ; + uint8_t RSVD2[0x37F0u - 0x36EE]; + __IOM uint32_t VW_ERR_STS; +} ESPI_IO_CAP_Type; + +/** @brief eSPI IO Component Peripheral Channel (PC) register structure + * PC registers at 0x400f3500. + * PC_LC_ADDR_LSW (@ 0x000) Last Cycle address bits[31:0] + * PC_LC_ADDR_MSW (@ 0x004) Last Cycle address bits[63:32] + * PC_LEN_TYPE_TAG (@ 0x008) Last Cycle length, type, and tag + * PC_ERR_ADDR_LSW (@ 0x00c) Address bits[31:0] causing an error + * PC_ERR_ADDR_MSW (@ 0x010) Address bits[63:32] causing an error + * PC_STATUS (@ 0x014) Peripheral channel status (RW/1C and RO) + * PC_IEN (@ 0x018) Peripheral channel interrupt enable + */ +typedef struct espi_io_pc_regs { + __IOM uint32_t PC_LC_ADDR_LSW; + __IOM uint32_t PC_LC_ADDR_MSW; + __IOM uint32_t PC_LC_LEN_TYPE_TAG; + __IOM uint32_t PC_ERR_ADDR_LSW; + __IOM uint32_t PC_ERR_ADDR_MSW; + __IOM uint32_t PC_STATUS; + __IOM uint32_t PC_IEN; +} ESPI_IO_PC_Type; + +/** @brief eSPIO IO Component LTR registers @ 0x400f3620 + * LTR_STS (@ 0x000) LTR peripheral ptatus + * LTR_IEN (@ 0x004) LTR peripheral interrupt enable + * LTR_CTRL (@ 0x008) LTR peripheral control + * LTR_MSG (@ 0x00c) LTR peripheral message + */ +typedef struct espi_io_ltr_regs { + __IOM uint32_t LTR_STS; + __IOM uint32_t LTR_IEN; + __IOM uint32_t LTR_CTRL; + __IOM uint32_t LTR_MSG; +} ESPI_IO_LTR_Type; + +/** @brief eSPI IO Component OOB registers @ 0x400F3640 + * RX_ADDR_LSW (@ 0x0000) OOB Receive Address bits[31:0] + * RX_ADDR_MSW (@ 0x0004) OOB Receive Address bits[63:32] + * TX_ADDR_LSW (@ 0x0008) OOB Transmit Address bits[31:0] + * TX_ADDR_MSW (@ 0x000C) OOB Transmit Address bits[63:32] + * RX_LEN (@ 0x0010) OOB Receive length + * TX_LEN (@ 0x0014) OOB Transmit length + * RX_CTRL (@ 0x0018) OOB Receive control + * RX_IEN (@ 0x001C) OOB Receive interrupt enable + * RX_STS (@ 0x0020) OOB Receive interrupt status + * TX_CTRL (@ 0x0024) OOB Transmit control + * TX_IEN (@ 0x0028) OOB Transmit interrupt enable + * TX_STS (@ 0x002C) OOB Transmit interrupt status + */ +typedef struct espi_io_oob_regs { + __IOM uint32_t RX_ADDR_LSW; + __IOM uint32_t RX_ADDR_MSW; + __IOM uint32_t TX_ADDR_LSW; + __IOM uint32_t TX_ADDR_MSW; + __IOM uint32_t RX_LEN; + __IOM uint32_t TX_LEN; + __IOM uint32_t RX_CTRL; + __IOM uint32_t RX_IEN; + __IOM uint32_t RX_STS; + __IOM uint32_t TX_CTRL; + __IOM uint32_t TX_IEN; + __IOM uint32_t TX_STS; +} ESPI_IO_OOB_Type; + +/** @brief eSPI IO Flash Channel registers @ 0x40003680 + * FL_ADDR_LSW (@ 0x0000) FC flash address bits[31:0] + * FL_ADDR_MSW (@ 0x0004) FC flash address bits[63:32] + * MEM_ADDR_LSW (@ 0x0008) FC EC Memory address bits[31:0] + * MEM_ADDR_MSW (@ 0x000C) FC EC Memory address bits[63:32] + * XFR_LEN (@ 0x0010) FC transfer length + * CTRL (@ 0x0014) FC Control + * IEN (@ 0x0018) FC interrupt enable + * CFG (@ 0x001C) FC configuration + * STS (@ 0x0020) FC status + */ +typedef struct espi_io_fc_regs { + __IOM uint32_t FL_ADDR_LSW; + __IOM uint32_t FL_ADDR_MSW; + __IOM uint32_t MEM_ADDR_LSW; + __IOM uint32_t MEM_ADDR_MSW; + __IOM uint32_t XFR_LEN; + __IOM uint32_t CTRL; + __IOM uint32_t IEN; + __IOM uint32_t CFG; + __IOM uint32_t STS; +} ESPI_IO_FC_Type; + +/** @brief eSPI IO component registers related to VW channel @ 0x400F36B0 */ +typedef struct { + __IOM uint32_t VW_EN_STS; /*! (@ 0x0000) Virtual Wire Enable Status */ + uint32_t RSVD1[12]; + __IOM uint8_t VW_CAP; /*! (@ 0x0034) Virtual Wire Chan Capabilities */ + uint8_t RSVD2[8]; + __IOM uint8_t VW_RDY; /*! (@ 0x003D) VW ready */ + uint8_t RSVD3[0x102]; + __IOM uint32_t VW_ERR_STS; /*! (@ 0x0140) IO Virtual Wire Error */ +} ESPI_IO_VW_Type; + +/** @brief eSPI IO BAR Host registers at 0x400f3520 + * These registers contain the Host side IO address for each peripheral. + * IOBAR_INH_LSW (@ 0x0000) BAR Inhibit LSW + * IOBAR_INH_MSW (@ 0x0004) BAR Inhibit MSW + * IOBAR_INIT (@ 0x0008) BAR Init + * EC_IRQ (@ 0x000C) EC IRQ + * IOBAR (@ 0x0014) Host IO Component BAR array, index is enum epio_io_bar_idx + */ +typedef struct espi_io_bar_host_regs { + __IOM uint32_t IOBAR_INH_LSW; + __IOM uint32_t IOBAR_INH_MSW; + __IOM uint32_t IOBAR_INIT; + __IOM uint32_t EC_IRQ; + uint32_t RSVD1[1]; + __IOM uint32_t IOBAR[23]; +} ESPI_IO_BAR_HOST_Type; + +/** @brief ESPI_IO_BAR_EC - eSPI IO EC-only component of IO BAR @ 0x400F3730 + * All fields are Read-Only + * Address mask in bits[7:0] + * Logical device number in bits[13:8] + * IO_ACTV (@ 0x0000) ESPI IO Component Activate + * IOBAR (@ 0x0004) IO Component BAR, index is enum espi_io_bar_idx + */ +typedef struct espi_io_bar_ec_ar_regs { + __IOM uint32_t IO_ACTV; + __IOM uint32_t IOBAR[23]; +} ESPI_IO_BAR_EC_AR_Type; + +/** @brief ESPI_IO_BAR_EC - eSPI IO EC-only component of IO BAR @ 0x400F3730 + * use named registers + */ +typedef struct espi_io_bar_ec_regs { + __IOM uint32_t IO_ACTV; /*!< (0x0000) eSPI IO component activate */ + __IOM uint32_t EC_BAR_IOC; /*!< (0x0004) IO component BAR */ + __IOM uint32_t EC_BAR_MEM; /*!< (0x0008) IO component MEM BAR */ + __IOM uint32_t EC_BAR_MBOX; /*!< (0x000C) IO Mailbox BAR */ + __IOM uint32_t EC_BAR_KBC; /*!< (0x0010) IO 8042 KBC BAR */ + __IOM uint32_t EC_BAR_ACPI_EC_0; /*!< (0x0014) ACPI EC 0 BAR */ + __IOM uint32_t EC_BAR_ACPI_EC_1; /*!< (0x0018) ACPI EC 1 BAR */ + __IOM uint32_t EC_BAR_ACPI_EC_2; /*!< (0x001C) ACPI EC 2 BAR */ + __IOM uint32_t EC_BAR_ACPI_EC_3; /*!< (0x0020) ACPI EC 3 BAR */ + __IOM uint32_t EC_BAR_ACPI_EC_4; /*!< (0x0024) ACPI EC 4 BAR */ + __IOM uint32_t EC_BAR_ACPI_PM1; /*!< (0x0028) ACPI PM1 BAR */ + __IOM uint32_t EC_BAR_PORT92; /*!< (0x002C) Legacy Port92 BAR */ + __IOM uint32_t EC_BAR_UART_0; /*!< (0x0030) UART 0 BAR */ + __IOM uint32_t EC_BAR_UART_1; /*!< (0x0034) UART 1 BAR */ + __IOM uint32_t EC_BAR_EMI_0; /*!< (0x0038) EMI 0 BAR */ + __IOM uint32_t EC_BAR_EMI_1; /*!< (0x003C) EMI 0 BAR */ + __IOM uint32_t EC_BAR_EMI_2; /*!< (0x0040) EMI 0 BAR */ + __IOM uint32_t EC_BAR_P80CAP_0; /*!< (0x0044) BDP Port 80 BAR */ + __IOM uint32_t EC_BAR_P80CAP_1; /*!< (0x0048) BDP Alias Port BAR */ + __IOM uint32_t EC_BAR_RTC; /*!< (0x004C) RTC BAR */ + uint32_t RSVD1[1]; + __IOM uint32_t EC_BAR_T32B; /*!< (0x0054) T32B BAR */ + uint32_t RSVD2[1]; + __IOM uint32_t EC_BAR_GLUE_LOG; /*!< (0x005C) Glue Logic BAR */ +} ESPI_IO_BAR_EC_Type; + +/** @brief eSPI IO Component Logical Device Serial IRQ config @ 0x400F37A0 + * SIRQ index with enum espi_io_sirq_idx + */ +typedef struct espi_io_sirq_ar_regs { + uint8_t RSVD1[12]; + uint8_t SIRQ[20]; +} ESPI_IO_SIRQ_AR_Type; + +typedef struct espi_io_sirq_regs { + uint8_t RSVD1[12]; + __IOM uint8_t MBOX_SIRQ_0; + __IOM uint8_t MBOX_SIRQ_1; + __IOM uint8_t KBC_SIRQ_0; + __IOM uint8_t KBC_SIRQ_1; + __IOM uint8_t ACPI_EC_0_SIRQ; + __IOM uint8_t ACPI_EC_1_SIRQ; + __IOM uint8_t ACPI_EC_2_SIRQ; + __IOM uint8_t ACPI_EC_3_SIRQ; + __IOM uint8_t ACPI_EC_4_SIRQ; + __IOM uint8_t UART_0_SIRQ; + __IOM uint8_t UART_1_SIRQ; + __IOM uint8_t EMI_0_SIRQ_0; + __IOM uint8_t EMI_0_SIRQ_1; + __IOM uint8_t EMI_1_SIRQ_0; + __IOM uint8_t EMI_1_SIRQ_1; + __IOM uint8_t EMI_2_SIRQ_0; + __IOM uint8_t EMI_2_SIRQ_1; + __IOM uint8_t RTC_SIRQ; + __IOM uint8_t EC_SIRQ; + uint8_t RSVD2[1]; +} ESPI_IO_SIRQ_Type; + +/** @brief eSPI Memory Component Bus Master registers @ 0x400F3A00 + * BM_STS (@ 0x0000) Bus Master Status + * BM_IEN (@ 0x0004) Bus Master interrupt enable + * BM_CFG (@ 0x0008) Bus Master configuration + * BM1_CTRL (@ 0x0010) Bus Master 1 control + * BM1_HOST_ADDR_LSW (@ 0x0014) Bus Master 1 host address bits[31:0] + * BM1_HOST_ADDR_MSW (@ 0x0018) Bus Master 1 host address bits[63:32] + * BM1_EC_ADDR_LSW (@ 0x001C) Bus Master 1 EC address bits[31:0] + * BM1_EC_ADDR_MSW (@ 0x0020) Bus Master 1 EC address bits[63:32] + * BM2_CTRL (@ 0x0024) Bus Master 2 control + * BM2_HOST_ADDR_LSW (@ 0x0028) Bus Master 2 host address bits[31:0] + * BM2_HOST_ADDR_MSW (@ 0x002C) Bus Master 2 host address bits[63:32] + * BM2_EC_ADDR_LSW (@ 0x0030) Bus Master 2 EC address bits[31:0] + * BM2_EC_ADDR_MSW (@ 0x0034) Bus Master 2 EC address bits[63:32] + */ +typedef struct espi_mem_bm_regs { + __IOM uint32_t BM_STS; + __IOM uint32_t BM_IEN; + __IOM uint32_t BM_CFG; + uint8_t RSVD1[4]; + __IOM uint32_t BM1_CTRL; + __IOM uint32_t BM1_HOST_ADDR_LSW; + __IOM uint32_t BM1_HOST_ADDR_MSW; + __IOM uint32_t BM1_EC_ADDR_LSW; + __IOM uint32_t BM1_EC_ADDR_MSW; + __IOM uint32_t BM2_CTRL; + __IOM uint32_t BM2_HOST_ADDR_LSW; + __IOM uint32_t BM2_HOST_ADDR_MSW; + __IOM uint32_t BM2_EC_ADDR_LSW; + __IOM uint32_t BM2_EC_ADDR_MSW; +} ESPI_MEM_BM_Type; + +/** @brief eSPI Memory Component Memory BAR EC-only registers @ 0x400F3930 */ +typedef struct espi_mem_bar_ec_regs { + __IOM uint16_t EMBAR[9 * 5]; +} ESPI_MEM_BAR_EC_Type; + +/** @brief eSPI Memory Component Memory BAR Host registers @ 0x400F3B30 */ +typedef struct espi_mem_bar_host_regs { + __IOM uint16_t HMBAR[9 * 5]; +} ESPI_MEM_BAR_HOST_Type; + +/* eSPI Memory Component SRAM 0 and 1 EC BAR's @ 0x400F39A0 */ +typedef struct espi_mem_sram_bar_ec_regs { + uint32_t RSVD1[3]; + __IOM uint16_t ESMB[2 * 5]; +} ESPI_MEM_SRAM_BAR_EC_Type; + +/* eSPI Memory Component SRAM 0 and 1 Host BAR's @ 0x400F3BA0 */ +typedef struct espi_mem_sram_bar_host_regs { + uint32_t RSVD1[3]; + __IOM uint16_t HSMB[2 * 5]; +} ESPI_MEM_SRAM_BAR_HOST_Type; + +/** @brief eSPI 96-bit Master-to-Slave Virtual Wire register */ +typedef struct espi_msvw_reg { + __IOM uint8_t INDEX; + __IOM uint8_t MTOS; + uint8_t RSVD1[2]; + __IOM uint32_t SRC_IRQ_SEL; + __IOM uint32_t SRC; +} ESPI_MSVW_REG; + +/** @brief HW implements 11 Master-to-Slave VW registers as an array */ +typedef struct { + ESPI_MSVW_REG MSVW[11]; +} ESPI_M2S_VW_AR_Type; + +/** @brief HW implements 11 Master-to-Slave VW registers as named registers */ +typedef struct { + ESPI_MSVW_REG MSVW00; + ESPI_MSVW_REG MSVW01; + ESPI_MSVW_REG MSVW02; + ESPI_MSVW_REG MSVW03; + ESPI_MSVW_REG MSVW04; + ESPI_MSVW_REG MSVW05; + ESPI_MSVW_REG MSVW06; + ESPI_MSVW_REG MSVW07; + ESPI_MSVW_REG MSVW08; + ESPI_MSVW_REG MSVW09; + ESPI_MSVW_REG MSVW10; +} ESPI_M2S_VW_Type; + +/** @brief eSPI M2S VW registers as an array of words at 0x400F9C00 */ +typedef struct { + __IOM uint32_t MSVW32[11 * 3]; +} ESPI_M2S_VW32_Type; + +/** @brief eSPI 64-bit Slave-to-Master Virtual Wire register */ +typedef struct espi_smvw_reg { + __IOM uint8_t INDEX; + __IOM uint8_t STOM; + __IM uint8_t SRC_CHG; + uint8_t RSVD1[1]; + __IOM uint32_t SRC; +} ESPI_SMVW_REG; + +/** @brief HW implements 11 Slave-to-Master VW registers as an array */ +typedef struct { + ESPI_SMVW_REG SMVW[11]; +} ESPI_S2M_VW_AR_Type; + +/** @brief HW implements 11 Slave-to-Master VW registers as named registers */ +typedef struct { + ESPI_SMVW_REG SMVW00; + ESPI_SMVW_REG SMVW01; + ESPI_SMVW_REG SMVW02; + ESPI_SMVW_REG SMVW03; + ESPI_SMVW_REG SMVW04; + ESPI_SMVW_REG SMVW05; + ESPI_SMVW_REG SMVW06; + ESPI_SMVW_REG SMVW07; + ESPI_SMVW_REG SMVW08; + ESPI_SMVW_REG SMVW09; + ESPI_SMVW_REG SMVW10; +} ESPI_S2M_VW_Type; + +/** @brief eSPI S2M VW registers as an array of words at 0x400F9E00 */ +typedef struct { + __IOM uint32_t SMVW[11 * 2]; +} ESPI_S2M_VW32_Type; + +/** @brief SAF SPI Opcoded and indices specifying start QMSPI descriptor for + * each opcode. There is one register group per flash device. + * OPA: read status1, resume, suspend, write enable + * OPB: erase 4KB, erase 32KB, erase 64KB, page program + * OPC: Fast Read Quad or Dual, N/A, continuous mode byte, read status 2 + * OP_DESCR: contains QMSPI descriptor indices for various opcode fields. + */ +struct mchp_espi_saf_op { + __IOM uint32_t OPA; + __IOM uint32_t OPB; + __IOM uint32_t OPC; + __IOM uint32_t OP_DESCR; +}; + +/** @brief SAF protection regions contain 4 32-bit registers. + * Start address in 4KB units. + * Limit address in 4KB units. + * Write-erase eSPI Master bit-map. + * Read access eSPI Master bit-map. + */ +struct mchp_espi_saf_pr { + __IOM uint32_t START; + __IOM uint32_t LIMIT; + __IOM uint32_t WEBM; + __IOM uint32_t RDBM; +}; + +/** @brief eSPI SAF configuration and control registers at 0x40008000 */ +typedef struct mchp_espi_saf { + uint32_t RSVD1[6]; + __IOM uint32_t SAF_ECP_CMD; + __IOM uint32_t SAF_ECP_FLAR; + __IOM uint32_t SAF_ECP_START; + __IOM uint32_t SAF_ECP_BFAR; + __IOM uint32_t SAF_ECP_STATUS; + __IOM uint32_t SAF_ECP_INTEN; + __IOM uint32_t SAF_FL_CFG_SIZE_LIM; + __IOM uint32_t SAF_FL_CFG_THRH; + __IOM uint32_t SAF_FL_CFG_MISC; + __IOM uint32_t SAF_ESPI_MON_STATUS; + __IOM uint32_t SAF_ESPI_MON_INTEN; + __IOM uint32_t SAF_ECP_BUSY; + uint32_t RSVD2[1]; + struct mchp_espi_saf_op SAF_CS_OP[2]; + __IOM uint32_t SAF_FL_CFG_GEN_DESCR; + __IOM uint32_t SAF_PROT_LOCK; + __IOM uint32_t SAF_PROT_DIRTY; + __IOM uint32_t SAF_TAG_MAP[3]; + struct mchp_espi_saf_pr SAF_PROT_RG[17]; + __IOM uint32_t SAF_POLL_TMOUT; + __IOM uint32_t SAF_POLL_INTRVL; + __IOM uint32_t SAF_SUS_RSM_INTRVL; + __IOM uint32_t SAF_CONSEC_RD_TMOUT; + __IOM uint16_t SAF_CS0_CFG_P2M; + __IOM uint16_t SAF_CS1_CFG_P2M; + __IOM uint32_t SAF_FL_CFG_SPM; + __IOM uint32_t SAF_SUS_CHK_DLY; + __IOM uint16_t SAF_CS0_CM_PRF; + __IOM uint16_t SAF_CS1_CM_PRF; + __IOM uint32_t SAF_DNX_PROT_BYP; +} MCHP_SAF_HW_REGS; + +/** @} */ /* End of group MEC172x_Peripheral_peripherals */ + +/* ==== End of section using anonymous unions ========================== */ +#if defined(__CC_ARM) +#pragma pop +#elif defined(__ICCARM__) +/* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) +#pragma warning restore +#elif defined(__CSMC__) +/* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif + +/* =========================================================================*/ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================*/ + +/** @addtogroup MEC172x_Peripheral_peripheralAddr + * @{ + */ + +/* Peripheral and SRAM base address */ +#define CODE_SRAM_BASE 0x000C0000UL /*!< (CODE SRAM ) Base Address */ +#define DATA_SRAM_BASE 0x00118000UL /*!< (DATA SRAM ) Base Address */ +#define DATA_SRAM_SIZE 0x10000UL /*!< (DATA SRAM Size ) 64KB */ +#define PERIPH_BASE 0x40000000UL /*!< (Peripheral) Base Address */ + +/* Peripheral memory map */ +#define WDT_BASE (PERIPH_BASE + 0x0400ul) /*!< (WDT0 ) Base Address */ +#define BTMR16_0_BASE (PERIPH_BASE + 0x0C00ul) /*!< (B16TMR 0 ) Base Address */ +#define BTMR16_1_BASE (PERIPH_BASE + 0x0C20ul) /*!< (B16TMR 1 ) Base Address */ +#define BTMR16_2_BASE (PERIPH_BASE + 0x0C40ul) /*!< (B16TMR 0 ) Base Address */ +#define BTMR16_3_BASE (PERIPH_BASE + 0x0C60ul) /*!< (B16TMR 1 ) Base Address */ +#define BTMR32_0_BASE (PERIPH_BASE + 0x0C80ul) /*!< (B32TMR 0 ) Base Address */ +#define BTMR32_1_BASE (PERIPH_BASE + 0x0CA0ul) /*!< (B32TMR 1 ) Base Address */ + +#define BTMR16_BASE(n) (BTMR16_0_BASE + ((uint32_t)(n) * 0x20ul)) +#define BTMR32_BASE(n) (BTMR32_0_BASE + ((uint32_t)(n) * 0x20ul)) + +#define CTMR_BASE(n) \ + (PERIPH_BASE + 0x0D00ul + ((n) * 0x20u)) /*! (CTRM n) Base Address */ + +#define CCT_0_BASE (PERIPH_BASE + 0x1000ul) /*!< (CCT 0 ) Base Address */ + +#define RCID_BASE(n) \ + (PERIPH_BASE + 0x1400ul + \ + ((uint32_t)(n) * 0x80)) /*! <(RCID n) Base Address */ + +#define DMA_BASE (PERIPH_BASE + 0x2400ul) /*!< (DMA ) Base Address */ +#define DMA_CHAN_BASE(n) (DMA_BASE + (((n) + 1) * 40UL)) +#define DMA_CH0_BASE (DMA_BASE + 0x0040ul) /*!< (DMA Chan 00 ) Base Address */ +#define DMA_CH1_BASE (DMA_BASE + 0x0080ul) /*!< (DMA Chan 01 ) Base Address */ +#define DMA_CH2_BASE (DMA_BASE + 0x00C0ul) /*!< (DMA Chan 02 ) Base Address */ +#define DMA_CH3_BASE (DMA_BASE + 0x0100ul) /*!< (DMA Chan 03 ) Base Address */ +#define DMA_CH4_BASE (DMA_BASE + 0x0140ul) /*!< (DMA Chan 04 ) Base Address */ +#define DMA_CH5_BASE (DMA_BASE + 0x0180ul) /*!< (DMA Chan 05 ) Base Address */ +#define DMA_CH6_BASE (DMA_BASE + 0x01C0ul) /*!< (DMA Chan 06 ) Base Address */ +#define DMA_CH7_BASE (DMA_BASE + 0x0200ul) /*!< (DMA Chan 07 ) Base Address */ +#define DMA_CH8_BASE (DMA_BASE + 0x0240ul) /*!< (DMA Chan 08 ) Base Address */ +#define DMA_CH9_BASE (DMA_BASE + 0x0280ul) /*!< (DMA Chan 09 ) Base Address */ +#define DMA_CH10_BASE (DMA_BASE + 0x02C0ul) /*!< (DMA Chan 10 ) Base Address */ +#define DMA_CH11_BASE (DMA_BASE + 0x0300ul) /*!< (DMA Chan 11 ) Base Address */ +#define DMA_CH12_BASE (DMA_BASE + 0x0340ul) /*!< (DMA Chan 12 ) Base Address */ +#define DMA_CH13_BASE (DMA_BASE + 0x0380ul) /*!< (DMA Chan 13 ) Base Address */ +#define DMA_CH14_BASE (DMA_BASE + 0x03C0ul) /*!< (DMA Chan 14 ) Base Address */ +#define DMA_CH15_BASE (DMA_BASE + 0x0400ul) /*!< (DMA Chan 15 ) Base Address */ + +#define EEPROMC_BASE \ + (PERIPH_BASE + 0x2C00ul) /*!< (EEPROMC ) Base Address */ + +#define PROCHOT_BASE (PERIPH_BASE + 0x3400ul) /*!< (PROCHOT ) Base Address */ + +#define I2C_SMB_BASE(n) (PERIPH_BASE + 0x4000ul + ((n) * 0x400UL)) +#define I2C_SMB_0_BASE (PERIPH_BASE + 0x4000ul) /*!< (I2C_SMB 0) Base Address */ +#define I2C_SMB_1_BASE (PERIPH_BASE + 0x4400ul) /*!< (I2C_SMB 1) Base Address */ +#define I2C_SMB_2_BASE (PERIPH_BASE + 0x4800ul) /*!< (I2C_SMB 2) Base Address */ +#define I2C_SMB_3_BASE (PERIPH_BASE + 0x4C00ul) /*!< (I2C_SMB 3) Base Address */ +#define I2C_SMB_4_BASE (PERIPH_BASE + 0x5000ul) /*!< (I2C_SMB 4) Base Address */ + +#define PWM_BASE(n) (PERIPH_BASE + 0x5800ul + ((n) * 0x10UL)) +#define PWM_0_BASE (PERIPH_BASE + 0x5800ul) /*!< (PWM 0) Base Address */ +#define PWM_1_BASE (PERIPH_BASE + 0x5810ul) /*!< (PWM 1) Base Address */ +#define PWM_2_BASE (PERIPH_BASE + 0x5820ul) /*!< (PWM 2) Base Address */ +#define PWM_3_BASE (PERIPH_BASE + 0x5830ul) /*!< (PWM 3) Base Address */ +#define PWM_4_BASE (PERIPH_BASE + 0x5840ul) /*!< (PWM 4) Base Address */ +#define PWM_5_BASE (PERIPH_BASE + 0x5850ul) /*!< (PWM 5) Base Address */ +#define PWM_6_BASE (PERIPH_BASE + 0x5860ul) /*!< (PWM 6) Base Address */ +#define PWM_7_BASE (PERIPH_BASE + 0x5870ul) /*!< (PWM 7) Base Address */ +#define PWM_8_BASE (PERIPH_BASE + 0x5880ul) /*!< (PWM 8) Base Address */ + +#define TACH_BASE(n) (PERIPH_BASE + 0x6000ul + ((n) * 0x10UL)) +#define TACH_0_BASE (PERIPH_BASE + 0x6000ul) /*!< (TACH 0) Base Address */ +#define TACH_1_BASE (PERIPH_BASE + 0x6010ul) /*!< (TACH 1) Base Address */ +#define TACH_2_BASE (PERIPH_BASE + 0x6020ul) /*!< (TACH 2) Base Address */ +#define TACH_3_BASE (PERIPH_BASE + 0x6030ul) /*!< (TACH 3) Base Address */ + +#define PECI_0_BASE (PERIPH_BASE + 0x6400ul) /*!< (PECI 0) Base Address */ + +#define SPIP_0_BASE (PERIPH_BASE + 0x7000ul) /*!< (SPIP 0) Base Address */ + +#define RTMR_0_BASE (PERIPH_BASE + 0x7400ul) /*!< (RTMR 0) Base Address */ + +#define ADC_0_BASE (PERIPH_BASE + 0x7C00ul) /*!< (ADC 0) Base Address */ + +#define ESPI_SAF_BASE (PERIPH_BASE + 0x8000ul) /*!< (ESPI_SAF) Base Address */ + +#define TFDP_0_BASE (PERIPH_BASE + 0x8C00ul) /*!< (TFDP 0) Base Address */ + +#define PS2_0_BASE (PERIPH_BASE + 0x9000ul) /*!< (PS2 0) Base Address */ + +#define GPSPI_0_BASE (PERIPH_BASE + 0x9400ul) /*!< (GPSPI 0) Base Addresss */ +#define GPSPI_1_BASE (PERIPH_BASE + 0x9480ul) /*!< (GPSPI 1) Base Addresss */ + +#define HTMR_0_BASE (PERIPH_BASE + 0x9800ul) /*!< (HTMR 0) Base Address */ +#define HTMR_1_BASE (PERIPH_BASE + 0x9820ul) /*!< (HTMR 1) Base Address */ + +#define KEYSCAN_BASE (PERIPH_BASE + 0x9C00ul) /*!< (KEYSCAN ) Base Address */ + +#define RPMFAN_0_BASE (PERIPH_BASE + 0xA000ul) /*!< (RPMFAN 0) Base Address */ +#define RPMFAN_1_BASE (PERIPH_BASE + 0xA080ul) /*!< (RPMFAN 1) Base Address */ + +#define VBATR_BASE (PERIPH_BASE + 0xA400ul) /*!< (VBATR ) Base Address */ +#define VBATM_BASE (PERIPH_BASE + 0xA800ul) /*!< (VBATM ) Base Address */ +#define WKTMR_BASE (PERIPH_BASE + 0xAC80ul) /*!< (WKTMR ) Base Address */ +#define VCI_BASE (PERIPH_BASE + 0xAE00ul) /*!< (VCI ) Base Address */ + +#define LED_0_BASE (PERIPH_BASE + 0xB800ul) /*!< (LED 0 ) Base Address */ +#define LED_1_BASE (PERIPH_BASE + 0xB900ul) /*!< (LED 1 ) Base Address */ +#define LED_2_BASE (PERIPH_BASE + 0xBA00ul) /*!< (LED 2 ) Base Address */ +#define LED_3_BASE (PERIPH_BASE + 0xBB00ul) /*!< (LED 3 ) Base Address */ + +#define BCL_0_BASE (PERIPH_BASE + 0xCD00ul) /*!< (BCL 0 ) Base Address */ + +#define ECIA_BASE (PERIPH_BASE + 0xE000ul) /*!< (ECIA ) Base Address */ + +/*!< (GIRQ 8<=n<=26) address */ +#define GIRQ_BASE(n) (ECIA_BASE + (((n) - 8U) * 0x14ul)) + +#define ECS_BASE (PERIPH_BASE + 0xFC00ul) /*!< (ECS ) Base Address */ + +/*!< (CACHE_CTRL ) Base Address */ +#define CACHE_CTRL_BASE (PERIPH_BASE + 0x10000ul) + +#define QMSPI_0_BASE (PERIPH_BASE + 0x70000ul) /*!< (QMSPI 0) Base Address */ + +#define PCR_BASE (PERIPH_BASE + 0x80100ul) /*!< (PCR ) Base Address */ + +#define GPIO_BASE (PERIPH_BASE + 0x81000ul) /*!< (GPIO ) Base Address */ +#define GPIO_CTRL_BASE (GPIO_BASE) /*!< (GPIO ) Control Base Address */ + +/*!< (GPIO Parallel I/O) Base Address */ +#define GPIO_PARIN_BASE (GPIO_BASE + 0x0300ul) +/*!< (GPIO Parallel I/O) Base Address */ +#define GPIO_PAROUT_BASE (GPIO_BASE + 0x0380ul) +/*!< (GPIO Lock) Base Address */ +#define GPIO_LOCK_BASE (GPIO_BASE + 0x03E8ul) +/*!< (GPIO ) Control2 Base Address */ +#define GPIO_CTRL2_BASE (GPIO_BASE + 0x0500ul) + +#define OTP_BASE (PERIPH_BASE + 0x82000ul) /*!< (OTP ) Base Address */ + +/* -------- Host Peripheral Base Addresses -------- */ +#define MBOX_0_BASE (PERIPH_BASE + 0xF0000ul) /*!< (MBOX 0) Base Address */ +#define KBC_0_BASE (PERIPH_BASE + 0xF0400ul) /*!< (KBC 0) Base Address */ + +/*!< (ACPI EC n ) Base Address 0 <= n <= 4 */ +#define ACPI_EC_BASE(n) (PERIPH_BASE + 0xF0800ul + ((n) * 0x400UL)) +#define ACPI_PM1_BASE (PERIPH_BASE + 0xF1C00ul) /*!< (ACPI PM1 ) Base Address */ + +#define PORT92_BASE (PERIPH_BASE + 0xF2000ul) /*!< (PORT92 ) Base Address */ + +#define UART_BASE(n) (PERIPH_BASE + 0xF2400ul + ((n) * 0x400UL)) +#define UART_0_BASE (PERIPH_BASE + 0xF2400ul) /*!< (UART0 ) Base Address */ +#define UART_1_BASE (PERIPH_BASE + 0xF2800ul) /*!< (UART1 ) Base Address */ + +#define GLUE_BASE (PERIPH_BASE + 0xF3C00ul) /*!< (Glue Logic ) Base Address */ + +#define EMI_0_BASE (PERIPH_BASE + 0xF4000ul) /*!< (EMI 0 ) Base Address */ +#define EMI_1_BASE (PERIPH_BASE + 0xF4400ul) /*!< (EMI 1 ) Base Address */ +#define EMI_2_BASE (PERIPH_BASE + 0xF4800ul) /*!< (EMI 2 ) Base Address */ + +#define RTC_BASE (PERIPH_BASE + 0xF5000ul) /*!< (RTC ) Base Address */ + +#define P80BD_0_BASE (PERIPH_BASE + 0xF8000ul) /*!< (P80BD 0 ) Base Address */ + +#define GCFG_BASE (PERIPH_BASE + 0xFFF00ul) /*!< (GCFG ) Base Address */ + +/* -------- eSPI Base Addresses -------- */ +/*!< (ESPI IO Component) Base Address */ +#define ESPI_IO_BASE (PERIPH_BASE + 0xF3400ul) +/*!< (ESPI IO Peripheral Channel) Base Address */ +#define ESPI_IO_PC_BASE ((ESPI_IO_BASE) +0x100ul) +/*!< (ESPI IO Host IO BAR) Base Address */ +#define ESPI_IO_HOST_BAR_BASE ((ESPI_IO_BASE) +0x120ul) +/*!< (ESPI IO LTR) Base Address */ +#define ESPI_IO_LTR_BASE ((ESPI_IO_BASE) +0x220ul) +/*!< (ESPI IO Out-of-Band Channel) Base Address */ +#define ESPI_IO_OOB_BASE ((ESPI_IO_BASE) +0x240ul) +/*!< (ESPI IO Flash Channel) Base Address */ +#define ESPI_IO_FC_BASE ((ESPI_IO_BASE) +0x280ul) +/*!< (ESPI IO Capabilities) Base Address */ +#define ESPI_IO_CAP_BASE ((ESPI_IO_BASE) +0x2B0ul) +/*!< (ESPI IO EC IO BAR) Base Address */ +#define ESPI_IO_EC_BAR_BASE ((ESPI_IO_BASE) +0x330ul) +/*!< (ESPI IO EC IO VW registers) Base Address */ +#define ESPI_IO_VW_BASE ((ESPI_IO_BASE) +0x2B0ul) +/*!< (ESPI IO Serial IRQ registers) Base Address */ +#define ESPI_IO_SIRQ_BASE ((ESPI_IO_BASE) +0x3A0ul) +/*!< (ESPI Memory Component) Base Address */ +#define ESPI_MEM_BASE (PERIPH_BASE + 0xF3800ul) +/*!< (ESPI Logical Device Memory BAR EC */ +#define ESPI_MEM_EC_BAR_BASE ((ESPI_MEM_BASE) +0x0130ul) +/*!< (ESPI Logical Device Memory BAR Host */ +#define ESPI_MEM_HOST_BAR_BASE ((ESPI_MEM_BASE) +0x0330ul) +/*!< (ESPI Memory SRAM BAR EC */ +#define ESPI_MEM_SRAM_EC_BAR_BASE ((ESPI_MEM_BASE) +0x01A0ul) +/*!< (ESPI Memory SRAM BAR Host */ +#define ESPI_MEM_SRAM_HOST_BAR_BASE ((ESPI_MEM_BASE) +0x03A0ul) +/*!< (ESPI Memory Component Bus Master) Base Address */ +#define ESPI_MEM_BM_BASE ((ESPI_MEM_BASE) +0x0200ul) +/*!< (ESPI VW Component) Base Address */ +#define ESPI_VW_BASE (PERIPH_BASE + 0xF9C00ul) +/*!< (ESPI VW Component Slave-to-Master) Base Address */ +#define ESPI_SMVW_BASE (ESPI_VW_BASE + 0x200ul) + +#define DELAY_US_BASE (0x08000000ul) /*!< (1 us Delay register) Base Address */ + +/** @} */ /* End of group MEC172x_Peripheral_peripheralAddr */ + +/* ARM Cortex-M4 input clock from PLL */ +#define MCHP_EC_CLOCK_INPUT_HZ 96000000U + +#define MCHP_ACMP_INSTANCES 1 +#define MCHP_ACPI_EC_INSTANCES 5 +#define MCHP_ACPI_PM1_INSTANCES 1 +#define MCHP_ADC_INSTANCES 1 +#define MCHP_BCL_INSTANCES 1 +#define MCHP_BTMR16_INSTANCES 4 +#define MCHP_BTMR32_INSTANCES 2 +#define MCHP_CCT_INSTANCES 1 +#define MCHP_CTMR_INSTANCES 4 +#define MCHP_DMA_INSTANCES 1 +#define MCHP_ECIA_INSTANCES 1 +#define MCHP_EMI_INSTANCES 3 +#define MCHP_HTMR_INSTANCES 2 +#define MCHP_I2C_INSTANCES 0 +#define MCHP_I2C_SMB_INSTANCES 5 +#define MCHP_LED_INSTANCES 4 +#define MCHP_MBOX_INSTANCES 1 +#define MCHP_OTP_INSTANCES 1 +#define MCHP_P80BD_INSTANCES 1 +#define MCHP_PECI_INSTANCES 1 +#define MCHP_PROCHOT_INSTANCES 1 +#define MCHP_PS2_INSTANCES 1 +#define MCHP_PWM_INSTANCES 9 +#define MCHP_QMSPI_INSTANCES 1 +#define MCHP_RCID_INSTANCES 3 +#define MCHP_RPMFAN_INSTANCES 2 +#define MCHP_RTC_INSTANCES 1 +#define MCHP_RTMR_INSTANCES 1 +#define MCHP_SPIEP_INSTANCES 1 +#define MCHP_TACH_INSTANCES 4 +#define MCHP_TFDP_INSTANCES 1 +#define MCHP_UART_INSTANCES 2 +#define MCHP_WDT_INSTANCES 1 +#define MCHP_WKTMR_INSTANCES 1 + +#define MCHP_ACMP_CHANNELS 2 +#define MCHP_ADC_CHANNELS 8 +#define MCHP_BGPO_GPIO_PINS 2 +#define MCHP_DMA_CHANNELS 16 +#define MCHP_GIRQS 19 +#define MCHP_GPIO_PINS 123 +#define MCHP_GPIO_PORTS 6 +#define MCHP_GPTP_PORTS 6 +#define MCHP_I2C_SMB_PORTS 15 +#define MCHP_I2C_PORTMAP 0xF7FFul; +#define MCHP_QMSPI_PORTS 3 +#define MCHP_PS2_PORTS 2 +#define MCHP_VCI_IN_PINS 4 +#define MCHP_VCI_OUT_PINS 1 +#define MCHP_VCI_OVRD_IN_PINS 1 + +#include "component/acpi_ec.h" +#include "component/adc.h" +#include "component/bcl.h" +#include "component/dma.h" +#include "component/ecia.h" +#include "component/ecs.h" +#include "component/eepromc.h" +#include "component/emi.h" +#include "component/espi_io.h" +#include "component/espi_mem.h" +#include "component/espi_saf.h" +#include "component/espi_vw.h" +#include "component/global_cfg.h" +#include "component/glue.h" +#include "component/gpio.h" +#include "component/gpspi.h" +#include "component/i2c_smb.h" +#include "component/kbc.h" +#include "component/keyscan.h" +#include "component/led.h" +#include "component/mailbox.h" +#include "component/p80bd.h" +#include "component/pcr.h" +#include "component/peci.h" +#include "component/port92.h" +#include "component/prochot.h" +#include "component/ps2_ctrl.h" +#include "component/pwm.h" +#include "component/qmspi.h" +#include "component/rcid.h" +#include "component/rpmfan.h" +#include "component/rtc.h" +#include "component/spi_periph.h" +#include "component/tach.h" +#include "component/tfdp.h" +#include "component/timer.h" +#include "component/uart.h" +#include "component/vbat.h" +#include "component/wdt.h" + +/* ===================================================================== */ +/* ================ Peripheral declaration ================ */ +/* ===================================================================== */ + +/** @addtogroup MEC172x_Peripheral_declaration + * @{ + */ + +#define WDT_REGS ((WDT_Type *)WDT_BASE) + +#define BTMR16_0_REGS ((BTMR16_Type *)BTMR16_BASE(0)) +#define BTMR16_1_REGS ((BTMR16_Type *)BTMR16_BASE(1)) +#define BTMR16_2_REGS ((BTMR16_Type *)BTMR16_BASE(2)) +#define BTMR16_3_REGS ((BTMR16_Type *)BTMR16_BASE(3)) +#define BTMR32_0_REGS ((BTMR32_Type *)BTMR32_BASE(0)) +#define BTMR32_1_REGS ((BTMR32_Type *)BTMR32_BASE(1)) +/* backwards compatible aliases */ +#define B16TMR0_REGS BTMR16_0_REGS +#define B16TMR1_REGS BTMR16_1_REGS +#define B16TMR2_REGS BTMR16_2_REGS +#define B16TMR3_REGS BTMR16_3_REGS +#define B32TMR0_REGS BTMR32_0_REGS +#define B32TMR1_REGS BTMR32_1_REGS + +#define CTMR_0_REGS ((CTMR_Type *)CTMR_BASE(0)) +#define CTMR_1_REGS ((CTMR_Type *)CTMR_BASE(1)) +#define CTMR_2_REGS ((CTMR_Type *)CTMR_BASE(2)) +#define CTMR_3_REGS ((CTMR_Type *)CTMR_BASE(3)) + +#define CCT_0_REGS ((CCT_Type *)(CCT_0_BASE)) +/* backwards compatible alias */ +#define CCT_REGS CCT_0_REGS + +#define RCID_0_REGS ((RCID_Type *)RCID_BASE(0)) +#define RCID_1_REGS ((RCID_Type *)RCID_BASE(1)) +#define RCID_2_REGS ((RCID_Type *)RCID_BASE(2)) + +/* Complete DMA block */ +#define DMA_REGS ((DMA_Type *)(DMA_BASE)) +/* DMA Main only */ +#define DMAM_REGS ((DMAM_Type *)(DMA_BASE)) +/* Individual DMA channels */ +#define DMA0_REGS ((DMA_CHAN_ALU_Type *)(DMA_CHAN_BASE(0))) +#define DMA1_REGS ((DMA_CHAN_ALU_Type *)(DMA_CHAN_BASE(1))) +#define DMA2_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(2))) +#define DMA3_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(3))) +#define DMA4_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(4))) +#define DMA5_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(5))) +#define DMA6_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(6))) +#define DMA7_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(7))) +#define DMA8_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(8))) +#define DMA9_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(9))) +#define DMA10_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(10))) +#define DMA11_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(11))) +#define DMA12_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(12))) +#define DMA13_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(13))) +#define DMA14_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(14))) +#define DMA15_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(15))) + +#define EEPROMC_REGS ((EEPROMC_Type *)EEPROMC_BASE) +#define PROCHOT_REGS ((PROCHOT_Type *)PROCHOT_BASE) + +#define I2C_SMB_0_REGS ((I2C_SMB_Type *)I2C_SMB_0_BASE) +#define I2C_SMB_1_REGS ((I2C_SMB_Type *)I2C_SMB_1_BASE) +#define I2C_SMB_2_REGS ((I2C_SMB_Type *)I2C_SMB_2_BASE) +#define I2C_SMB_3_REGS ((I2C_SMB_Type *)I2C_SMB_3_BASE) +#define I2C_SMB_4_REGS ((I2C_SMB_Type *)I2C_SMB_4_BASE) + +#define PWM_0_REGS ((PWM_Type *)PWM_0_BASE) +#define PWM_1_REGS ((PWM_Type *)PWM_1_BASE) +#define PWM_2_REGS ((PWM_Type *)PWM_2_BASE) +#define PWM_3_REGS ((PWM_Type *)PWM_3_BASE) +#define PWM_4_REGS ((PWM_Type *)PWM_4_BASE) +#define PWM_5_REGS ((PWM_Type *)PWM_5_BASE) +#define PWM_6_REGS ((PWM_Type *)PWM_6_BASE) +#define PWM_7_REGS ((PWM_Type *)PWM_7_BASE) +#define PWM_8_REGS ((PWM_Type *)PWM_8_BASE) + +#define TACH_0_REGS ((TACH_Type *)TACH_0_BASE) +#define TACH_1_REGS ((TACH_Type *)TACH_1_BASE) +#define TACH_2_REGS ((TACH_Type *)TACH_2_BASE) +#define TACH_3_REGS ((TACH_Type *)TACH_3_BASE) + +#define PECI_REGS ((PECI_Type *)PECI_0_BASE) + +#define SPIP_0_REGS ((SPIP_Type *)SPIP_0_BASE) + +#define RTMR_0_REGS ((RTMR_Type *)RTMR_0_BASE) +/* backwards compatible alias */ +#define RTMR_REGS RTMR_0_REGS + +#define ADC_0_REGS ((ADC_Type *)ADC_0_BASE) + +#define TFDP_0_REGS ((TFDP_Type *)TFDP_0_BASE) + +#define PS2_0_REGS ((PS2_Type *)PS2_0_BASE) + +#define GPSPI_0_REGS ((GPSPI_Type *)GPSPI_0_BASE) +#define GPSPI_1_REGS ((GPSPI_Type *)GPSPI_1_BASE) + +#define HTMR_0_REGS ((HTMR_Type *)HTMR_0_BASE) +#define HTMR_1_REGS ((HTMR_Type *)HTMR_1_BASE) + +#define KSCAN_REGS ((KSCAN_Type *)(KEYSCAN_BASE)) + +#define RPMFAN_0_REGS ((RPMFAN_Type *)RPMFAN_0_BASE) +#define RPMFAN_1_REGS ((RPMFAN_Type *)RPMFAN_0_BASE) + +#define VBATR_REGS ((VBATR_Type *)VBATR_BASE) +#define VBATM_REGS ((VBATM_Type *)VBATM_BASE) +#define WKTMR_REGS ((WKTMR_Type *)WKTMR_BASE) + +#define VCI_REGS ((VCI_Type *)VCI_BASE) + +#define LED_0_REGS ((LED_Type *)LED_0_BASE) +#define LED_1_REGS ((LED_Type *)LED_1_BASE) +#define LED_2_REGS ((LED_Type *)LED_2_BASE) +#define LED_3_REGS ((LED_Type *)LED_3_BASE) + +#define BCL_0_REGS ((BCL_Type *)BCL_0_BASE) + +#define ECIA_REGS ((ECIA_Type *)ECIA_BASE) +#define ECIA_AR_REGS ((ECIA_AR_Type *)ECIA_BASE) +#define GIRQ08_REGS ((GIRQ_Type *)GIRQ_BASE(8)) +#define GIRQ09_REGS ((GIRQ_Type *)GIRQ_BASE(9)) +#define GIRQ10_REGS ((GIRQ_Type *)GIRQ_BASE(10)) +#define GIRQ11_REGS ((GIRQ_Type *)GIRQ_BASE(11)) +#define GIRQ12_REGS ((GIRQ_Type *)GIRQ_BASE(12)) +#define GIRQ13_REGS ((GIRQ_Type *)GIRQ_BASE(13)) +#define GIRQ14_REGS ((GIRQ_Type *)GIRQ_BASE(14)) +#define GIRQ15_REGS ((GIRQ_Type *)GIRQ_BASE(15)) +#define GIRQ16_REGS ((GIRQ_Type *)GIRQ_BASE(16)) +#define GIRQ17_REGS ((GIRQ_Type *)GIRQ_BASE(17)) +#define GIRQ18_REGS ((GIRQ_Type *)GIRQ_BASE(18)) +#define GIRQ19_REGS ((GIRQ_Type *)GIRQ_BASE(19)) +#define GIRQ20_REGS ((GIRQ_Type *)GIRQ_BASE(20)) +#define GIRQ21_REGS ((GIRQ_Type *)GIRQ_BASE(21)) +#define GIRQ22_REGS ((GIRQ_Type *)GIRQ_BASE(22)) +#define GIRQ23_REGS ((GIRQ_Type *)GIRQ_BASE(23)) +#define GIRQ24_REGS ((GIRQ_Type *)GIRQ_BASE(24)) +#define GIRQ25_REGS ((GIRQ_Type *)GIRQ_BASE(25)) +#define GIRQ26_REGS ((GIRQ_Type *)GIRQ_BASE(26)) + +#define ECS_REGS ((ECS_Type *)ECS_BASE) + +#define QMSPI_REGS ((QMSPI_Type *)QMSPI_0_BASE) + +#define PCR_REGS ((PCR_Type *)PCR_BASE) + +#define GPIO_REGS ((GPIO_Type *)(GPIO_CTRL_BASE)) +#define GPIO_CTRL_REGS ((GPIO_CTRL_Type *)(GPIO_CTRL_BASE)) +#define GPIO_CTRL2_REGS ((GPIO_CTRL2_Type *)(GPIO_CTRL2_BASE)) +#define GPIO_PARIN_REGS ((GPIO_PARIN_Type *)(GPIO_PARIN_BASE)) +#define GPIO_PAROUT_REGS ((GPIO_PAROUT_Type *)(GPIO_PAROUT_BASE)) +#define GPIO_LOCK_REGS ((GPIO_LOCK_Type *)(GPIO_LOCK_BASE)) + +#define MBOX_0_REGS ((MBOX_Type *)(MBOX_0_BASE)) + +#define KBC_0_REGS ((KBC_Type *)(KBC_0_BASE)) +/* backwards compatible */ +#define KBC_REGS KBC_0_REGS + +#define ACPI_EC_0_REGS ((ACPI_EC_Type *)(ACPI_EC_BASE(0))) +#define ACPI_EC_1_REGS ((ACPI_EC_Type *)(ACPI_EC_BASE(1))) +#define ACPI_EC_2_REGS ((ACPI_EC_Type *)(ACPI_EC_BASE(2))) +#define ACPI_EC_3_REGS ((ACPI_EC_Type *)(ACPI_EC_BASE(3))) +#define ACPI_EC_4_REGS ((ACPI_EC_Type *)(ACPI_EC_BASE(4))) + +#define ACPI_PM1_REGS ((ACPI_PM1_Type *)ACPI_PM1_BASE) + +#define PORT92_REGS ((PORT92_Type *)(PORT92_BASE)) + +#define UART_0_REGS ((UART_Type *)UART_0_BASE) +#define UART_1_REGS ((UART_Type *)UART_1_BASE) +/* backwards compatible */ +#define UART0_REGS UART_0_REGS +#define UART1_REGS UART_1_REGS + +#define GLUE_REGS ((GLUE_Type *)(GLUE_BASE)) + +#define EMI0_REGS ((EMI_Type *)(EMI_0_BASE)) +#define EMI1_REGS ((EMI_Type *)(EMI_1_BASE)) +#define EMI2_REGS ((EMI_Type *)(EMI_2_BASE)) + +#define RTC_REGS ((RTC_Type *)RTC_BASE) + +#define P80BD_0_REGS ((P80BD_Type *)(P80BD_0_BASE)) + +#define GLOBAL_CFG_REGS ((GLOBAL_CFG_Type *)GCFG_BASE) + +/* -------- eSPI Register instaniations -------- */ +#define ESPI_PC_REGS ((ESPI_IO_PC_Type *)(ESPI_IO_PC_BASE)) + +#define ESPI_HIO_BAR_REGS ((ESPI_IO_BAR_HOST_Type *)(ESPI_IO_HOST_BAR_BASE)) + +#define ESPI_LTR_REGS ((ESPI_IO_LTR_Type *)(ESPI_IO_LTR_BASE)) +#define ESPI_OOB_REGS ((ESPI_IO_OOB_Type *)(ESPI_IO_OOB_BASE)) +#define ESPI_FC_REGS ((ESPI_IO_FC_Type *)(ESPI_IO_FC_BASE)) +#define ESPI_CAP_REGS ((ESPI_IO_CAP_Type *)(ESPI_IO_CAP_BASE)) +#define ESPI_EIO_BAR_REGS ((ESPI_IO_BAR_EC_Type *)(ESPI_IO_EC_BAR_BASE)) +#define ESPI_SIRQ_REGS ((ESPI_IO_SIRQ_Type *)(ESPI_IO_SIRQ_BASE)) +#define ESPI_SIRQ_AR_REGS ((ESPI_IO_SIRQ_AR_Type *)(ESPI_IO_SIRQ_BASE)) + +#define ESPI_MEM_EBAR_REGS ((ESPI_MEM_BAR_EC_Type *)(ESPI_MEM_EC_BAR_BASE)) +#define ESPI_MEM_HBAR_REGS ((ESPI_MEM_BAR_HOST_Type *)(ESPI_MEM_HOST_BAR_BASE)) + +#define ESPI_MEM_SRAM_EBAR_REGS \ + ((ESPI_MEM_SRAM_BAR_EC_Type *)(ESPI_MEM_SRAM_EC_BAR_BASE)) +#define ESPI_MEM_SRAM_HBAR_REGS \ + ((ESPI_MEM_SRAM_BAR_HOST_Type *)(ESPI_MEM_SRAM_HOST_BAR_BASE)) + +#define ESPI_MEM_BM_REGS ((ESPI_MEM_BM_Type *)(ESPI_MEM_BM_BASE)) + +/* eSPI Virtual Wire registers in IO component */ +#define ESPI_IO_VW_REGS ((ESPI_IO_VW_Type *)(ESPI_IO_VW_BASE)) +/* eSPI Virtual Wire registers for each group of 4 VWires */ +#define ESPI_M2S_VW_REGS ((ESPI_M2S_VW_Type *)(ESPI_VW_BASE)) +#define ESPI_S2M_VW_REGS ((ESPI_S2M_VW_Type *)(ESPI_SMVW_BASE)) + +/** @} */ /* End of group MEC172x_Peripheral_declaration */ + +/** @} */ /* End of group MEC172XNSZ */ + +/** @} */ /* End of group MCHP */ + +#ifdef __cplusplus +} +#endif +#endif /* MEC172XNSZ_H */ diff --git a/mec/mec172x/component/acpi_ec.h b/mec/mec172x/component/acpi_ec.h new file mode 100644 index 0000000..2ad661f --- /dev/null +++ b/mec/mec172x/component/acpi_ec.h @@ -0,0 +1,204 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file acpi_ec.h + * MEC172x ACPI EC Registers + */ +/** @defgroup MEC172x Peripherals ACPI_EC + */ + +#ifndef _ACPI_EC_H +#define _ACPI_EC_H + +#include +#include + +#include +#include + +#define MCHP_ACPI_EC_BASE_ADDR 0x400f0800U +#define MCHP_ACPI_EC_SPACING 0x0400U +#define MCHP_ACPI_EC_SPACING_PWROF2 10U + +/* 0 <= n < MCHP_ACPI_EC_INSTANCES */ +#define MCHP_ACPI_EC_ADDR(n) (MCHP_ACPI_EC_BASE_ADDR + \ + ((uint32_t)(n) * MCHP_ACPI_EC_SPACING)) + +/* ACPI_EC interrupts */ +#define MCHP_ACPI_EC_GIRQ 15u +#define MCHP_ACPI_EC_GIRQ_NVIC 7u + +#define MCHP_ACPI_EC_0_IBF_NVIC 45u +#define MCHP_ACPI_EC_0_OBE_NVIC 46u +#define MCHP_ACPI_EC_0_IBF_GIRQ_POS 5u +#define MCHP_ACPI_EC_0_OBE_GIRQ_POS 6u +#define MCHP_ACPI_EC_0_IBF_GIRQ BIT(5) +#define MCHP_ACPI_EC_0_OBE_GIRQ BIT(6) + +#define MCHP_ACPI_EC_1_IBF_NVIC 47u +#define MCHP_ACPI_EC_1_OBE_NVIC 48u +#define MCHP_ACPI_EC_1_IBF_GIRQ_POS 7u +#define MCHP_ACPI_EC_1_OBE_GIRQ_POS 8u +#define MCHP_ACPI_EC_1_IBF_GIRQ BIT(7) +#define MCHP_ACPI_EC_1_OBE_GIRQ BIT(8) + +#define MCHP_ACPI_EC_2_IBF_NVIC 49u +#define MCHP_ACPI_EC_2_OBE_NVIC 50u +#define MCHP_ACPI_EC_2_IBF_GIRQ_POS 9u +#define MCHP_ACPI_EC_2_OBE_GIRQ_POS 10u +#define MCHP_ACPI_EC_2_IBF_GIRQ BIT(9) +#define MCHP_ACPI_EC_2_OBE_GIRQ BIT(10) + +#define MCHP_ACPI_EC_3_IBF_NVIC 51u +#define MCHP_ACPI_EC_3_OBE_NVIC 52u +#define MCHP_ACPI_EC_3_IBF_GIRQ_POS 11u +#define MCHP_ACPI_EC_3_OBE_GIRQ_POS 12u +#define MCHP_ACPI_EC_3_IBF_GIRQ BIT(11) +#define MCHP_ACPI_EC_3_OBE_GIRQ BIT(12) + +/* 0 <= n < MCHP_ACPI_EC_INSTANCES */ +#define MCHP_ACPI_EC_IBF_NVIC(n) (45ul + ((uint32_t)(n) * 2U)) +#define MCHP_ACPI_EC_OBE_NVIC(n) (46ul + ((uint32_t)(n) * 2U)) +#define MCHP_ACPI_EC_IBF_GIRQ_POS(n) (5ul + ((uint32_t)(n) * 2U)) +#define MCHP_ACPI_EC_OBE_GIRQ_POS(n) (6ul + ((uint32_t)(n) * 2U)) +#define MCHP_ACPI_EC_IBF_GIRQ(n) BIT(MCHP_ACPI_EC_IBF_GIRQ_POS(n)) +#define MCHP_ACPI_EC_OBE_GIRQ(n) BIT(MCHP_ACPI_EC_OBE_GIRQ_POS(n)) + +/* EC_STS and OS_CMD_STS(read) bit definitions */ +#define MCHP_ACPI_EC_STS_OBF_POS 0u +#define MCHP_ACPI_EC_STS_OBF BIT(MCHP_ACPI_EC_STS_OBF_POS) +#define MCHP_ACPI_EC_STS_IBF_POS 1u +#define MCHP_ACPI_EC_STS_IBF BIT(MCHP_ACPI_EC_STS_IBF_POS) +#define MCHP_ACPI_EC_STS_UD1A_POS 2u +#define MCHP_ACPI_EC_STS_UD1A BIT(MCHP_ACPI_EC_STS_UD1A_POS) +#define MCHP_ACPI_EC_STS_CMD_POS 3u +#define MCHP_ACPI_EC_STS_CMD BIT(MCHP_ACPI_EC_STS_CMD_POS) +#define MCHP_ACPI_EC_STS_BURST_POS 4u +#define MCHP_ACPI_EC_STS_BURST BIT(MCHP_ACPI_EC_STS_BURST_POS) +#define MCHP_ACPI_EC_STS_SCI_POS 5u +#define MCHP_ACPI_EC_STS_SCI BIT(MCHP_ACPI_EC_STS_SCI_POS) +#define MCHP_ACPI_EC_STS_SMI_POS 6u +#define MCHP_ACPI_EC_STS_SMI BIT(MCHP_ACPI_EC_STS_SMI_POS) +#define MCHP_ACPI_EC_STS_UD0A_POS 7u +#define MCHP_ACPI_EC_STS_UD0A BIT(MCHP_ACPI_EC_STS_UD0A_POS) + +/* EC_BYTE_CTRL and OS_BYTE_CTRL */ +#define MCHP_ACPI_EC_BYTE_CTRL_4B_POS 0u +#define MCHP_ACPI_EC_BYTE_CTRL_4B_EN BIT(MCHP_ACPI_EC_BYTE_CTRL_4B_POS) + +/* =========================================================================*/ +/* ================ ACPI_PM1 =================== */ +/* =========================================================================*/ + +#define MCHP_ACPI_PM1_BASE_ADDR 0x400F1C00ul + +/* + * ACPI_PM1 interrupts + */ +#define MCHP_ACPI_PM1_CTL_GIRQ 15u +#define MCHP_ACPI_PM1_EN_GIRQ 15u +#define MCHP_ACPI_PM1_STS_GIRQ 15u + +/* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ +#define MCHP_ACPI_PM1_CTL_GIRQ_POS 15u +#define MCHP_ACPI_PM1_EN_GIRQ_POS 16u +#define MCHP_ACPI_PM1_STS_GIRQ_POS 17u + +#define MCHP_ACPI_PM1_CTL_GIRQ_VAL BIT(MCHP_ACPI_PM1_CTL_GIRQ_POS) +#define MCHP_ACPI_PM1_EN_GIRQ_VAL BIT(MCHP_ACPI_PM1_EN_GIRQ_POS) +#define MCHP_ACPI_PM1_STS_GIRQ_VAL BIT(MCHP_ACPI_PM1_STS_GIRQ_POS) + +/* VCI GIRQ aggregated NVIC input */ +#define MCHP_ACPI_PM1_CTL_NVIC_AGGR 7u +#define MCHP_ACPI_PM1_EN_NVIC_AGGR 7u +#define MCHP_ACPI_PM1_STS_NVIC_AGGR 7u + +/* VCI direct NVIC inputs */ +#define MCHP_ACPI_PM1_CTL_NVIC_DIRECT 55u +#define MCHP_ACPI_PM1_EN_NVIC_DIRECT 56u +#define MCHP_ACPI_PM1_STS_NVIC_DIRECT 57u + +/* ACPI_PM1 RT/EC Status 1 */ +#define MCHP_ACPI_PM1_RT_STS1_REG_OFS 0x0000ul +#define MCHP_ACPI_PM1_EC_STS1_REG_OFS 0x0100ul +#define MCHP_ACPI_PM1_STS1_REG_MASK 0x0000ul + +/* ACPI_PM1 RT/EC Status 2 */ +#define MCHP_ACPI_PM1_RT_STS2_REG_OFS 0x0001ul +#define MCHP_ACPI_PM1_EC_STS2_REG_OFS 0x0101ul +#define MCHP_ACPI_PM1_STS2_REG_MASK 0x008Ful +#define MCHP_ACPI_PM1_STS2_PWRBTN BIT(0) +#define MCHP_ACPI_PM1_STS2_SLPBTN BIT(1) +#define MCHP_ACPI_PM1_STS2_RTC BIT(2) +#define MCHP_ACPI_PM1_STS2_PWRBTNOR BIT(3) +#define MCHP_ACPI_PM1_STS2_WAK BIT(7) + +/* ACPI_PM1 RT/EC Enable 1 */ +#define MCHP_ACPI_PM1_RT_EN1_REG_OFS 0x0002ul +#define MCHP_ACPI_PM1_EC_EN1_REG_OFS 0x0102ul +#define MCHP_ACPI_PM1_EN1_REG_MASK 0x0000ul + +/* ACPI_PM1 RT/EC Enable 2 */ +#define MCHP_ACPI_PM1_RT_EN2_REG_OFS 0x0003ul +#define MCHP_ACPI_PM1_EC_EN2_REG_OFS 0x0103ul +#define MCHP_ACPI_PM1_EN2_REG_MASK 0x0007ul +#define MCHP_ACPI_PM1_EN2_PWRBTN BIT(0) +#define MCHP_ACPI_PM1_EN2_SLPBTN BIT(1) +#define MCHP_ACPI_PM1_EN2_RTC BIT(2) + +/* ACPI_PM1 RT/EC Control 1 */ +#define MCHP_ACPI_PM1_RT_CTRL1_REG_OFS 0x0004ul +#define MCHP_ACPI_PM1_EC_CTRL1_REG_OFS 0x0104ul +#define MCHP_ACPI_PM1_CTRL1_REG_MASK 0x0000ul + +/* ACPI_PM1 RT/EC Control 2 */ +#define MCHP_ACPI_PM1_RT_CTRL2_REG_OFS 0x0005ul +#define MCHP_ACPI_PM1_EC_CTRL2_REG_OFS 0x0105ul +#define MCHP_ACPI_PM1_CTRL2_REG_MASK 0x003Eul +#define MCHP_ACPI_PM1_CTRL2_PWRBTNOR_EN BIT(1) +#define MCHP_ACPI_PM1_CTRL2_SLP_TYPE_POS 2 +#define MCHP_ACPI_PM1_CTRL2_SLP_TYPE_MASK SHLU32(0x03u, 2) +#define MCHP_ACPI_PM1_CTRL2_SLP_EN BIT(5) + +/* ACPI_PM1 RT/EC Control 21 */ +#define MCHP_ACPI_PM1_RT_CTRL21_REG_OFS 0x0006ul +#define MCHP_ACPI_PM1_EC_CTRL21_REG_OFS 0x0106ul +#define MCHP_ACPI_PM1_CTRL21_REG_MASK 0x0000ul + +/* ACPI_PM1 RT/EC Control 22 */ +#define MCHP_ACPI_PM1_RT_CTRL22_REG_OFS 0x0007ul +#define MCHP_ACPI_PM1_EC_CTRL22_REG_OFS 0x0107ul +#define MCHP_ACPI_PM1_CTRL22_REG_MASK 0x0000ul + +/* ACPI_PM1 EC PM Status register */ +#define MCHP_ACPI_PM1_EC_PM_STS_REG_OFS 0x0110ul +#define MCHP_ACPI_PM1_EC_PM_STS_REG_MASK 0x0001ul +#define MCHP_ACPI_PM1_EC_PM_STS_SCI 0x0001ul + +#endif /* #ifndef _ACPI_EC_H */ +/* end acpi_ec.h */ +/** @} + */ diff --git a/mec/mec172x/component/adc.h b/mec/mec172x/component/adc.h new file mode 100644 index 0000000..e6268f4 --- /dev/null +++ b/mec/mec172x/component/adc.h @@ -0,0 +1,188 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file peci.h + * MEC172x Analog to Digital Converter registers + */ +/** @defgroup MEC172x Peripherals ADC + */ + +#ifndef _ADC_H +#define _ADC_H + +#include +#include + +#include +#include + +/* =========================================================================*/ +/* ================ ADC =========== */ +/* =========================================================================*/ + +#define MCHP_ADC_BASE_ADDR 0x40007C00ul + +/* + * ADC block implements two interrupt signals: + * single conversion and repeat conversion done. + */ +#define MCHP_ADC_GIRQ 17u + +/* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ +#define MCHP_ADC_SNG_DONE_GIRQ_POS 8 +#define MCHP_ADC_RPT_DONE_GIRQ_POS 9 + +#define MCHP_ADC_SNG_DONE_GIRQ_VAL BIT(MCHP_ADC_SNG_DONE_GIRQ_POS) +#define MCHP_ADC_RPT_DONE_GIRQ_VAL BIT(MCHP_ADC_RPT_DONE_GIRQ_POS) + +/* ADC GIRQ aggregated NVIC input */ +#define MCHP_ADC_SNG_DONE_NVIC_AGGR 9u +#define MCHP_ADC_RPT_DONE_NVIC_AGGR 9u + +/* ADC direct NVIC inputs */ +#define MCHP_ADC_SNG_DONE_NVIC_DIRECT 78u +#define MCHP_ADC_RPT_DONE_NVIC_DIRECT 79u + +/* Eight ADC channels numbered 0 - 7 */ +#define MCHP_ADC_MAX_CHAN 8u +#define MCHP_ADC_MAX_CHAN_MASK 0x07u + +/* Control register */ +#define MCHP_ADC_CTRL_REG_OFS 0u +#define MCHP_ADC_CTRL_REG_MASK 0xDFu +#define MCHP_ADC_CTRL_REG_RW_MASK 0x1Fu +#define MCHP_ADC_CTRL_REG_RW1C_MASK 0xC0u +#define MCHP_ADC_CTRL_ACTV BIT(0) +#define MCHP_ADC_CTRL_START_SNGL BIT(1) +#define MCHP_ADC_CTRL_START_RPT BIT(2) +#define MCHP_ADC_CTRL_PWRSV_DIS BIT(3) +#define MCHP_ADC_CTRL_SRST BIT(4) +#define MCHP_ADC_CTRL_RPT_DONE_STS BIT(6) /* R/W1C */ +#define MCHP_ADC_CTRL_SNGL_DONE_STS BIT(7) /* R/W1C */ + +/* Delay register. Start and repeat delays in units of 40 us */ +#define MCHP_ADC_DELAY_REG_OFS 4u +#define MCHP_ADC_DELAY_REG_MASK 0xFFFFFFFFu +#define MCHP_ADC_DELAY_START_POS 0u +#define MCHP_ADC_DELAY_START_MASK 0xFFFFu +#define MCHP_ADC_DELAY_RPT_POS 16u +#define MCHP_ADC_DELAY_RPT_MASK 0xFFFF0000u + +/* Status register. 0 <= n < MCHP_ADC_MAX_CHAN */ +#define MCHP_ADC_STATUS_REG_OFS 8u +#define MCHP_ADC_STATUS_REG_MASK 0xFFFFu +#define MCHP_ADC_STATUS_CHAN(n) BIT(n) + +/* Single Conversion Select register */ +#define MCHP_ADC_SCS_REG_OFS 0x0Cu +#define MCHP_ADC_SCS_REG_MASK 0xffu +#define MCHP_ADC_SCS_CH_0_7 0xffu +#define MCHP_ADC_SCS_CH(n) BIT(((n) & 0x07)) + +/* Repeat Conversion Select register */ +#define MCHP_ADC_RCS_REG_OFS 0x10u +#define MCHP_ADC_RCS_REG_MASK 0xffu +#define MCHP_ADC_RCS_CH_0_7 0xffu +#define MCHP_ADC_RCS_CH(n) BIT(((n) & 0x07)) + +/* Channel reading registers */ +#define MCHP_ADC_RDCH_REG_MASK 0xFFFul +#define MCHP_ADC_RDCH0_REG_OFS 0x14 +#define MCHP_ADC_RDCH1_REG_OFS 0x18 +#define MCHP_ADC_RDCH2_REG_OFS 0x1C +#define MCHP_ADC_RDCH3_REG_OFS 0x20 +#define MCHP_ADC_RDCH4_REG_OFS 0x24 +#define MCHP_ADC_RDCH5_REG_OFS 0x28 +#define MCHP_ADC_RDCH6_REG_OFS 0x2C +#define MCHP_ADC_RDCH7_REG_OFS 0x30 + +/* Configuration register */ +#define MCHP_ADC_CFG_REG_OFS 0x7Cu +#define MCHP_ADC_CFG_REG_MASK 0xffffu +#define MCHP_ADC_CFG_CLK_LO_TIME_POS 0 +#define MCHP_ADC_CFG_CLK_LO_TIME_MASK0 0xffu +#define MCHP_ADC_CFG_CLK_LO_TIME_MASK 0xffu +#define MCHP_ADC_CFG_CLK_HI_TIME_POS 8 +#define MCHP_ADC_CFG_CLK_HI_TIME_MASK0 0xffu +#define MCHP_ADC_CFG_CLK_HI_TIME_MASK SHLU32(0xffu, 8) + +/* Channel Vref Select register */ +#define MCHP_ADC_CH_VREF_SEL_REG_OFS 0x80u +#define MCHP_ADC_CH_VREF_SEL_REG_MASK 0x00fffffful +#define MCHP_ADC_CH_VREF_SEL_MASK(n) SHLU32(0x03u, (((n) & 0x07) * 2U)) +#define MCHP_ADC_CH_VREF_SEL_PAD(n) 0u +#define MCHP_ADC_CH_VREF_SEL_GPIO(n) SHLU32(0x01u, (((n) & 0x07) * 2U)) + +/* Vref Control register */ +#define MCHP_ADC_VREF_CTRL_REG_OFS 0x84u +#define MCHP_ADC_VREF_CTRL_REG_MASK 0xffffffffu +#define MCHP_ADC_VREF_CTRL_CHRG_DEL_POS 0 +#define MCHP_ADC_VREF_CTRL_CHRG_DEL_MASK0 0xffffu +#define MCHP_ADC_VREF_CTRL_CHRG_DEL_MASK 0xffffu +#define MCHP_ADC_VREF_CTRL_SW_DEL_POS 16 +#define MCHP_ADC_VREF_CTRL_SW_DEL_MASK0 0x1fffu +#define MCHP_ADC_VREF_CTRL_SW_DEL_MASK SHLU32(0x1ffful, 16) +#define MCHP_ADC_VREF_CTRL_PAD_POS 29 +#define MCHP_ADC_VREF_CTRL_PAD_UNUSED_FLOAT 0ul +#define MCHP_ADC_VREF_CTRL_PAD_UNUSED_DRIVE_LO BIT(29) +#define MCHP_ADC_VREF_CTRL_SEL_STS_POS 30 +#define MCHP_ADC_VREF_CTRL_SEL_STS_MASK0 0x03u +#define MCHP_ADC_VREF_CTRL_SEL_STS_MASK SHLU32(0x03u, 30) + +/* SAR ADC Control register */ +#define MCHP_ADC_SAR_CTRL_REG_OFS 0x88u +#define MCHP_ADC_SAR_CTRL_REG_MASK 0x0001FF8Ful +/* Select single ended or differential operation */ +#define MCHP_ADC_SAR_CTRL_SELDIFF_POS 0 +#define MCHP_ADC_SAR_CTRL_SELDIFF_DIS 0ul +#define MCHP_ADC_SAR_CTRL_SELDIFF_EN BIT(0) +/* Select resolution */ +#define MCHP_ADC_SAR_CTRL_RES_POS 1 +#define MCHP_ADC_SAR_CTRL_RES_MASK0 0x03u +#define MCHP_ADC_SAR_CTRL_RES_MASK 0x06u +#define MCHP_ADC_SAR_CTRL_RES_10_BITS 0x04u +#define MCHP_ADC_SAR_CTRL_RES_12_BITS 0x06u +/* Shift data in reading register */ +#define MCHP_ADC_SAR_CTRL_SHIFTD_POS 3 +#define MCHP_ADC_SAR_CTRL_SHIFTD_DIS 0ul +#define MCHP_ADC_SAR_CTRL_SHIFTD_EN BIT(3) +/* Warm up delay in ADC clock cycles */ +#define MCHP_ADC_SAR_CTRL_WUP_DLY_POS 7 +#define MCHP_ADC_SAR_CTRL_WUP_DLY_MASK0 0x3fful +#define MCHP_ADC_SAR_CTRL_WUP_DLY_MASK SHLU32(0x3ffu, 7) +#define MCHP_ADC_SAR_CTRL_WUP_DLY_DFLT SHLU32(0x202u, 7) + +/* Register interface */ +#define MCHP_ADC_CH_NUM(n) ((n) & MCHP_ADC_MAX_CHAN_MASK) +#define MCHP_ADC_CH_OFS(n) (MCHP_ADC_CH_NUM(n) * 4U) +#define MCHP_ADC_CH_ADDR(n) (MCHP_ADC_BASE_ADDR + MCHP_ADC_CH_OFS(n)) + +#define MCHP_ADC_RD_CHAN(n) REG32(MCHP_ADC_CH_ADDR(n)) + +#endif /* #ifndef _ADC_H */ +/* end adc.h */ +/** @} + */ diff --git a/mec/mec172x/component/bcl.h b/mec/mec172x/component/bcl.h new file mode 100644 index 0000000..c793418 --- /dev/null +++ b/mec/mec172x/component/bcl.h @@ -0,0 +1,87 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file bcl.h + * MEC172x BC-Link controller registers + */ +/** @defgroup MEC172x Peripherals BCL + */ + +#ifndef _COMPONENT_BCL_H +#define _COMPONENT_BCL_H + +#include +#include + +#include +#include + +#define MCHP_BCL_0_BASE_ADDR 0x4000CD00ul + +#define MCHP_BCL_0_GIRQ 18u +#define MCHP_BCL_0_NVIC_GIRQ 10u +#define MCHP_BCL_0_BCLR_POS 6u +#define MCHP_BCL_0_ERR_POS 7u +#define MCHP_BCL_0_BCLR_NVIC 97u +#define MCHP_BCL_0_ERR_NVIC 96u +#define MCHP_BCL_0_BCLR_GIRQ_VAL BIT(6) +#define MCHP_BCL_0_ERR_GIRQ_VAL BIT(7) + +/* EC-only registers */ + +/* BCL Status register at 0x00 */ +#define MCHP_BCL_STS_OFS 0x00u +#define MCHP_BCL_STS_MASK 0xF1u +#define MCHP_BCL_STS_RESET BIT(7) +#define MCHP_BCL_STS_ERR_RWC BIT(6) +#define MCHP_BCL_STS_ERR_IEN BIT(5) +#define MCHP_BCL_STS_BCLR_IEN BIT(4) +#define MCHP_BCL_STS_BUSY_RO BIT(0) + +/* BCL Target address register at 0x04 */ +#define MCHP_BCL_TADDR_OFS 0x04u +#define MCHP_BCL_TADDR_MASK 0xFFu + +/* BCL Data register at 0x08 */ +#define MCHP_BCL_DATA_OFS 0x08u +#define MCHP_BCL_DATA_MASK 0xFFu + +/* BCL Clock select register at 0x0C */ +#define MCHP_BCL_CLKSEL_OFS 0x0Cu +#define MCHP_BCL_CLKSEL_DIV_MSK 0xFFu +#define MCHP_BCL_CLKSEL_DFLT 0x04u +#define MCHP_BCL_CLKSEL_48M 0x00u +#define MCHP_BCL_CLKSEL_24M 0x01u +#define MCHP_BCL_CLKSEL_16M 0x02u +#define MCHP_BCL_CLKSEL_12M 0x03u +#define MCHP_BCL_CLKSEL_8M 0x05u +#define MCHP_BCL_CLKSEL_6M 0x07u +#define MCHP_BCL_CLKSEL_1M 0x2Fu + +#endif /* #ifndef _COMPONENT_BCL_H */ +/* end bcl.h */ +/** @} + */ diff --git a/mec/mec172x/component/dma.h b/mec/mec172x/component/dma.h new file mode 100644 index 0000000..06c3185 --- /dev/null +++ b/mec/mec172x/component/dma.h @@ -0,0 +1,446 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file dma.h + * MEC172x DMA controller definitions + */ +/** @defgroup MEC172x Peripherals DMA + */ + +#ifndef _COMPONENT_DMA_H +#define _COMPONENT_DMA_H + +#include +#include +#include + +#include +#include + +#define MCHP_NUM_DMA_CHANNELS 16ul + +#define MCHP_DMA_BLOCK_BASE_ADDR 0x40002400ul +#define MCHP_DMA_CHAN_OFFSET 0x40ul +#define MCHP_DMA_OFFSET_POF2 6u +#define MCHP_DMA_CHAN0_ADDR \ + ((MCHP_DMA_BLOCK_BASE_ADDR) + (MCHP_DMA_CHAN_OFFSET)) + +#define MCHP_DMA_CHAN_ADDR(n) ((uintptr_t)(MCHP_DMA_CHAN0_ADDR) + \ + ((uintptr_t)(n) << MCHP_DMA_OFFSET_POF2)) + +/* + * DMA block PCR register and bit + * Bit position applied to PCR Sleep Enable, Clock Req(RO), and Reset + * registers. + */ +#define MCHP_DMA_PCR_SLP_EN_ADDR 0x40080134ul +#define MCHP_DMA_PCR_CLK_REQ_ADDR 0x40080154ul +#define MCHP_DMA_PCR_RST_ADDR 0x40080174ul +#define MCHP_DMA_PCR_SCR_POS 6u +#define MCHP_DMA_PCR_SCR_VAL BIT(6) + +#define MCHP_DMA_GIRQ_ID 14u +#define MCHP_DMA_GIRQ_SRC_ADDR 0x4000E078ul +#define MCHP_DMA_GIRQ_EN_SET_ADDR 0x4000E07Cul +#define MCHP_DMA_GIRQ_RESULT_ADDR 0x4000E080ul +#define MCHP_DMA_GIRQ_EN_CLR_ADDR 0x4000E084ul + +#define MCHP_DMA_GIRQ_NUM 14u +#define MCHP_DMA_GIRQ_IDX ((MCHP_DMA_GIRQ_NUM) -8u) + +/* Aggregated GIRQ14 NVIC input */ +#define MCHP_DMA_AGGR_NVIC 6u + +/* + * Value used for GIRQ Source, Set Enable, + * Result, and Clear Enable registers. + * 0 <= ch < MCHP_NUM_DMA_CHANNELS + */ +#define MCHP_DMA_GIRQ_VAL(ch) BIT(ch) + +/* + * DMA channel direct NVIC external interrupt inputs + * 0 <= ch < 12 + */ +#define MCHP_DMA_DIRECT_NVIC_NUM(ch) (24ul + (ch)) + +/* + * DMA channel direct NVIC external interrupt input from channel address. + * Channels are located starting at offset 0x40 from DMA block base address. + * Channels are spaced every 0x40 bytes. + * DMA block has 1KB total register space. + */ +#define MCHP_DMA_DIRECT_NVIC_NUM_BA(chba) \ + (24ul + (((uintptr_t)(chba) - (uintptr_t)MCHP_DMA_CHAN_ADDR(0)) >> 6)) + +#define MCHP_DMA0_GIRQ_NVIC (24u + 0u) +#define MCHP_DMA1_GIRQ_NVIC (24u + 1u) +#define MCHP_DMA2_GIRQ_NVIC (24u + 2u) +#define MCHP_DMA3_GIRQ_NVIC (24u + 3u) +#define MCHP_DMA4_GIRQ_NVIC (24u + 4u) +#define MCHP_DMA5_GIRQ_NVIC (24u + 5u) +#define MCHP_DMA6_GIRQ_NVIC (24u + 6u) +#define MCHP_DMA7_GIRQ_NVIC (24u + 7u) +#define MCHP_DMA8_GIRQ_NVIC (24u + 8u) +#define MCHP_DMA9_GIRQ_NVIC (24u + 9u) +#define MCHP_DMA10_GIRQ_NVIC (24u + 10u) +#define MCHP_DMA11_GIRQ_NVIC (24u + 11u) +#define MCHP_DMA12_GIRQ_NVIC (24u + 12u) +#define MCHP_DMA13_GIRQ_NVIC (24u + 13u) +#define MCHP_DMA14_GIRQ_NVIC (24u + 14u) +#define MCHP_DMA15_GIRQ_NVIC (24u + 15u) + +/* GIRQ bit position from channel base address */ +#define MCHP_DMA_GIRQ_POS_BA(chba) \ + (((uintptr_t)(chba) - (uintptr_t)MCHP_DMA_CHAN_ADDR(0)) >> 6) + +#define MCHP_DMA_GIRQ_VAL_BA(chba) \ + (1ul << MCHP_DMA_GIRQ_POS_BA(chba)) + +#define MCHP_DMA0_GIRQ_POS 0u +#define MCHP_DMA1_GIRQ_POS 1u +#define MCHP_DMA2_GIRQ_POS 2u +#define MCHP_DMA3_GIRQ_POS 3u +#define MCHP_DMA4_GIRQ_POS 4u +#define MCHP_DMA5_GIRQ_POS 5u +#define MCHP_DMA6_GIRQ_POS 6u +#define MCHP_DMA7_GIRQ_POS 7u +#define MCHP_DMA8_GIRQ_POS 8u +#define MCHP_DMA9_GIRQ_POS 9u +#define MCHP_DMA10_GIRQ_POS 10u +#define MCHP_DMA11_GIRQ_POS 11u +#define MCHP_DMA12_GIRQ_POS 12u +#define MCHP_DMA13_GIRQ_POS 13u +#define MCHP_DMA14_GIRQ_POS 14u +#define MCHP_DMA15_GIRQ_POS 15u + +#define MCHP_DMA0_GIRQ_VAL BIT(0) +#define MCHP_DMA1_GIRQ_VAL BIT(1) +#define MCHP_DMA2_GIRQ_VAL BIT(2) +#define MCHP_DMA3_GIRQ_VAL BIT(3) +#define MCHP_DMA4_GIRQ_VAL BIT(4) +#define MCHP_DMA5_GIRQ_VAL BIT(5) +#define MCHP_DMA6_GIRQ_VAL BIT(6) +#define MCHP_DMA7_GIRQ_VAL BIT(7) +#define MCHP_DMA8_GIRQ_VAL BIT(8) +#define MCHP_DMA9_GIRQ_VAL BIT(9) +#define MCHP_DMA10_GIRQ_VAL BIT(10) +#define MCHP_DMA11_GIRQ_VAL BIT(11) +#define MCHP_DMA12_GIRQ_VAL BIT(12) +#define MCHP_DMA13_GIRQ_VAL BIT(13) +#define MCHP_DMA14_GIRQ_VAL BIT(14) +#define MCHP_DMA15_GIRQ_VAL BIT(15) + +/* Device Numbers for Channel Control Reg Device Number Field */ +#define MCHP_DMA_DEVNUM_SMB0_SLV 0ul +#define MCHP_DMA_DEVNUM_SMB0_MTR 1ul +#define MCHP_DMA_DEVNUM_SMB1_SLV 2ul +#define MCHP_DMA_DEVNUM_SMB1_MTR 3ul +#define MCHP_DMA_DEVNUM_SMB2_SLV 4ul +#define MCHP_DMA_DEVNUM_SMB2_MTR 5ul +#define MCHP_DMA_DEVNUM_SMB3_SLV 6ul +#define MCHP_DMA_DEVNUM_SMB3_MTR 7ul +#define MCHP_DMA_DEVNUM_SMB4_SLV 8ul +#define MCHP_DMA_DEVNUM_SMB4_RX 9ul +#define MCHP_DMA_DEVNUM_QMSPI_TX 10ul +#define MCHP_DMA_DEVNUM_QMSPI_RX 11ul +#define MCHP_DMA_DEVNUM_GPSPI_0_TX 12ul +#define MCHP_DMA_DEVNUM_GPSPI_0_RX 13ul +#define MCHP_DMA_DEVNUM_GPSPI_1_TX 14ul +#define MCHP_DMA_DEVNUM_GPSPI_1_RX 15ul +#define MCHP_DMA_DEVNUM_MAX 16ul + +#define MCHP_DMA_CHAN_REG_BLEN 0x40ul + +/* DMA Block Layout + * DMA Main registers start at block base + * Three registers located at word boundaries (0, 4, 8) + * Each channel starts at base + ((channel_number + 1) * DMA_CHAN_REG_BLEN) + * DMA Main @ base + * DMA Channel 0 @ base + DMA_CHAN_REG_BLEN + * DMA Channel 1 @ base + (2 * DMA_CHAN_REG_BLEN) + * + */ + +/* DMA Main Registers */ +#define MCHP_DMAM_CTRL_OFS 0x00ul +#define MCHP_DMAM_PKT_RO_OFS 0x04ul +#define MCHP_DMAM_FSM_RO_OFS 0x08ul + +#define MCHP_DMAM_CTRL_OFFSET 0x00ul +#define MCHP_DMAM_CTRL_MASK 0x03UL +#define MCHP_DMAM_CTRL_ENABLE BIT(0) +#define MCHP_DMAM_CTRL_SOFT_RESET BIT(1) + +/* DMA Main Register Access */ +#define MCHP_DMAM_CTRL() \ + REG8_OFS(MCHP_DMA_BLOCK_BASE_ADDR, MCHP_DMAM_CTRL_OFS) + +#define MCHP_DMAM_PKT_RO() \ + REG32_OFS(MCHP_DMA_BLOCK_BASE_ADDR, MCHP_DMAM_PKT_RO_OFS) + +#define MCHP_DMAM_FSM_RO() \ + REG32_OFS(MCHP_DMA_BLOCK_BASE_ADDR, MCHP_DMAM_FSM_RO_OFS) + +/* DMA channel register offsets */ +#define MCHP_DMA_ACTV_OFS 0x00ul +#define MCHP_DMA_MSTART_OFS 0x04ul +#define MCHP_DMA_MEND_OFS 0x08ul +#define MCHP_DMA_DSTART_OFS 0x0Cul +#define MCHP_DMA_CTRL_OFS 0x10ul +#define MCHP_DMA_ISTS_OFS 0x14ul +#define MCHP_DMA_IEN_OFS 0x18ul +#define MCHP_DMA_FSM_RO_OFS 0x1Cul +/* Channels 0 and 1 include optional ALU */ +#define MCHP_DMA_ALU_CTRL_OFS 0x20ul +#define MCHP_DMA_ALU_DATA_OFS 0x24ul +#define MCHP_DMA_ALU_STS_RO_OFS 0x28ul + +/* DMA Channel register addresses */ +#define MCHP_DMA_ACTV_ADDR(ch) \ + (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_ACTV_OFS)) + +#define MCHP_DMA_MSTART_ADDR(ch) \ + (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_MSTART_OFS)) + +#define MCHP_DMA_MEND_ADDR(ch) \ + (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_MEND_OFS)) + +#define MCHP_DMA_DSTART_ADDR(ch) \ + (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_DSTART_OFS)) + +#define MCHP_DMA_CTRL_ADDR(ch) \ + (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_CTRL_OFS)) + +#define MCHP_DMA_ISTS_ADDR(ch) \ + (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_ISTS_OFS)) + +#define MCHP_DMA_IEND_ADDR(ch) \ + (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_IEN_OFS)) + +#define MCHP_DMA_FSM_ADDR(ch) \ + (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_FSM_RO_OFS)) + +/* Channels 0 and 1 include optional ALU */ +#define MCHP_DMA_ALU_CTRL_ADDR(ch) \ + (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_ALU_CTRL_OFS)) + +#define MCHP_DMA_ALU_DATA_ADDR(ch) \ + (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_ALU_DATA_OFS)) + +#define MCHP_DMA_ALU_STS_RO_ADDR(ch) \ + (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_ALU_STS_RO_OFS)) + +/* + * DMA Channel Register Access + * ch = channel ID: 0 <= ch < MCHP_NUM_DMA_CHANNELS + */ +#define MCHP_DMA_ACTV(ch) \ + REG8_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_ACTV_OFS) + +#define MCHP_DMA_MSTART(ch) \ + REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_MSTART_OFS) + +#define MCHP_DMA_MEND(ch) \ + REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_MEND_OFS) + +#define MCHP_DMA_DSTART(ch) \ + REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_DSTART_OFS) + +#define MCHP_DMA_CTRL(ch) \ + REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_CTRL_OFS) + +#define MCHP_DMA_ISTS(ch) \ + REG8_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_ISTS_OFS) + +#define MCHP_DMA_IEN(ch) \ + REG8_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_IEN_OFS) + +#define MCHP_DMA_FSM(ch) \ + REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_FSM_RO_OFS) + +#define MCHP_DMA_ALU_EN(ch) \ + REG8_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_ALU_CTRL_OFS) + +#define MCHP_DMA_ALU_DATA(ch) \ + REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_ALU_DATA_OFS) + +#define MCHP_DMA_ALU_STS_RO(ch) \ + REG8_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_ALU_STS_RO_OFS) + +/* + * DMA Channel Register Access by base address + * chba = channel base address (start of channel registers) + */ +#define MCHP_DMA_ACTV_BA(chba) \ + REG8_OFS(chba, MCHP_DMA_ACTV_OFS) + +#define MCHP_DMA_MSTART_BA(chba) \ + REG32_OFS(chba, MCHP_DMA_MSTART_OFS) + +#define MCHP_DMA_MEND_BA(chba) \ + REG32_OFS(chba, MCHP_DMA_MEND_OFS) + +#define MCHP_DMA_DSTART_BA(chba) \ + REG32_OFS(chba, MCHP_DMA_DSTART_OFS) + +#define MCHP_DMA_CTRL_BA(chba) \ + REG32_OFS(chba, MCHP_DMA_CTRL_OFS) + +#define MCHP_DMA_ISTS_BA(chba) \ + REG8_OFS(chba, MCHP_DMA_ISTS_OFS) + +#define MCHP_DMA_IEN_BA(chba) \ + REG8_OFS(chba, MCHP_DMA_IEN_OFS) + +#define MCHP_DMA_FSM_BA(chba) \ + REG32_OFS(chba, MCHP_DMA_FSM_RO_OFS) + +#define MCHP_DMA_ALU_EN_BA(chba) \ + REG8_OFS(chba, MCHP_DMA_ALU_CTRL_OFS) + +#define MCHP_DMA_ALU_DATA_BA(chba) \ + REG32_OFS(chba, MCHP_DMA_ALU_DATA_OFS) + +#define MCHP_DMA_ALU_STS_RO_BA(chba) \ + REG8_OFS(chba, MCHP_DMA_ALU_STS_RO_OFS) + +/* Channel Activate, Offset 0x00, R/W */ +#define MCHP_DMA_ACTV_REG_MASK 0x01ul +#define MCHP_DMA_ACTV_VAL (1UL << 0) + +/* Target (destination) Start Memory Address, Offset 0x04 */ +#define MCHP_DMA_MSTART_REG_MASK 0xFFFFFFFFul + +/* Target (destination) End Memory Address, Offset 0x08 */ +#define MCHP_DMA_MEND_REG_MASK 0xFFFFFFFFul + +/* Source (device) Address, Offset 0x0C */ +#define MCHP_DMA_DSTART_REG_MASK 0xFFFFFFFFul + +/* Control, Offset 0x10 */ +#define MCHP_DMA_C_REG_MASK 0x037FFF3Ful +#define MCHP_DMA_C_RUN BIT(0) +#define MCHP_DMA_C_REQ_STS_RO BIT(1) +#define MCHP_DMA_C_DONE_STS_RO BIT(2) +#define MCHP_DMA_C_CHAN_STS_MASK SHLU32(3, 3) +#define MCHP_DMA_C_BUSY_STS_POS 5u +#define MCHP_DMA_C_BUSY_STS BIT(5) +#define MCHP_DMA_C_DIR_POS 8u +#define MCHP_DMA_C_DEV2MEM 0UL +#define MCHP_DMA_C_MEM2DEV BIT(8) +#define MCHP_DMA_C_DEV_NUM_POS 9u +#define MCHP_DMA_C_DEV_NUM_MASK0 0x7Ful +#define MCHP_DMA_C_DEV_NUM_MASK SHLU32(0x7F, 9) +#define MCHP_DMA_C_NO_INCR_MEM 0UL +#define MCHP_DMA_C_INCR_MEM BIT(16) +#define MCHP_DMA_C_NO_INCR_DEV 0UL +#define MCHP_DMA_C_INCR_DEV BIT(17) +#define MCHP_DMA_C_LOCK_CHAN BIT(18) +#define MCHP_DMA_C_DIS_HWFLC BIT(19) +#define MCHP_DMA_C_XFRU_POS 20u +#define MCHP_DMA_C_XFRU_MASK0 0x07ul +#define MCHP_DMA_C_XFRU_MASK SHLU32(0x07, 20) +#define MCHP_DMA_C_XFRU_1B SHLU32(1, MCHP_DMA_C_XFRU_POS) +#define MCHP_DMA_C_XFRU_2B SHLU32(2, MCHP_DMA_C_XFRU_POS) +#define MCHP_DMA_C_XFRU_4B SHLU32(4, MCHP_DMA_C_XFRU_POS) +#define MCHP_DMA_C_XFER_GO BIT(24) +#define MCHP_DMA_C_XFER_ABORT BIT(25) +/* combine direction and device number fields */ +#define MCHP_DMA_C_DEVDIR_POS 8u +#define MCHP_DMA_C_DEVDIR_MASK0 0xFFul +#define MCHP_DMA_C_DEVDIR_MASK (0xFFul << 8) + +/* Channel Interrupt Status, Offset 0x14 */ +#define MCHP_DMA_STS_REG_MASK 0x0Ful +#define MCHP_DMA_STS_BUS_ERR BIT(0) +#define MCHP_DMA_STS_FLOW_CTRL_ERR BIT(1) +#define MCHP_DMA_STS_DONE BIT(2) +#define MCHP_DMA_STS_DEV_TERM BIT(3) +#define MCHP_DMA_STS_ALL 0x0Ful + +/* Channel Interrupt Enable, Offset 0x18 */ +#define MCHP_DMA_IEN_REG_MASK 0x0Ful +#define MCHP_DMA_IEN_BUS_ERR BIT(0) +#define MCHP_DMA_IEN_FLOW_CTRL_ERR BIT(1) +#define MCHP_DMA_IEN_DONE BIT(2) +#define MCHP_DMA_IEN_DEV_TERM BIT(3) +#define MCHP_DMA_IEN_ALL 0x0Ful + +/* Channel FSM (read-only), Offset 0x1C */ +#define MCHP_DMA_FSM_REG_MASK 0x0FFFFul + +/* + * DMA Block with optional ALU includes four extra registers. + * Channel's total register allocation is 0x40 + */ + +/* ALU Control, Offset 0x20 */ +#define MCHP_DMA_ALU_CTRL_MASK 0x03ul +#define MCHP_DMA_ALU_ENABLE_POS 0 +#define MCHP_DMA_ALU_MASK BIT(MCHP_DMA_ALU_ENABLE_POS) +#define MCHP_DMA_ALU_DISABLE 0ul +#define MCHP_DMA_ALU_ENABLE BIT(MCHP_DMA_ALU_ENABLE_POS) +#define MCHP_DMA_ALU_POST_XFER_EN_POS 1u +#define MCHP_DMA_ALU_POST_XFER_EN_MASK BIT(MCHP_DMA_ALU_POST_XFER_EN_POS) +#define MCHP_DMA_ALU_POST_XFER_DIS 0ul +#define MCHP_DMA_ALU_POST_XFER_EN BIT(MCHP_DMA_ALU_POST_XFER_EN_POS) + +/* ALU Data, Offset 0x24 */ +#define MCHP_DMA_ALU_DATA_MASK 0xFFFFFFFFul + +/* ALU Status, Offset 0x28 Read-Only */ +#define MCHP_DMA_ALU_STS_MASK 0x0Ful +#define MCHP_DMA_ALU_STS_DONE_POS 0u +#define MCHP_DMA_ALU_STS_RUN_POS 1u +#define MCHP_DMA_ALU_STS_XFR_DONE_POS 2u +#define MCHP_DMA_ALU_STS_DATA_RDY_POS 3u +#define MCHP_DMA_ALU_STS_DONE BIT(MCHP_DMA_ALU_STS_DONE_POS) +#define MCHP_DMA_ALU_STS_RUN BIT(MCHP_DMA_ALU_STS_RUN_POS) +#define MCHP_DMA_ALU_STS_XFR_DONE BIT(MCHP_DMA_ALU_STS_XFR_DONE_POS) +#define MCHP_DMA_ALU_STS_DATA_RDY BIT((MCHP_DMA_ALU_STS_DATA_RDY_POS) + +/* ALU Test, Offset 0x2C Reserved */ +#define MCHP_DMA_ALU_TEST_MASK 0xFFFFFFFFul + +/* + * Channel 0 has ALU for CRC32 + * Channel 1 has ALU for memory fill + * Channels 2-11 do not implement an ALU + */ +#define MCHP_DMA_NUM_CHAN 16u +#define MCHP_DMA_CHAN_SPACING 0x40ul +#define MCHP_DMA_CHAN_SPACING_POF2 6u + +#define MCHP_DMA_WCRC_CHAN_ID 0u +#define MCHP_DMA_WMF_CHAN_ID 1u +#define MCHP_MAX_DMA_CHAN 16u +#define MCHP_NUM_DMA_CHAN_NO_ALU ((MCHP_MAX_DMA_CHAN) -2) + +#endif /* #ifndef _COMPONENT_DMA_H */ +/* end dma.h */ +/** @} + */ diff --git a/mec/mec172x/component/ecia.h b/mec/mec172x/component/ecia.h new file mode 100644 index 0000000..2abccd2 --- /dev/null +++ b/mec/mec172x/component/ecia.h @@ -0,0 +1,841 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file ecia.h + * MEC172x EC Interrupt Aggregator Subsystem definitions + */ +/** @defgroup MEC172x Peripherals ECIA + */ + +#ifndef _COMPONENT_ECIA_H +#define _COMPONENT_ECIA_H + +#include +#include + +#include +#include + +#define MCHP_ECIA_ADDR 0x4000E000ul +#define MCHP_FIRST_GIRQ 8u +#define MCHP_LAST_GIRQ 26u + +#define MCHP_ECIA_GIRQ_NO_NVIC 22u + +#define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \ + BIT(12) | BIT(24) | BIT(25) | BIT(26)) + +#define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \ + BIT(17) | BIT(18) | BIT(19) | BIT(20) | \ + BIT(21) | BIT(23)) + +#define MCHP_ECIA_ALL_BITMAP 0x07FFFF00ul + +/* MEC172x implements 8 priority levels. ARM NVIC 0 = highest priority */ +#define MCHP_NVIC_NUM_PRI_BITS 3u +#define MCHP_NVIC_PRI_LO_VAL 0x07u + +/* + * ARM Cortex-M4 NVIC registers + * External sources are grouped by 32-bit registers. + * MEC172x has 181 external sources requiring 6 32-bit registers. + */ +#define MCHP_NUM_NVIC_REGS 6u +#define MCHP_NVIC_SET_EN_BASE 0xE000E100ul +#define MCHP_NVIC_CLR_EN_BASE 0xE000E180ul +#define MCHP_NVIC_SET_PEND_BASE 0xE000E200ul +#define MCHP_NVIC_CLR_PEND_BASE 0xE000E280ul +#define MCHP_NVIC_ACTIVE_BASE 0xE000E800ul +#define MCHP_NVIC_PRI_BASE 0xE000E400ul + +/* 0 <= n < MCHP_NUM_NVIC_REGS */ +#define MCHP_NVIC_SET_EN(n) \ + REG32(MCHP_NVIC_SET_EN_BASE + ((uintptr_t)(n) * 4U)) + +#define MCHP_NVIC_CLR_EN(n) \ + REG32(MCHP_NVIC_CLR_EN_BASE + ((uintptr_t)(n) * 4U)) + +#define MCHP_NVIC_SET_PEND(n) \ + REG32(MCHP_NVIC_SET_PEND_BASE + ((uintptr_t)(n) * 4U)) + +#define MCHP_NVIC_CLR_PEND(n) \ + REG32(MCHP_NVIC_CLR_PEND_BASE + ((uintptr_t)(n) * 4U)) + +/* + * ECIA registers + * Implements 19 GIRQ's. GIRQ's aggregated interrupts source into one + * set of registers. + * For historical reason GIRQ's are numbered starting at 8 in the documentation. + * This numbering only affects the ECIA BLOCK_EN_SET, BLOCK_EN_CLR, and + * BLOCK_ACTIVE registers: GIRQ8 is bit[8], ..., GIRQ26 is bit[26]. + * + * Each GIRQ is composed of 5 32-bit registers. + * +00h = GIRQ08 Source containing RW/1C status bits + * +04h = Enable Set write 1 to bit(s) to enable the corresponding source(s) + * +08h = Read-Only Result = Source AND Enable-Set + * +0Ch = Enable Clear write 1 to bit(s) to disable the corresponding source(s) + * +14h = Reserved(unused). + * +18h = GIRQ09 Source + * ... + * There are three other registers at offset 0x200, 0x204, and 0x208 + * 0x200: BLOCK_EN_SET bit == 1 allows bit-wise OR of all GIRQn source + * bits to be connected to NVIC GIRQn input. + * bit[8]=GIRQ8, bit[9]=GIRQ9, ..., bit[26]=GIRQ26 + * 0x204: BLOCK_EN_CLR bit == 1 disconnects bit-wise OR of GIRQn source + * bits from NVIC GIRQn input. + * 0x208: BLOCK_ACTIVE (read-only) + * bit[8]=GIRQ8 has at least one source bit enabled and active. + * ... + * bit[26]=GIRQ26 has at least one source bit enabled and active. + * + */ + +/* zero based logical numbering */ +#define MCHP_GIRQ08_ZID 0u +#define MCHP_GIRQ09_ZID 1u +#define MCHP_GIRQ10_ZID 2u +#define MCHP_GIRQ11_ZID 3u +#define MCHP_GIRQ12_ZID 4u +#define MCHP_GIRQ13_ZID 5u +#define MCHP_GIRQ14_ZID 6u +#define MCHP_GIRQ15_ZID 7u +#define MCHP_GIRQ16_ZID 8u +#define MCHP_GIRQ17_ZID 9u +#define MCHP_GIRQ18_ZID 10u +#define MCHP_GIRQ19_ZID 11u +#define MCHP_GIRQ20_ZID 12u /* Nothing in datasheet */ +#define MCHP_GIRQ21_ZID 13u + +#define MCHP_GIRQ23_ZID 14u /* Adjust per datasheet */ +#define MCHP_GIRQ24_ZID 15u +#define MCHP_GIRQ25_ZID 16u +#define MCHP_GIRQ26_ZID 17u +#define MCHP_GIRQ_ZID_MAX 18u + +#define MCHP_ECIA_BLK_ENSET_OFS 0x200ul +#define MCHP_ECIA_BLK_ENCLR_OFS 0x204ul +#define MCHP_ECIA_BLK_ACTIVE_OFS 0x208ul + +#define MCHP_GIRQ_BLK_ENSET_ADDR \ + (MCHP_ECIA_ADDR + MCHP_ECIA_BLK_ENSET_OFS) + +#define MCHP_GIRQ_BLK_ENCLR_ADDR \ + (MCHP_ECIA_ADDR + MCHP_ECIA_BLK_ENCLR_OFS) + +#define MCHP_GIRQ_BLK_ACTIVE_ADDR \ + (MCHP_ECIA_ADDR + MCHP_ECIA_BLK_ACTIVE_OFS) + +/* 8 <= n <= 26 */ +#define MCHP_GIRQ_TO_AGGR_NVIC(n) (((n) < 23) ? ((n) - 8) : ((n) - 9)) + +/* 8 <= n <= 26 */ +#define MCHP_GIRQ_SRC_ADDR(n) \ + ((MCHP_ECIA_ADDR + 0x00ul) + (((uint32_t)(n) - 8ul) * 0x14ul)) + +#define MCHP_GIRQ_ENSET_ADDR(n) \ + ((MCHP_ECIA_ADDR + 0x04ul) + (((uint32_t)(n) - 8ul) * 0x14ul)) + +#define MCHP_GIRQ_RESULT_ADDR(n) \ + ((MCHP_ECIA_ADDR + 0x08ul) + (((uint32_t)(n) - 8ul) * 0x14ul)) + +#define MCHP_GIRQ_ENCLR_ADDR(n) \ + ((MCHP_ECIA_ADDR + 0x0Cul) + (((uint32_t)(n) - 8ul) * 0x14ul)) + +#define MCHP_GIRQ08_SRC_ADDR MCHP_GIRQ_SRC_ADDR(8) +#define MCHP_GIRQ08_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(8) +#define MCHP_GIRQ08_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(8) +#define MCHP_GIRQ08_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(8) + +#define MCHP_GIRQ09_SRC_ADDR MCHP_GIRQ_SRC_ADDR(9) +#define MCHP_GIRQ09_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(9) +#define MCHP_GIRQ09_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(9) +#define MCHP_GIRQ09_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(9) + +#define MCHP_GIRQ10_SRC_ADDR MCHP_GIRQ_SRC_ADDR(10) +#define MCHP_GIRQ10_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(10) +#define MCHP_GIRQ10_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(10) +#define MCHP_GIRQ10_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(10) + +#define MCHP_GIRQ11_SRC_ADDR MCHP_GIRQ_SRC_ADDR(11) +#define MCHP_GIRQ11_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(11) +#define MCHP_GIRQ11_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(11) +#define MCHP_GIRQ11_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(11) + +#define MCHP_GIRQ12_SRC_ADDR MCHP_GIRQ_SRC_ADDR(12) +#define MCHP_GIRQ12_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(12) +#define MCHP_GIRQ12_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(12) +#define MCHP_GIRQ12_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(12) + +#define MCHP_GIRQ13_SRC_ADDR MCHP_GIRQ_SRC_ADDR(13) +#define MCHP_GIRQ13_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(13) +#define MCHP_GIRQ13_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(13) +#define MCHP_GIRQ13_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(13) + +#define MCHP_GIRQ14_SRC_ADDR MCHP_GIRQ_SRC_ADDR(14) +#define MCHP_GIRQ14_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(14) +#define MCHP_GIRQ14_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(14) +#define MCHP_GIRQ14_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(14) + +#define MCHP_GIRQ15_SRC_ADDR MCHP_GIRQ_SRC_ADDR(15) +#define MCHP_GIRQ15_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(15) +#define MCHP_GIRQ15_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(15) +#define MCHP_GIRQ15_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(15) + +#define MCHP_GIRQ16_SRC_ADDR MCHP_GIRQ_SRC_ADDR(16) +#define MCHP_GIRQ16_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(16) +#define MCHP_GIRQ16_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(16) +#define MCHP_GIRQ16_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(16) + +#define MCHP_GIRQ17_SRC_ADDR MCHP_GIRQ_SRC_ADDR(17) +#define MCHP_GIRQ17_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(17) +#define MCHP_GIRQ17_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(17) +#define MCHP_GIRQ17_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(17) + +#define MCHP_GIRQ18_SRC_ADDR MCHP_GIRQ_SRC_ADDR(18) +#define MCHP_GIRQ18_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(18) +#define MCHP_GIRQ18_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(18) +#define MCHP_GIRQ18_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(18) + +#define MCHP_GIRQ19_SRC_ADDR MCHP_GIRQ_SRC_ADDR(19) +#define MCHP_GIRQ19_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(19) +#define MCHP_GIRQ19_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(19) +#define MCHP_GIRQ19_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(19) + +#define MCHP_GIRQ20_SRC_ADDR MCHP_GIRQ_SRC_ADDR(20) +#define MCHP_GIRQ20_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(20) +#define MCHP_GIRQ20_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(20) +#define MCHP_GIRQ20_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(20) + +#define MCHP_GIRQ21_SRC_ADDR MCHP_GIRQ_SRC_ADDR(21) +#define MCHP_GIRQ21_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(21) +#define MCHP_GIRQ21_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(21) +#define MCHP_GIRQ21_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(21) + +#define MCHP_GIRQ22_SRC_ADDR MCHP_GIRQ_SRC_ADDR(22) +#define MCHP_GIRQ22_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(22) +#define MCHP_GIRQ22_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(22) +#define MCHP_GIRQ22_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(22) + +#define MCHP_GIRQ23_SRC_ADDR MCHP_GIRQ_SRC_ADDR(23) +#define MCHP_GIRQ23_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(23) +#define MCHP_GIRQ23_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(23) +#define MCHP_GIRQ23_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(23) + +#define MCHP_GIRQ24_SRC_ADDR MCHP_GIRQ_SRC_ADDR(24) +#define MCHP_GIRQ24_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(24) +#define MCHP_GIRQ24_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(24) +#define MCHP_GIRQ24_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(24) + +#define MCHP_GIRQ25_SRC_ADDR MCHP_GIRQ_SRC_ADDR(25) +#define MCHP_GIRQ25_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(25) +#define MCHP_GIRQ25_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(25) +#define MCHP_GIRQ25_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(25) + +#define MCHP_GIRQ26_SRC_ADDR MCHP_GIRQ_SRC_ADDR(26) +#define MCHP_GIRQ26_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(26) +#define MCHP_GIRQ26_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(26) +#define MCHP_GIRQ26_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(26) + +/* + * Register access + */ +#define MCHP_GIRQ_BLK_ENSET() \ + REG32(MCHP_GIRQ_BLK_ENSET_ADDR) + +#define MCHP_GIRQ_BLK_ENCLR() \ + REG32(MCHP_GIRQ_BLK_ENCLR_ADDR) + +#define MCHP_GIRQ_BLK_ACTIVE() \ + REG32(MCHP_GIRQ_BLK_ACTIVE_ADDR) + +/* + * Set/clear GIRQ Block Enable + * Check if block is active + * 8 <= n <= 26 corresponding to GIRQ08, GIRQ09, ..., GIRQ26 + */ +#define MCHP_GIRQ_BLK_SETEN(n) \ + REG32(MCHP_GIRQ_BLK_ENSET_ADDR) = BIT(n) + +#define MCHP_GIRQ_BLK_CLREN(n) \ + REG32(MCHP_GIRQ_BLK_ENCLR_ADDR) = BIT(n) + +#define MCHP_GIRQ_BLK_IS_ACTIVE(n) \ + ((REG32(MCHP_GIRQ_BLK_ACTIVE_ADDR) & BIT(n)) != 0ul) + +/* 8 <= n <= 26 corresponding to GIRQ08, GIRQ09, ..., GIRQ26 */ +#define MCHP_GIRQ_SRC(n) REG32(MCHP_GIRQ_SRC_ADDR(n)) + +#define MCHP_GIRQ_ENSET(n) REG32(MCHP_GIRQ_ENSET_ADDR(n)) + +#define MCHP_GIRQ_RESULT(n) REG32(MCHP_GIRQ_RESULT_ADDR(n)) +#define MCHP_GIRQ_ENCLR(n) REG32(MCHP_GIRQ_ENCLR_ADDR(n)) + +/* + * 8 <= n <= 26 corresponding to GIRQ08, GIRQ09, ..., GIRQ26 + * 0 <= pos <= 31 the bit position of the peripheral interrupt source. + */ +#define MCHP_GIRQ_SRC_CLR(n, pos) \ + REG32(MCHP_GIRQ_SRC_ADDR(n)) = BIT(pos) + +#define MCHP_GIRQ_SET_EN(n, pos) \ + REG32(MCHP_GIRQ_ENSET_ADDR(n)) = BIT(pos) + +#define MCHP_GIRQ_CLR_EN(n, pos) \ + REG32(MCHP_GIRQ_ENCLR_ADDR(n)) = BIT(pos) + +#define MCHP_GIRQ_IS_RESULT(n, pos) \ + ((REG32(MCHP_GIRQ_RESULT_ADDR(n)) & BIT(pos)) != 0ul) + +/* =========================================================================*/ +/* ================ ECIA ================ */ +/* =========================================================================*/ + +enum MCHP_GIRQ_IDS { + MCHP_GIRQ08_ID = 8, + MCHP_GIRQ09_ID, + MCHP_GIRQ10_ID, + MCHP_GIRQ11_ID, + MCHP_GIRQ12_ID, + MCHP_GIRQ13_ID, + MCHP_GIRQ14_ID, + MCHP_GIRQ15_ID, + MCHP_GIRQ16_ID, + MCHP_GIRQ17_ID, + MCHP_GIRQ18_ID, + MCHP_GIRQ19_ID, + MCHP_GIRQ20_ID, + MCHP_GIRQ21_ID, + MCHP_GIRQ22_ID, + MCHP_GIRQ23_ID, + MCHP_GIRQ24_ID, + MCHP_GIRQ25_ID, + MCHP_GIRQ26_ID, + MCHP_GIRQ_ID_MAX, +}; + +/* zero based index into ECIA_Type GIRQ[] */ +enum MCHP_GIRQ_INDEX { + GIRQ08_IDX = 0, + GIRQ09_IDX, + GIRQ10_IDX, + GIRQ11_IDX, + GIRQ12_IDX, + GIRQ13_IDX, + GIRQ14_IDX, + GIRQ15_IDX, + GIRQ16_IDX, + GIRQ17_IDX, + GIRQ18_IDX, + GIRQ19_IDX, + GIRQ20_IDX, + GIRQ21_IDX, + GIRQ22_IDX, + GIRQ23_IDX, + GIRQ24_IDX, + GIRQ25_IDX, + GIRQ26_IDX, + GIRQ_MAX_IDX +}; + +/* GIRQ08 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_GPIO_0140_GIRQ_BIT BIT(0) +#define MCHP_GPIO_0141_GIRQ_BIT BIT(1) +#define MCHP_GPIO_0142_GIRQ_BIT BIT(2) +#define MCHP_GPIO_0143_GIRQ_BIT BIT(3) +#define MCHP_GPIO_0144_GIRQ_BIT BIT(4) +#define MCHP_GPIO_0145_GIRQ_BIT BIT(5) +#define MCHP_GPIO_0146_GIRQ_BIT BIT(6) +#define MCHP_GPIO_0147_GIRQ_BIT BIT(7) +#define MCHP_GPIO_0150_GIRQ_BIT BIT(8) +#define MCHP_GPIO_0151_GIRQ_BIT BIT(9) +#define MCHP_GPIO_0152_GIRQ_BIT BIT(10) +#define MCHP_GPIO_0153_GIRQ_BIT BIT(11) +#define MCHP_GPIO_0154_GIRQ_BIT BIT(12) +#define MCHP_GPIO_0155_GIRQ_BIT BIT(13) +#define MCHP_GPIO_0156_GIRQ_BIT BIT(14) +#define MCHP_GPIO_0157_GIRQ_BIT BIT(15) +#define MCHP_GPIO_0160_GIRQ_BIT BIT(16) +#define MCHP_GPIO_0161_GIRQ_BIT BIT(17) +#define MCHP_GPIO_0162_GIRQ_BIT BIT(18) +#define MCHP_GPIO_0165_GIRQ_BIT BIT(21) +#define MCHP_GPIO_0166_GIRQ_BIT BIT(22) +#define MCHP_GPIO_0170_GIRQ_BIT BIT(24) +#define MCHP_GPIO_0171_GIRQ_BIT BIT(25) +#define MCHP_GPIO_0172_GIRQ_BIT BIT(26) +#define MCHP_GPIO_0173_GIRQ_BIT BIT(27) +#define MCHP_GPIO_0174_GIRQ_BIT BIT(28) +#define MCHP_GPIO_0175_GIRQ_BIT BIT(29) +#define MCHP_GPIO_0140_0176_GIRQ_MASK 0x3F67FFFFu + +/* GIRQ09 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_GPIO_0100_GIRQ_BIT BIT(0) +#define MCHP_GPIO_0101_GIRQ_BIT BIT(1) +#define MCHP_GPIO_0102_GIRQ_BIT BIT(2) +#define MCHP_GPIO_0103_GIRQ_BIT BIT(3) +#define MCHP_GPIO_0104_GIRQ_BIT BIT(4) +#define MCHP_GPIO_0105_GIRQ_BIT BIT(5) +#define MCHP_GPIO_0106_GIRQ_BIT BIT(6) +#define MCHP_GPIO_0107_GIRQ_BIT BIT(7) +#define MCHP_GPIO_0110_GIRQ_BIT BIT(8) +#define MCHP_GPIO_0111_GIRQ_BIT BIT(9) +#define MCHP_GPIO_0112_GIRQ_BIT BIT(10) +#define MCHP_GPIO_0113_GIRQ_BIT BIT(11) +#define MCHP_GPIO_0114_GIRQ_BIT BIT(12) +#define MCHP_GPIO_0115_GIRQ_BIT BIT(13) +#define MCHP_GPIO_0116_GIRQ_BIT BIT(14) +#define MCHP_GPIO_0117_GIRQ_BIT BIT(15) +#define MCHP_GPIO_0120_GIRQ_BIT BIT(16) +#define MCHP_GPIO_0121_GIRQ_BIT BIT(17) +#define MCHP_GPIO_0122_GIRQ_BIT BIT(18) +#define MCHP_GPIO_0123_GIRQ_BIT BIT(19) +#define MCHP_GPIO_0124_GIRQ_BIT BIT(20) +#define MCHP_GPIO_0125_GIRQ_BIT BIT(21) +#define MCHP_GPIO_0126_GIRQ_BIT BIT(22) +#define MCHP_GPIO_0127_GIRQ_BIT BIT(23) +#define MCHP_GPIO_0130_GIRQ_BIT BIT(24) +#define MCHP_GPIO_0131_GIRQ_BIT BIT(25) +#define MCHP_GPIO_0132_GIRQ_BIT BIT(26) +#define MCHP_GPIO_0133_GIRQ_BIT BIT(27) +#define MCHP_GPIO_0134_GIRQ_BIT BIT(28) +#define MCHP_GPIO_0135_GIRQ_BIT BIT(29) +#define MCHP_GPIO_0100_0136_GIRQ_MASK 0x3FFFFFFFu + +/* GIRQ10 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_GPIO_0040_GIRQ_BIT BIT(0) +#define MCHP_GPIO_0041_GIRQ_BIT BIT(1) +#define MCHP_GPIO_0042_GIRQ_BIT BIT(2) +#define MCHP_GPIO_0043_GIRQ_BIT BIT(3) +#define MCHP_GPIO_0044_GIRQ_BIT BIT(4) +#define MCHP_GPIO_0045_GIRQ_BIT BIT(5) +#define MCHP_GPIO_0046_GIRQ_BIT BIT(6) +#define MCHP_GPIO_0047_GIRQ_BIT BIT(7) +#define MCHP_GPIO_0050_GIRQ_BIT BIT(8) +#define MCHP_GPIO_0051_GIRQ_BIT BIT(9) +#define MCHP_GPIO_0052_GIRQ_BIT BIT(10) +#define MCHP_GPIO_0053_GIRQ_BIT BIT(11) +#define MCHP_GPIO_0054_GIRQ_BIT BIT(12) +#define MCHP_GPIO_0055_GIRQ_BIT BIT(13) +#define MCHP_GPIO_0056_GIRQ_BIT BIT(14) +#define MCHP_GPIO_0057_GIRQ_BIT BIT(15) +#define MCHP_GPIO_0060_GIRQ_BIT BIT(16) +#define MCHP_GPIO_0061_GIRQ_BIT BIT(17) +#define MCHP_GPIO_0062_GIRQ_BIT BIT(18) +#define MCHP_GPIO_0063_GIRQ_BIT BIT(19) +#define MCHP_GPIO_0064_GIRQ_BIT BIT(20) +#define MCHP_GPIO_0065_GIRQ_BIT BIT(21) +#define MCHP_GPIO_0066_GIRQ_BIT BIT(22) +#define MCHP_GPIO_0067_GIRQ_BIT BIT(23) +#define MCHP_GPIO_0070_GIRQ_BIT BIT(24) +#define MCHP_GPIO_0071_GIRQ_BIT BIT(25) +#define MCHP_GPIO_0072_GIRQ_BIT BIT(26) +#define MCHP_GPIO_0073_GIRQ_BIT BIT(27) +#define MCHP_GPIO_0074_GIRQ_BIT BIT(28) +#define MCHP_GPIO_0075_GIRQ_BIT BIT(29) +#define MCHP_GPIO_0076_GIRQ_BIT BIT(30) +#define MCHP_GPIO_0040_0076_GIRQ_MASK 0x7FFFFFFFu + +/* GIRQ11 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_GPIO_0000_GIRQ_BIT BIT(0) +#define MCHP_GPIO_0001_GIRQ_BIT BIT(1) +#define MCHP_GPIO_0002_GIRQ_BIT BIT(2) +#define MCHP_GPIO_0003_GIRQ_BIT BIT(3) +#define MCHP_GPIO_0004_GIRQ_BIT BIT(4) +#define MCHP_GPIO_0005_GIRQ_BIT BIT(5) +#define MCHP_GPIO_0006_GIRQ_BIT BIT(6) +#define MCHP_GPIO_0007_GIRQ_BIT BIT(7) +#define MCHP_GPIO_0010_GIRQ_BIT BIT(8) +#define MCHP_GPIO_0011_GIRQ_BIT BIT(9) +#define MCHP_GPIO_0012_GIRQ_BIT BIT(10) +#define MCHP_GPIO_0013_GIRQ_BIT BIT(11) +#define MCHP_GPIO_0014_GIRQ_BIT BIT(12) +#define MCHP_GPIO_0015_GIRQ_BIT BIT(13) +#define MCHP_GPIO_0016_GIRQ_BIT BIT(14) +#define MCHP_GPIO_0017_GIRQ_BIT BIT(15) +#define MCHP_GPIO_0020_GIRQ_BIT BIT(16) +#define MCHP_GPIO_0021_GIRQ_BIT BIT(17) +#define MCHP_GPIO_0022_GIRQ_BIT BIT(18) +#define MCHP_GPIO_0023_GIRQ_BIT BIT(19) +#define MCHP_GPIO_0024_GIRQ_BIT BIT(20) +#define MCHP_GPIO_0025_GIRQ_BIT BIT(21) +#define MCHP_GPIO_0026_GIRQ_BIT BIT(22) +#define MCHP_GPIO_0027_GIRQ_BIT BIT(23) +#define MCHP_GPIO_0030_GIRQ_BIT BIT(24) +#define MCHP_GPIO_0031_GIRQ_BIT BIT(25) +#define MCHP_GPIO_0032_GIRQ_BIT BIT(26) +#define MCHP_GPIO_0033_GIRQ_BIT BIT(27) +#define MCHP_GPIO_0034_GIRQ_BIT BIT(28) +#define MCHP_GPIO_0035_GIRQ_BIT BIT(29) +#define MCHP_GPIO_0036_GIRQ_BIT BIT(30) +#define MCHP_GPIO_0000_0036_GIRQ_MASK 0x7FFFFFFFu + +/* GIRQ12 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_GPIO_0200_GIRQ_BIT BIT(0) +#define MCHP_GPIO_0201_GIRQ_BIT BIT(1) +#define MCHP_GPIO_0202_GIRQ_BIT BIT(2) +#define MCHP_GPIO_0203_GIRQ_BIT BIT(3) +#define MCHP_GPIO_0204_GIRQ_BIT BIT(4) +#define MCHP_GPIO_0205_GIRQ_BIT BIT(5) +#define MCHP_GPIO_0206_GIRQ_BIT BIT(6) +#define MCHP_GPIO_0207_GIRQ_BIT BIT(7) +#define MCHP_GPIO_0210_GIRQ_BIT BIT(8) +#define MCHP_GPIO_0211_GIRQ_BIT BIT(9) +#define MCHP_GPIO_0212_GIRQ_BIT BIT(10) +#define MCHP_GPIO_0213_GIRQ_BIT BIT(11) +#define MCHP_GPIO_0214_GIRQ_BIT BIT(12) +#define MCHP_GPIO_0215_GIRQ_BIT BIT(13) +#define MCHP_GPIO_0216_GIRQ_BIT BIT(14) +#define MCHP_GPIO_0217_GIRQ_BIT BIT(15) +#define MCHP_GPIO_0220_GIRQ_BIT BIT(16) +#define MCHP_GPIO_0221_GIRQ_BIT BIT(17) +#define MCHP_GPIO_0222_GIRQ_BIT BIT(18) +#define MCHP_GPIO_0223_GIRQ_BIT BIT(19) +#define MCHP_GPIO_0224_GIRQ_BIT BIT(20) +#define MCHP_GPIO_0225_GIRQ_BIT BIT(21) +#define MCHP_GPIO_0226_GIRQ_BIT BIT(22) +#define MCHP_GPIO_0227_GIRQ_BIT BIT(23) +#define MCHP_GPIO_0230_GIRQ_BIT BIT(24) +#define MCHP_GPIO_0231_GIRQ_BIT BIT(25) +#define MCHP_GPIO_0232_GIRQ_BIT BIT(26) +#define MCHP_GPIO_0233_GIRQ_BIT BIT(27) +#define MCHP_GPIO_0234_GIRQ_BIT BIT(28) +#define MCHP_GPIO_0235_GIRQ_BIT BIT(29) +#define MCHP_GPIO_0236_GIRQ_BIT BIT(30) +#define MCHP_GPIO_0200_0236_GIRQ_MASK 0x7FFFFFFFu + +/* GIRQ13 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_I2C_SMB_0_GIRQ_BIT BIT(0) +#define MCHP_I2C_SMB_1_GIRQ_BIT BIT(1) +#define MCHP_I2C_SMB_2_GIRQ_BIT BIT(2) +#define MCHP_I2C_SMB_3_GIRQ_BIT BIT(3) +#define MCHP_I2C_SMB_4_GIRQ_BIT BIT(4) +#define MCHP_SMB_I2C_GIRQ_MASK 0x1Fu + +/* GIRQ14 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_DMA_CH00_GIRQ_BIT BIT(0) +#define MCHP_DMA_CH01_GIRQ_BIT BIT(1) +#define MCHP_DMA_CH02_GIRQ_BIT BIT(2) +#define MCHP_DMA_CH03_GIRQ_BIT BIT(3) +#define MCHP_DMA_CH04_GIRQ_BIT BIT(4) +#define MCHP_DMA_CH05_GIRQ_BIT BIT(5) +#define MCHP_DMA_CH06_GIRQ_BIT BIT(6) +#define MCHP_DMA_CH07_GIRQ_BIT BIT(7) +#define MCHP_DMA_CH08_GIRQ_BIT BIT(8) +#define MCHP_DMA_CH09_GIRQ_BIT BIT(9) +#define MCHP_DMA_CH10_GIRQ_BIT BIT(10) +#define MCHP_DMA_CH11_GIRQ_BIT BIT(11) +#define MCHP_DMA_CH12_GIRQ_BIT BIT(12) +#define MCHP_DMA_CH13_GIRQ_BIT BIT(13) +#define MCHP_DMA_CH14_GIRQ_BIT BIT(14) +#define MCHP_DMA_CH15_GIRQ_BIT BIT(15) +#define MCHP_DMA_GIRQ_MASK 0xFFFFu + +/* GIRQ15 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_UART_0_GIRQ_BIT BIT(0) +#define MCHP_UART_1_GIRQ_BIT BIT(1) +#define MCHP_EMI_0_GIRQ_BIT BIT(2) +#define MCHP_EMI_1_GIRQ_BIT BIT(3) +#define MCHP_EMI_2_GIRQ_BIT BIT(4) +#define MCHP_ACPI_EC_0_IBF_GIRQ_BIT BIT(5) +#define MCHP_ACPI_EC_0_OBE_GIRQ_BIT BIT(6) +#define MCHP_ACPI_EC_1_IBF_GIRQ_BIT BIT(7) +#define MCHP_ACPI_EC_1_OBE_GIRQ_BIT BIT(8) +#define MCHP_ACPI_EC_2_IBF_GIRQ_BIT BIT(9) +#define MCHP_ACPI_EC_2_OBE_GIRQ_BIT BIT(10) +#define MCHP_ACPI_EC_3_IBF_GIRQ_BIT BIT(11) +#define MCHP_ACPI_EC_3_OBE_GIRQ_BIT BIT(12) +#define MCHP_ACPI_EC_4_IBF_GIRQ_BIT BIT(13) +#define MCHP_ACPI_EC_4_OBE_GIRQ_BIT BIT(14) +#define MCHP_ACPI_PM1_CTL_GIRQ_BIT BIT(15) +#define MCHP_ACPI_PM1_EN_GIRQ_BIT BIT(16) +#define MCHP_ACPI_PM1_STS_GIRQ_BIT BIT(17) +#define MCHP_KBC_OBE_GIRQ_BIT BIT(18) +#define MCHP_KBC_IBF_GIRQ_BIT BIT(19) +#define MCHP_MBOX_0_GIRQ_BIT BIT(20) +#define MCHP_BDP_0_GIRQ_BIT BIT(22) +/* Legacy name of previous HW block */ +#define MCHP_PORT80_DEBUG0_GIRQ_VAL BIT(22) +/* Masks for blocks with multiple instances or sources */ +#define MCHP_UART_GIRQ_MASK 0x03u +#define MCHP_UART_EMI_GIRQ_MASK 0x1Cu +#define MCHP_ACPI_EC_GIRQ_MASK 0x07FE0u +#define MCHP_ACPI_PM1_GIRQ_MASK 0x38000u +#define MCHP_KBC_GIRQ_MASK 0xC0000u +#define MCHP_HOST_PERIPH_GIRQ_MASK 0x5FFFFFu + +/* GIRQ16 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_PK_GIRQ_BIT BIT(0) +#define MCHP_RNG_GIRQ_BIT BIT(2) +#define MCHP_AESH_GIRQ_BIT BIT(3) +#define MCHP_CRYPTO_GIRQ_MASK 0x0Du + +/* GIRQ17 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_PECI_GIRQ_BIT BIT(0) +#define MCHP_TACH_0_GIRQ_BIT BIT(1) +#define MCHP_TACH_1_GIRQ_BIT BIT(2) +#define MCHP_TACH_2_GIRQ_BIT BIT(3) +#define MCHP_TACH_3_GIRQ_BIT BIT(4) +#define MCHP_ADC_0_SGL_GIRQ_BIT BIT(8) +#define MCHP_ADC_0_RPT_GIRQ_BIT BIT(9) +#define MCHP_RCID_0_GIRQ_BIT BIT(10) +#define MCHP_RCID_1_GIRQ_BIT BIT(11) +#define MCHP_RCID_2_GIRQ_BIT BIT(12) +#define MCHP_LED_0_GIRQ_BIT BIT(13) +#define MCHP_LED_1_GIRQ_BIT BIT(14) +#define MCHP_LED_2_GIRQ_BIT BIT(15) +#define MCHP_LED_3_GIRQ_BIT BIT(16) +#define MCHP_PHOT_0_GIRQ_BIT BIT(17) +#define MCHP_RPMFAN_0_FAIL_GIRQ_BIT BIT(20) +#define MCHP_RPMFAN_0_STALL_GIRQ_BIT BIT(21) +#define MCHP_RPMFAN_1_FAIL_GIRQ_BIT BIT(22) +#define MCHP_RPMFAN_1_STALL_GIRQ_BIT BIT(23) +/* Masks for blocks with multiple instances or sources */ +#define MCHP_TACH_GIRQ_MASK 0x1Eu +#define MCHP_ADC_GIRQ_MASK 0x300u +#define MCHP_RCID_GIRQ_MASK 0x1C00u +#define MCHP_LED_GIRQ_MASK 0x1E000u +#define MCHP_RPMFAN_0_GIRQ_MASK 0x300000u +#define MCHP_RPMFAN_1_GIRQ_MASK 0xC00000u +#define MCHP_PERIPH_GROUP_1_MASK 0xF3FF1Fu + +/* GIRQ18 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_SPIEP_0_GIRQ_BIT BIT(0) +#define MCHP_QMSPI_0_GIRQ_BIT BIT(1) +#define MCHP_GPSPI_0_TXBE_GIRQ_BIT BIT(2) +#define MCHP_GPSPI_0_RXBF_GIRQ_BIT BIT(3) +#define MCHP_GPSPI_1_TXBE_GIRQ_BIT BIT(4) +#define MCHP_GPSPI_1_RXBF_GIRQ_BIT BIT(5) +#define MCHP_BCL_0_BCLR_GIRQ_BIT BIT(6) +#define MCHP_BCL_0_BERR_GIRQ_BIT BIT(7) +#define MCHP_PS2_0_ACT_GIRQ_BIT BIT(10) +#define MCHP_EERPROMC_0_GIRQ_BIT BIT(13) +#define MCHP_CCT_0_CNT_GIRQ_BIT BIT(20) +#define MCHP_CCT_0_CAP0_GIRQ_BIT BIT(21) +#define MCHP_CCT_0_CAP1_GIRQ_BIT BIT(22) +#define MCHP_CCT_0_CAP2_GIRQ_BIT BIT(23) +#define MCHP_CCT_0_CAP3_GIRQ_BIT BIT(24) +#define MCHP_CCT_0_CAP4_GIRQ_BIT BIT(25) +#define MCHP_CCT_0_CAP5_GIRQ_BIT BIT(26) +#define MCHP_CCT_0_CMP0_GIRQ_BIT BIT(27) +#define MCHP_CCT_0_CMP1_GIRQ_BIT BIT(28) +/* Masks for blocks with multiple instances or sources */ +#define MCHP_GPSPI_0_GIRQ_MASK 0x0Cu +#define MCHP_GPSPI_1_GIRQ_MASK 0x30u +#define MCHP_BCL_0_GIRQ_MASK 0xC0u +#define MCHP_CCT_0_GIRQ_MASK 0x1FF00000u +#define MCHP_PERIPH_GROUP_2_MASK 0x1FF024FFu + +/* GIRQ19 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_ESPI_PC_GIRQ_BIT BIT(0) +#define MCHP_ESPI_BM1_GIRQ_BIT BIT(1) +#define MCHP_ESPI_BM2_GIRQ_BIT BIT(2) +#define MCHP_ESPI_LTR_GIRQ_BIT BIT(3) +#define MCHP_ESPI_OOB_UP_GIRQ_BIT BIT(4) +#define MCHP_ESPI_OOB_DN_GIRQ_BIT BIT(5) +#define MCHP_ESPI_FC_GIRQ_BIT BIT(6) +#define MCHP_ESPI_RESET_GIRQ_BIT BIT(7) +#define MCHP_ESPI_VWEN_GIRQ_BIT BIT(8) +#define MCHP_ESPI_SAF_DONE_GIRQ_BIT BIT(9) +#define MCHP_ESPI_SAF_ERR_GIRQ_BIT BIT(10) +#define MCHP_ESPI_SAF_CACHE_GIRQ_BIT BIT(11) +/* Masks for blocks with multiple instances or sources */ +#define MCHP_ESPI_BM_GIRQ_MASK 0x006u +#define MCHP_ESPI_OOB_GIRQ_MASK 0x030u +#define MCHP_ESPI_SAF_GIRQ_MASK 0xE00u +#define MCHP_ESPI_GIRQ_MASK 0xFFFu + +/* GIRQ20 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_STAP_OBF_GIRQ_BIT BIT(0) +#define MCHP_STAP_IBF_GIRQ_BIT BIT(1) +#define MCHP_STAP_WAKE_GIRQ_BIT BIT(2) +#define MCHP_OTP_READY_GIRQ_BIT BIT(3) +#define MCHP_ISPI_ERR_GIRQ_BIT BIT(8) +#define MCHP_CLK32_MON_GIRQ_BIT BIT(9) +/* Masks for blocks with multiple instances or sources */ +#define MCHP_STAP_GIRQ_MASK 0x007u +#define MCHP_PERIPH_GROUP_3_MASK 0x30Fu + +/* GIRQ21 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_WDT_GIRQ_BIT BIT(2) +#define MCHP_WTMR_ALARM_GIRQ_BIT BIT(3) +#define MCHP_WTMR_SUBWK_GIRQ_BIT BIT(4) +#define MCHP_WTMR_ONESEC_GIRQ_BIT BIT(5) +#define MCHP_WTMR_SUBSEC_GIRQ_BIT BIT(6) +#define MCHP_WTMR_SPP_GIRQ_BIT BIT(7) +#define MCHP_RTC_GIRQ_BIT BIT(8) +#define MCHP_RTC_ALARM_GIRQ_BIT BIT(9) +#define MCHP_VCI_OVRD_IN_GIRQ_BIT BIT(10) +#define MCHP_VCI_IN0_GIRQ_BIT BIT(11) +#define MCHP_VCI_IN1_GIRQ_BIT BIT(12) +#define MCHP_VCI_IN2_GIRQ_BIT BIT(13) +#define MCHP_VCI_IN3_GIRQ_BIT BIT(14) +#define MCHP_VCI_IN4_GIRQ_BIT BIT(15) +#define MCHP_PS2_0_PORT0A_WK_GIRQ_BIT BIT(18) +#define MCHP_PS2_0_PORT0B_WK_GIRQ_BIT BIT(19) +#define MCHP_KEYSCAN_GIRQ_BIT BIT(25) +#define MCHP_GLUE_GIRQ_BIT BIT(26) +/* Masks for blocks with multiple instances or sources */ +#define MCHP_WTMR_GIRQ_MASK 0xF8u +#define MCHP_RTC_GIRQ_MASK 0x300u +#define MCHP_VCI_GIRQ_MASK 0xFC00u +#define MCHP_PS2_PORT_WK_GIRQ_MASK 0xC0000u +#define MCHP_PERIPH_GROUP_4_MASK 0x60CFFFCu + +/* + * GIRQ22 Source, Enable_Set/Clr, Result registers bit positions + * NOTE: These wake sources allow the peripheral to turn back on clocks + * long enough to facilite the data transfer. No interrupt to the EC occurs + * unless the peripheral was configured to generate an EC interrupt for + * the specific data transfer. + */ +#define MCHP_SPIEP_WK_CLK_GIRQ_BIT BIT(0) +#define MCHP_I2C_SMB_0_WK_CLK_GIRQ_BIT BIT(1) +#define MCHP_I2C_SMB_1_WK_CLK_GIRQ_BIT BIT(2) +#define MCHP_I2C_SMB_2_WK_CLK_GIRQ_BIT BIT(3) +#define MCHP_I2C_SMB_3_WK_CLK_GIRQ_BIT BIT(4) +#define MCHP_I2C_SMB_4_WK_CLK_GIRQ_BIT BIT(5) +#define MCHP_ESPI_WK_CLK_GIRQ_BIT BIT(9) +#define MCHP_STAP_WK_CLK_GIRQ_BIT BIT(15) +/* Masks for blocks with multiple instances or sources */ +#define MCHP_I2C_SMB_WK_CLK_GIRQ_MASK 0x3Eu +#define MCHP_CLK_WK_CLK_GIRQ_MASK 0x823Fu + +/* GIRQ23 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_BTMR16_0_GIRQ_BIT BIT(0) +#define MCHP_BTMR16_1_GIRQ_BIT BIT(1) +#define MCHP_BTMR16_2_GIRQ_BIT BIT(2) +#define MCHP_BTMR16_3_GIRQ_BIT BIT(3) +#define MCHP_BTMR32_0_GIRQ_BIT BIT(4) +#define MCHP_BTMR32_1_GIRQ_BIT BIT(5) +#define MCHP_CTMR_0_GIRQ_BIT BIT(6) +#define MCHP_CTMR_1_GIRQ_BIT BIT(7) +#define MCHP_CTMR_2_GIRQ_BIT BIT(8) +#define MCHP_CTMR_3_GIRQ_BIT BIT(9) +#define MCHP_RTMR_0_GIRQ_BIT BIT(10) +#define MCHP_RTMR_0_SWI0_GIRQ_BIT BIT(11) +#define MCHP_RTMR_0_SWI1_GIRQ_BIT BIT(12) +#define MCHP_RTMR_0_SWI2_GIRQ_BIT BIT(13) +#define MCHP_RTMR_0_SWI3_GIRQ_BIT BIT(14) +#define MCHP_HTMR_0_GIRQ_BIT BIT(16) +#define MCHP_HTMR_1_GIRQ_BIT BIT(17) +/* Masks for blocks with multiple instances or sources */ +#define MCHP_BTMR16_GIRQ_MASK 0x0Fu +#define MCHP_BTMR32_GIRQ_MASK 0x30u +#define MCHP_CTMR_GIRQ_MASK 0x3C0u +#define MCHP_RMTR_GIRQ_MASK 0x7C00u +#define MCHP_HTMR_GIRQ_MASK 0x30000u +#define MCHP_PERIPH_GROUP_5_GIRQ_MASK 0x37FFFu + +/* GIRQ24 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_MSVW00_SRC0_GIRQ_BIT BIT(0) +#define MCHP_MSVW00_SRC1_GIRQ_BIT BIT(1) +#define MCHP_MSVW00_SRC2_GIRQ_BIT BIT(2) +#define MCHP_MSVW00_SRC3_GIRQ_BIT BIT(3) +#define MCHP_MSVW01_SRC0_GIRQ_BIT BIT(4) +#define MCHP_MSVW01_SRC1_GIRQ_BIT BIT(5) +#define MCHP_MSVW01_SRC2_GIRQ_BIT BIT(6) +#define MCHP_MSVW01_SRC3_GIRQ_BIT BIT(7) +#define MCHP_MSVW02_SRC0_GIRQ_BIT BIT(8) +#define MCHP_MSVW02_SRC1_GIRQ_BIT BIT(9) +#define MCHP_MSVW02_SRC2_GIRQ_BIT BIT(10) +#define MCHP_MSVW02_SRC3_GIRQ_BIT BIT(11) +#define MCHP_MSVW03_SRC0_GIRQ_BIT BIT(12) +#define MCHP_MSVW03_SRC1_GIRQ_BIT BIT(13) +#define MCHP_MSVW03_SRC2_GIRQ_BIT BIT(14) +#define MCHP_MSVW03_SRC3_GIRQ_BIT BIT(15) +#define MCHP_MSVW04_SRC0_GIRQ_BIT BIT(16) +#define MCHP_MSVW04_SRC1_GIRQ_BIT BIT(17) +#define MCHP_MSVW04_SRC2_GIRQ_BIT BIT(18) +#define MCHP_MSVW04_SRC3_GIRQ_BIT BIT(19) +#define MCHP_MSVW05_SRC0_GIRQ_BIT BIT(20) +#define MCHP_MSVW05_SRC1_GIRQ_BIT BIT(21) +#define MCHP_MSVW05_SRC2_GIRQ_BIT BIT(22) +#define MCHP_MSVW05_SRC3_GIRQ_BIT BIT(23) +#define MCHP_MSVW06_SRC0_GIRQ_BIT BIT(24) +#define MCHP_MSVW06_SRC1_GIRQ_BIT BIT(25) +#define MCHP_MSVW06_SRC2_GIRQ_BIT BIT(26) +#define MCHP_MSVW06_SRC3_GIRQ_BIT BIT(27) +/* Masks for blocks with multiple instances or sources */ +#define MCHP_MSVW00_GIRQ_MASK 0xFu +#define MCHP_MSVW01_GIRQ_MASK 0xF0u +#define MCHP_MSVW02_GIRQ_MASK 0xF00u +#define MCHP_MSVW03_GIRQ_MASK 0xF000u +#define MCHP_MSVW04_GIRQ_MASK 0xF0000u +#define MCHP_MSVW05_GIRQ_MASK 0xF00000u +#define MCHP_MSVW06_GIRQ_MASK 0xF000000u +#define MCHP_MSVW00_06_GIRQ_MASK 0x0FFFFFFFu + +/* GIRQ25 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_MSVW07_SRC0_GIRQ_BIT BIT(0) +#define MCHP_MSVW07_SRC1_GIRQ_BIT BIT(1) +#define MCHP_MSVW07_SRC2_GIRQ_BIT BIT(2) +#define MCHP_MSVW07_SRC3_GIRQ_BIT BIT(3) +#define MCHP_MSVW08_SRC0_GIRQ_BIT BIT(4) +#define MCHP_MSVW08_SRC1_GIRQ_BIT BIT(5) +#define MCHP_MSVW08_SRC2_GIRQ_BIT BIT(6) +#define MCHP_MSVW08_SRC3_GIRQ_BIT BIT(7) +#define MCHP_MSVW09_SRC0_GIRQ_BIT BIT(8) +#define MCHP_MSVW09_SRC1_GIRQ_BIT BIT(9) +#define MCHP_MSVW09_SRC2_GIRQ_BIT BIT(10) +#define MCHP_MSVW09_SRC3_GIRQ_BIT BIT(11) +#define MCHP_MSVW10_SRC0_GIRQ_BIT BIT(12) +#define MCHP_MSVW10_SRC1_GIRQ_BIT BIT(13) +#define MCHP_MSVW10_SRC2_GIRQ_BIT BIT(14) +#define MCHP_MSVW10_SRC3_GIRQ_BIT BIT(15) +/* Masks for blocks with multiple instances or sources */ +#define MCHP_MSVW07_GIRQ_MASK 0xFu +#define MCHP_MSVW08_GIRQ_MASK 0xF0u +#define MCHP_MSVW09_GIRQ_MASK 0xF00u +#define MCHP_MSVW10_GIRQ_MASK 0xF000u +#define MCHP_MSVW07_10_GIRQ_MASK 0xFFFFu + +/* GIRQ26 Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_GPIO_0240_GIRQ_BIT BIT(0) +#define MCHP_GPIO_0241_GIRQ_BIT BIT(1) +#define MCHP_GPIO_0242_GIRQ_BIT BIT(2) +#define MCHP_GPIO_0243_GIRQ_BIT BIT(3) +#define MCHP_GPIO_0244_GIRQ_BIT BIT(4) +#define MCHP_GPIO_0245_GIRQ_BIT BIT(5) +#define MCHP_GPIO_0246_GIRQ_BIT BIT(6) +#define MCHP_GPIO_0254_GIRQ_BIT BIT(12) +#define MCHP_GPIO_0255_GIRQ_BIT BIT(13) +/* Masks for blocks with multiple instances or sources */ +#define MCHP_GPIO_0240_0276_GIRQ_MASK 0x307Fu + +/* GIRQ numbering */ +#define MCHP_GIRQ_START_NUM 8u +#define MCHP_GIRQ_LAST_NUM 26u +#define MCHP_GIRQ_IDX(girq) ((uint32_t)(girq) - 8ul) +#define MCHP_GIRQ_IDX_FIRST 0u +#define MCHP_GIRQ_IDX_MAX 19u +/* Number of NVIC Enable_Set/Clr, Pending_Set/Clr, Active 32-bit registers */ +#define MCHP_MAX_NVIC_IDX 6u +/* Number of external NVIC inputs */ +#define MCHP_MAX_NVIC_EXT_INPUTS 181u + +#endif /* #ifndef _COMPONENT_ECIA_H */ +/* end ecia.h */ +/** @} + */ diff --git a/mec/mec172x/component/ecs.h b/mec/mec172x/component/ecs.h new file mode 100644 index 0000000..6c9c7e6 --- /dev/null +++ b/mec/mec172x/component/ecs.h @@ -0,0 +1,229 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file ecs.h + * MEC172x EC Subsystem (ECS) registers + */ +/** @defgroup MEC172x Peripherals ECS + */ + +#include +#include + +#include +#include + +#ifndef _COMPONENT_ECS_H +#define _COMPONENT_ECS_H + +/* =========================================================================*/ +/* ================ ECS ================ */ +/* =========================================================================*/ + +#define MCHP_ECS_BASE_ADDR 0x4000FC00ul + +/* AHB Error Address, write any value to clear */ +#define MCHP_ECS_AHB_ERR_ADDR_OFS 0x04ul + +/* AHB Error Control */ +#define MCHP_ECS_AHB_ERR_CTRL_OFS 0x14ul +#define MCHP_ECS_AHB_ERR_CTRL_DIS_POS 0 +#define MCHP_ECS_AHB_ERR_CTRL_DIS BIT(MCHP_ECS_AHB_ERR_CTRL_DIS_POS) + +/* Interrupt Control */ +#define MCHP_ECS_ICTRL_OFS 0x18ul +#define MCHP_ECS_ICTRL_DIRECT_POS 0 +#define MCHP_ECS_ICTRL_DIRECT_EN BIT(MCHP_ECS_ICTRL_DIRECT_POS) + +/* ETM Control Register */ +#define MCHP_ECS_ETM_CTRL_OFS 0x1Cul +#define MCHP_ECS_ETM_CTRL_EN_POS 0 +#define MCHP_ECS_ETM_CTRL_EN BIT(MCHP_ECS_ETM_CTRL_EN_POS) + +/* Debug Control Register */ +#define MCHP_ECS_DCTRL_OFS 0x20ul +#define MCHP_ECS_DCTRL_MASK 0x1Ful +#define MCHP_ECS_DCTRL_DBG_EN_POS 0u +#define MCHP_ECS_DCTRL_DBG_EN BIT(MCHP_ECS_DCTRL_DBG_EN_POS) +#define MCHP_ECS_DCTRL_MODE_POS 1u +#define MCHP_ECS_DCTRL_MODE_MASK0 0x03ul +#define MCHP_ECS_DCTRL_MODE_MASK \ + SHLU32(MCHP_ECS_DCTRL_DBG_MODE_MASK0, MCHP_ECS_DCTRL_DBG_MODE_POS) + +#define MCHP_ECS_DCTRL_DBG_MODE_POS 1u +#define MCHP_ECS_DCTRL_MODE_JTAG 0x00u +#define MCHP_ECS_DCTRL_MODE_SWD SHLU32(0x02u, 1u) +#define MCHP_ECS_DCTRL_MODE_SWD_SWV SHLU32(0x01u, 1u) +#define MCHP_ECS_DCTRL_PUEN_POS 3u +#define MCHP_ECS_DCTRL_PUEN BIT(MCHP_ECS_DCTRL_PUEN_POS) +#define MCHP_ECS_DCTRL_BSCAN_POS 4u +#define MCHP_ECS_DCTRL_BSCAN_EN BIT(MCHP_ECS_DCTRL_BSCAN_POS) + +/* WDT Event Count */ +#define MCHP_ECS_WDT_EVC_OFS 0x28U +#define MCHP_ECS_WDT_EVC_MASK 0x0FU + +/* PECI Disable */ +#define MCHP_ECS_PECI_DIS_OFS 0x40U +#define MCHP_ECS_PECI_DIS_MASK 0x01U +#define MCHP_ECS_PECI_DIS_POS 0 +#define MCHP_ECS_PECI_DISABLE BIT(0) + +/* VCI FW Override */ +#define MCHP_ECS_VCI_FW_OVR_OFS 0x50U +#define MCHP_ECS_VCI_FW_OVR_MASK 0x01U +#define MCHP_ECS_VCI_FW_OVR_SSHD_POS 0 +#define MCHP_ECS_VCI_FW_OVR_SSHD BIT(0) + +/* Boot-ROM Status */ +#define MCHP_ECS_BROM_STS_OFS 0x54U +#define MCHP_ECS_BROM_STS_MASK 0x03U +#define MCHP_ECS_BROM_STS_VTR_POS 0 +#define MCHP_ECS_BROM_STS_WDT_POS 1 +#define MCHP_ECS_BROM_STS_VTR BIT(0) +#define MCHP_ECS_BROM_STS_WDT BIT(1) + +/* JTAG Controller Config */ +#define MCHP_ECS_JTCC_OFS 0x70U +#define MCHP_ECS_JTCC_MASK 0x0FU +#define MCHP_ECS_JTCC_CLK_POS 0 +#define MCHP_ECS_JTCC_CLK_DFLT 0x03U +#define MCHP_ECS_JTCC_CLK_24M 0x01U +#define MCHP_ECS_JTCC_CLK_12M 0x02U +#define MCHP_ECS_JTCC_CLK_6M 0x03U +#define MCHP_ECS_JTCC_CLK_3M 0x04U +#define MCHP_ECS_JTCC_CLK_1500K 0x05U +#define MCHP_ECS_JTCC_CLK_750K 0x06U +#define MCHP_ECS_JTCC_CLK_375K 0x07U +#define MCHP_ECS_JTCC_MS_POS 3 +#define MCHP_ECS_JTCC_M BIT(3) + +/* JTAG Controller Status */ +#define MCHP_ECS_JTST_OFS 0x74U +#define MCHP_ECS_JTST_MASK 0x01U +#define MCHP_ECS_JTST_DONE BIT(0) + +#define MCHP_ECS_JT_TDO_OFS 0x78U +#define MCHP_ECS_JT_TDI_OFS 0x7CU +#define MCHP_ECS_JT_TMS_OFS 0x80U + +/* JTAG Controller Command */ +#define MCHP_ECS_JT_CMD_OFS 0x84U +#define MCHP_ECS_JT_CMD_MASK 0x1FU + +/* VWire Source Configuration */ +#define MCHP_ECS_VWSC_OFS 0x90U +#define MCHP_ECS_VWSC_MASK 0x07U +#define MCHP_ECS_VWSC_DFLT 0x07U +#define MCHP_ECS_VWSC_EC_SCI_DIS BIT(0) +#define MCHP_ECS_VWSC_MBH_SMI_DIS BIT(1) + +/* Analog Comparator Control */ +#define MCHP_ECS_ACC_OFS 0x94U +#define MCHP_ECS_ACC_MASK 0x15U +#define MCHP_ECS_ACC_EN0 BIT(0) +#define MCHP_ECS_ACC_CFG_LOCK0 BIT(2) +#define MCHP_ECS_ACC_EN1 BIT(4) + +/* Analog Comparator Sleep Control */ +#define MCHP_ECS_ACSC_OFS 0x98U +#define MCHP_ECS_ACSC_MASK 0x03U +#define MCHP_ECS_ACSC_DSLP_EN0 BIT(0) +#define MCHP_ECS_ACSC_DSLP_EN1 BIT(1) + +/* Embedded Reset Enable */ +#define MCHP_ECS_EMBR_EN_OFS 0xB0U +#define MCHP_ECS_EMBR_EN_MASK 0x01U +#define MCHP_ECS_EMBR_EN_ON BIT(0) + +/* Embedded Reset Timeout value */ +#define MCHP_ECS_EMBR_TMOUT_OFS 0xB4U +#define MCHP_ECS_EMBR_TMOUT_MASK 0x07U +#define MCHP_ECS_EMBR_TMOUT_6S 0U +#define MCHP_ECS_EMBR_TMOUT_7S 1U +#define MCHP_ECS_EMBR_TMOUT_8S 2U +#define MCHP_ECS_EMBR_TMOUT_9S 3U +#define MCHP_ECS_EMBR_TMOUT_10S 4U +#define MCHP_ECS_EMBR_TMOUT_11S 5U +#define MCHP_ECS_EMBR_TMOUT_12S 6U +#define MCHP_ECS_EMBR_TMOUT_14S 7U + +/* Embedded Reset Status */ +#define MCHP_ECS_EMBR_STS_OFS 0xB8U +#define MCHP_ECS_EMBR_STS_MASK 0x01U +#define MCHP_ECS_EMBR_STS_RST BIT(0) + +/* Embedded Reset Count (RO) */ +#define MCHP_ECS_EMBR_CNT_OFS 0xBCU +#define MCHP_ECS_EMBR_CNT_MASK 0x7ffffU + +/* Register Access */ +#define MCHP_ECS_AHB_ERR() \ + REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_AHB_ERR_ADDR_OFS) + +#define MCHP_ECS_AHB_ERR_CTRL() \ + REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_AHB_ERR_CTRL_OFS) + +#define MCHP_ECS_ICTRL() \ + REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_ICTRL_OFS) + +#define MCHP_ECS_ETM_CTRL() \ + REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_ETM_CTRL_OFS) + +#define MCHP_ECS_DCTRL() \ + REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_DCTRL_OFS) + +#define MCHP_ECS_WDT_EVC() REG8(MCHP_ECS_BASE_ADDR + MCHP_ECS_WDT_EVC_OFS) + +#define MCHP_ECS_PECI_DIS() REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_PECI_DIS_OFS) + +#define MCHP_ECS_VCI_FW_OVR() \ + REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_VCI_FW_OVR_OFS) + +#define MCHP_ECS_BROM_STS() REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_BROM_STS_OFS) + +#define MCHP_ECS_JTCC() REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_JTCC_OFS) +#define MCHP_ECS_JTST() REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_JTST_OFS) +#define MCHP_ECS_JT_TDO() REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_JT_TDO_OFS) +#define MCHP_ECS_JT_TDI() REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_JT_TDI_OFS) +#define MCHP_ECS_JT_TMS() REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_JT_TMS_OFS) +#define MCHP_ECS_JT_CMD() REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_JT_CMD_OFS) + +#define MCHP_ECS_VWSC() REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_VWSC_OFS) + +#define MCHP_ECS_ACC() REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_ACC_OFS) +#define MCHP_ECS_ACSC() REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_ACSC_OFS) + +#define MCHP_ECS_EMBR_EN() REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_EMBR_EN_OFS) +#define MCHP_ECS_EMBR_TMOUT() \ + REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_EMBR_TMOUT_OFS) +#define MCHP_ECS_EMBR_STS() REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_EMBR_STS_OFS) +#define MCHP_ECS_EMBR_CNT() REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_EMBR_CNT_OFS) + +#endif /* #ifndef _COMPONENT_ECS_H */ +/* end ecs.h */ +/** @} + */ diff --git a/mec/mec172x/component/eepromc.h b/mec/mec172x/component/eepromc.h new file mode 100644 index 0000000..7196724 --- /dev/null +++ b/mec/mec172x/component/eepromc.h @@ -0,0 +1,105 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file eepromc.h + * MEC172x EEPROM controller registers + */ +/** @defgroup MEC172x Peripherals EEPROM + */ + +#ifndef _COMPONENT_EEPROMC_H +#define _COMPONENT_EEPROMC_H + +#include +#include + +#include +#include + +#define MCHP_EEPROM_0_BASE_ADDR 0x40002C00ul + +#define MCHP_EEPROM_GIRQ 18u +#define MCHP_EEPROM_NVIC_GIRQ 10u +#define MCHP_EEPROM_POS 13u +#define MCHP_EEPROM_NVIC 155u +#define MCHP_EEPROM_GIRQ_VAL BIT(13) + +/* EC-only registers */ + +/* EEPROM controller mode register at 0x00 */ +#define MCHP_EEPROM_MODE_OFS 0x00u +#define MCHP_EEPROM_MODE_MASK 0x03u +#define MCHP_EEPROM_MODE_ACTV BIT(0) +#define MCHP_EEPROM_MODE_SRST BIT(1) + +/* EEPROM controller execute register at 0x04 */ +#define MCHP_EEPROM_EXE_OFS 0x04u +#define MCHP_EEPROM_EXE_ADDR_POS 0 +#define MCHP_EEPROM_EXE_ADDR_MSK 0xFFFFu +#define MCHP_EEPROM_EXE_CMD_POS 16 +#define MCHP_EEPROM_EXE_CMD_MSK 0x70000u +#define MCHP_EEPROM_EXE_SZ_POS 24 +#define MCHP_EEPROM_EXE_SZ_MSK 0x1F000000u + +#define MCHP_EEPROM_EXE_VAL(addr, cmd, sz) \ + ((SHLU32(addr, MCHP_EEPROM_EXE_ADDR_POS) & MCHP_EEPROM_EXE_ADDR_MSK) \ + | (SHLU32(cmd, MCHP_EEPROM_EXE_CMD_POS) & MCHP_EEPROM_EXE_CMD_MSK) \ + | (SHLU32(sz, MCHP_EEPROM_EXE_SZ_POS) & MCHP_EEPROM_EXE_SZ_MSK)) + +/* EEPROM controller status register at 0x08 */ +#define MCHP_EEPROM_STS_OFS 0x08u +#define MCHP_EEPROM_STS_MASK 0x103u +#define MCHP_EEPROM_STS_DONE BIT(0) +#define MCHP_EEPROM_STS_ERR BIT(1) +#define MCHP_EEPROM_STS_ACTIVE_RO BIT(8) + +/* EEPROM controller interrupt enable register at 0x0C */ +#define MCHP_EEPROM_IEN_OFS 0x0Cu +#define MCHP_EEPROM_IEN_MASK 0x03u +#define MCHP_EEPROM_IEN_DONE BIT(0) +#define MCHP_EEPROM_IEN_ERR BIT(1) + +/* EEPROM controller password register at 0x10 (WO) */ +#define MCHP_EEPROM_PSWD_OFS 0x10u +#define MCHP_EEPROM_PSWD_MASK 0x7FFFFFFFul + +/* EEPROM controller unlock register at 0x14 (WO) */ +#define MCHP_EEPROM_UNLOCK_OFS 0x14u +#define MCHP_EEPROM_ULOCK_MASK 0x7FFFFFFFul + +/* EEPROM controller lock register at 0x18 */ +#define MCHP_EEPROM_LOCK_OFS 0x18u +#define MCHP_EEPROM_LOCK_MASK 0x03u +#define MCHP_EEPROM_LOCK_JTAG BIT(0) +#define MCHP_EEPROM_LOCK_ACCESS BIT(1) + +/* EEPROM controller buffer/data registers at 0x20 - 0x3F */ +#define MCHP_EEPROM_DATA_OFS 0x20u + +#endif /* #ifndef _COMPONENT_EEPROMC_H */ +/* end eepromc.h */ +/** @} + */ diff --git a/mec/mec172x/component/emi.h b/mec/mec172x/component/emi.h new file mode 100644 index 0000000..c279864 --- /dev/null +++ b/mec/mec172x/component/emi.h @@ -0,0 +1,142 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file emi.h + * MEC172x EC Host Memory Interface Registers + */ +/** @defgroup MEC172x Peripherals EMI + */ + +#ifndef _COMPONENT_EMI_H +#define _COMPONENT_EMI_H + +#include +#include + +#include +#include + +#define MCHP_EMI_BASE_ADDR 0x400F4000ul + +#define MCHP_EMI_SPACING 0x0400ul +#define MCHP_EMI_SPACING_PWROF2 10u + +#define MCHP_EMI0_ADDR 0x400F4000ul +#define MCHP_EMI1_ADDR 0x400F4400ul +#define MCHP_EMI2_ADDR 0x400F4800ul + +/* EMI interrupts */ +#define MCHP_EMI_GIRQ 15u +#define MCHP_EMI_GIRQ_NVIC 7u +/* Direct NVIC connections */ +#define MCHP_EMI0_NVIC 42u +#define MCHP_EMI1_NVIC 43u +#define MCHP_EMI2_NVIC 44u + +/* GIRQ Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_EMI0_GIRQ_POS 2u +#define MCHP_EMI1_GIRQ_POS 3u +#define MCHP_EMI2_GIRQ_POS 4u + +#define MCHP_EMI0_GIRQ BIT(2) +#define MCHP_EMI1_GIRQ BIT(3) +#define MCHP_EMI2_GIRQ BIT(4) + +/* OS_INT_SRC_LSB */ +#define MCHP_EMI_OSIS_LSB_EC_WR_POS 0u +#define MCHP_EMI_OSIS_LSB_EC_WR BIT(0) +/* the following bits are also apply to OS_INT_MASK_LSB */ +#define MCHP_EMI_OSIS_LSB_SWI_POS 1u +#define MCHP_EMI_OSIS_LSB_SWI_MASK0 0x7Ful +#define MCHP_EMI_OSIS_LSB_SWI_MASK 0xFEul +#define MCHP_EMI_OSIS_LSB_SWI1 BIT(1) +#define MCHP_EMI_OSIS_LSB_SWI2 BIT(2) +#define MCHP_EMI_OSIS_LSB_SWI3 BIT(3) +#define MCHP_EMI_OSIS_LSB_SWI4 BIT(4) +#define MCHP_EMI_OSIS_LSB_SWI5 BIT(5) +#define MCHP_EMI_OSIS_LSB_SWI6 BIT(6) +#define MCHP_EMI_OSIS_LSB_SWI7 BIT(7) + +/* OS_INT_SRC_MSB and OS_INT_MASK_MSB */ +#define MCHP_EMI_OSIS_MSB_SWI_POS 0u +#define MCHP_EMI_OSIS_MSB_SWI_MASK0 0xFFul +#define MCHP_EMI_OSIS_MSB_SWI_MASK 0xFFul +#define MCHP_EMI_OSIS_MSB_SWI8 BIT(0) +#define MCHP_EMI_OSIS_MSB_SWI9 BIT(1) +#define MCHP_EMI_OSIS_MSB_SWI10 BIT(2) +#define MCHP_EMI_OSIS_MSB_SWI11 BIT(3) +#define MCHP_EMI_OSIS_MSB_SWI12 BIT(4) +#define MCHP_EMI_OSIS_MSB_SWI13 BIT(5) +#define MCHP_EMI_OSIS_MSB_SWI14 BIT(6) +#define MCHP_EMI_OSIS_MSB_SWI15 BIT(7) + +/* OS_APP_ID */ +#define MCHP_EMI_OS_APP_ID_MASK 0xFFul + +/* + * MEM_BASE_0 and MEM_BASE_1 registers + * bits[1:0] = 00b read-only forcing EC SRAM location to + * be aligned >= 4 bytes. + */ +#define MCHP_EMI_MEM_BASE_MASK 0xFFFFFFFCul + +/* + * MEM_LIMIT_0 and MEM_LIMIT_1 registers are split into two fields + * bits[15:0] = read limit + * bits[1:0]=00b read-only forcing >= 4 byte alignment + * bits[31:16] = write limit + * bits[17:16]=00b read-only forcing >= 4 byte alignment + */ +#define MEM_EMI_MEM_LIMIT_MASK 0xFFFCFFFCul +#define MEM_EMI_MEM_LIMIT_RD_POS 0u +#define MEM_EMI_MEM_LIMIT_RD_MASK0 0xFFFCul +#define MEM_EMI_MEM_LIMIT_RD_MASK 0xFFFCul +#define MEM_EMI_MEM_LIMIT_WR_POS 16u +#define MEM_EMI_MEM_LIMIT_WR_MASK0 0xFFFCul +#define MEM_EMI_MEM_LIMIT_WR_MASK SHLU32(0xFFFCu, 16) + +/* EC_SET_OS_INT and EC_OS_INT_CLR_EN */ +#define MCHP_EMI_EC_OS_SWI_MASK 0xFFFEul +#define MCHP_EMI_EC_OS_SWI1 BIT(1) +#define MCHP_EMI_EC_OS_SWI2 BIT(2) +#define MCHP_EMI_EC_OS_SWI3 BIT(3) +#define MCHP_EMI_EC_OS_SWI4 BIT(4) +#define MCHP_EMI_EC_OS_SWI5 BIT(5) +#define MCHP_EMI_EC_OS_SWI6 BIT(6) +#define MCHP_EMI_EC_OS_SWI7 BIT(7) +#define MCHP_EMI_EC_OS_SWI8 BIT(8) +#define MCHP_EMI_EC_OS_SWI9 BIT(9) +#define MCHP_EMI_EC_OS_SWI10 BIT(10) +#define MCHP_EMI_EC_OS_SWI11 BIT(11) +#define MCHP_EMI_EC_OS_SWI12 BIT(12) +#define MCHP_EMI_EC_OS_SWI13 BIT(13) +#define MCHP_EMI_EC_OS_SWI14 BIT(14) +#define MCHP_EMI_EC_OS_SWI15 BIT(15) + +#endif /* #ifndef _COMPONENT_EMI_H */ +/* end emi.h */ +/** @} + */ diff --git a/mec/mec172x/component/espi_io.h b/mec/mec172x/component/espi_io.h new file mode 100644 index 0000000..39d0971 --- /dev/null +++ b/mec/mec172x/component/espi_io.h @@ -0,0 +1,707 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file espi_io.h + * MEC172x eSPI IO Component definitions + */ +/** @defgroup MEC172x Peripherals eSPI IO Component + */ + +#ifndef _COMPONENT_ESPI_IO_H +#define _COMPONENT_ESPI_IO_H + +#include +#include + +#include +#include + +/*------------------------------------------------------------------*/ + +#define MCHP_ESPI_IO_BASE_ADDR 0x400F3400ul + +/* Offsets from base for various register groups */ +#define MCHP_ESPI_IO_PC_OFS 0x0100ul +#define MCHP_ESPI_IO_HOST_BAR_OFS 0x0120ul +#define MCHP_ESPI_IO_LTR_OFS 0x0220ul +#define MCHP_ESPI_IO_OOB_OFS 0x0240ul +#define MCHP_ESPI_IO_FC_OFS 0x0280ul +#define MCHP_ESPI_IO_CAP_OFS 0x02b0ul +#define MCHP_ESPI_IO_SIRQ_OFS 0x03a0ul + +/* ESPI IO Component interrupts */ +#define MCHP_ESPI_IO_GIRQ 19u +#define MCHP_ESPI_IO_GIRQ_NVIC 11u + +/* Direct mode NVIC inputs */ +#define MCHP_ESPI_PC_NVIC 103u +#define MCHP_ESPI_BM1_NVIC 104u +#define MCHP_ESPI_BM2_NVIC 105u +#define MCHP_ESPI_LTR_NVIC 106u +#define MCHP_ESPI_OOB_UP_NVIC 107u +#define MCHP_ESPI_OOB_DN_NVIC 108u +#define MCHP_ESPI_FC_NVIC 109u +#define MCHP_ESPI_ESPI_RST_NVIC 110u +#define MCHP_ESPI_VW_EN_NVIC 156u +#define MCHP_ESPI_SAF_DONE 166u +#define MCHP_ESPI_SAF_ERR 167u +#define MCHP_ESPI_SAF_CACHE 169u + +/* GIRQ Source, Enable_Set/Clr, Result registers bit positions */ +#define MCHP_ESPI_PC_GIRQ_POS 0u +#define MCHP_ESPI_BM1_GIRQ_POS 1u +#define MCHP_ESPI_BM2_GIRQ_POS 2u +#define MCHP_ESPI_LTR_GIRQ_POS 3u +#define MCHP_ESPI_OOB_UP_GIRQ_POS 4u +#define MCHP_ESPI_OOB_DN_GIRQ_POS 5u +#define MCHP_ESPI_FC_GIRQ_POS 6u +#define MCHP_ESPI_ESPI_RST_GIRQ_POS 7u +#define MCHP_ESPI_VW_EN_GIRQ_POS 8u +#define MCHP_ESPI_SAF_DONE_GIRQ_POS 9u +#define MCHP_ESPI_SAF_ERR_GIRQ_POS 10u +#define MCHP_ESPI_SAF_CACHE_GIRQ_POS 11u + +#define MCHP_ESPI_PC_GIRQ_VAL BIT(0) +#define MCHP_ESPI_BM1_GIRQ_VAL BIT(1) +#define MCHP_ESPI_BM2_GIRQ_VAL BIT(2) +#define MCHP_ESPI_LTR_GIRQ_VAL BIT(3) +#define MCHP_ESPI_OOB_UP_GIRQ_VAL BIT(4) +#define MCHP_ESPI_OOB_DN_GIRQ_VAL BIT(5) +#define MCHP_ESPI_FC_GIRQ_VAL BIT(6) +#define MCHP_ESPI_ESPI_RST_GIRQ_VAL BIT(7) +#define MCHP_ESPI_VW_EN_GIRQ_VAL BIT(8) +#define MCHP_ESPI_SAF_DONE_GIRQ_VAL BIT(9) +#define MCHP_ESPI_SAF_ERR_GIRQ_VAL BIT(10) +#define MCHP_ESPI_SAF_CACHE_GIRQ_VAL BIT(11) + +/* eSPI Global Capabilities 0 */ +#define MCHP_ESPI_GBL_CAP0_MASK 0x0Fu +#define MCHP_ESPI_GBL_CAP0_PC_SUPP BIT(0) +#define MCHP_ESPI_GBL_CAP0_VW_SUPP BIT(1) +#define MCHP_ESPI_GBL_CAP0_OOB_SUPP BIT(2) +#define MCHP_ESPI_GBL_CAP0_FC_SUPP BIT(3) + +/* eSPI Global Capabilities 1 */ +#define MCHP_ESPI_GBL_CAP1_MASK 0xFFu +#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_POS 0u +#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_MASK 0x07u +#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_20M 0x00u +#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_25M 0x01u +#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_33M 0x02u +#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_50M 0x03u +#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_66M 0x04u +#define MCHP_ESPI_GBL_CAP1_ALERT_POS 3u /* Read-Only */ +#define MCHP_ESPI_GBL_CAP1_ALERT_DED_PIN \ + BIT(MCHP_ESPI_GBL_CAP1_ALERT_POS) +#define MCHP_ESPI_GBL_CAP1_ALERT_ON_IO1 0u +#define MCHP_ESPI_GBL_CAP1_IO_MODE_POS 4u +#define MCHP_ESPI_GBL_CAP1_IO_MODE_MASK0 0x03u +#define MCHP_ESPI_GBL_CAP1_IO_MODE_MASK SHLU32(0x03u, 4) +#define MCHP_ESPI_GBL_CAP1_IO_MODE0_1 0u +#define MCHP_ESPI_GBL_CAP1_IO_MODE0_12 1u +#define MCHP_ESPI_GBL_CAP1_IO_MODE0_14 2u +#define MCHP_ESPI_GBL_CAP1_IO_MODE0_124 3u +#define MCHP_ESPI_GBL_CAP1_IO_MODE_1 \ + SHLU32(MCHP_ESPI_GBL_CAP1_IO_MODE0_1, MCHP_ESPI_GBL_CAP1_IO_MODE_POS) + +#define MCHP_ESPI_GBL_CAP1_IO_MODE_12 \ + SHLU32(MCHP_ESPI_GBL_CAP1_IO_MODE0_12, MCHP_ESPI_GBL_CAP1_IO_MODE_POS) + +#define MCHP_ESPI_GBL_CAP1_IO_MODE_14 \ + SHLU32(MCHP_ESPI_GBL_CAP1_IO_MODE0_14, MCHP_ESPI_GBL_CAP1_IO_MODE_POS) + +#define MCHP_ESPI_GBL_CAP1_IO_MODE_124 \ + SHLU32(MCHP_ESPI_GBL_CAP1_IO_MODE0_124, MCHP_ESPI_GBL_CAP1_IO_MODE_POS) + +/* + * Support Open Drain ALERT pin configuration + * EC sets this bit if it can support open-drain ESPI_ALERT# + */ +#define MCHP_ESPI_GBL_CAP1_ALERT_ODS_POS 6u +#define MCHP_ESPI_GBL_CAP1_ALERT_ODS BIT(MCHP_ESPI_GBL_CAP1_ALERT_ODS_POS) + +/* + * Read-Only ALERT Open Drain select. + * If EC has indicated it can support open-drain ESPI_ALERT# then + * the Host can enable open-drain ESPI_ALERT# by sending a configuraiton + * message. This read-only bit relects the configuration selection. + */ +#define MCHP_ESPI_GBL_CAP1_ALERT_ODS_SEL_POS 7u +#define MCHP_ESPI_GBL_CAP1_ALERT_SEL_ODS \ + BIT(MCHP_ESPI_GBL_CAP1_ALERT_ODS_SEL_POS) + +/* Peripheral Channel(PC) Capabilites */ +#define MCHP_ESPI_PC_CAP_MASK 0x07u +#define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_MASK 0x07u +#define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_64 0x01u +#define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_128 0x02u +#define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_256 0x03u + +/* Virtual Wire(VW) Capabilities */ +#define MCHP_ESPI_VW_CAP_MASK 0x3Fu +#define MCHP_ESPI_VW_CAP_MAX_VW_CNT_MASK 0x3Fu + +/* Out-of-Band(OOB) Capabilities */ +#define MCHP_ESPI_OOB_CAP_MASK 0x07u +#define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_MASK 0x07u +#define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_73 0x01u +#define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_137 0x02u +#define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_265 0x03u + +/* Flash Channel(FC) Capabilities */ +#define MCHP_ESPI_FC_CAP_MASK 0xFFu +#define MCHP_ESPI_FC_CAP_MAX_PLD_SZ_MASK 0x07u +#define MCHP_ESPI_FC_CAP_MAX_PLD_SZ_64 0x01u +#define MCHP_ESPI_FC_CAP_SHARE_POS 3u +#define MCHP_ESPI_FC_CAP_SHARE_MASK0 0x03u +#define MCHP_ESPI_FC_CAP_SHARE_MASK \ + SHLU32(MCHP_ESPI_FC_CAP_SHARE_MASK0, MCHP_ESPI_FC_CAP_SHARE_POS) + +#define MCHP_ESPI_FC_CAP_SHARE_MAF_ONLY 0u +#define MCHP_ESPI_FC_CAP_SHARE_MAF2_ONLY \ + SHLU32(1U, MCHP_ESPI_FC_CAP_SHARE_POS) + +#define MCHP_ESPI_FC_CAP_SHARE_SAF_ONLY \ + SHLU32(2U, MCHP_ESPI_FC_CAP_SHARE_POS) + +#define MCHP_ESPI_FC_CAP_SHARE_MAF_SAF \ + SHLU32(3U, MCHP_ESPI_FC_CAP_SHARE_POS) + +#define MCHP_ESPI_FC_CAP_MAX_RD_SZ_POS 5u +#define MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK0 0x07u +#define MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK \ + SHLU32(MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK0, \ + MCHP_ESPI_FC_CAP_MAX_RD_SZ_POS) + +#define MCHP_ESPI_FC_CAP_MAX_RD_SZ_64 \ + BIT(MCHP_ESPI_FC_CAP_MAX_RD_SZ_POS) + +/* PC Ready */ +#define MCHP_ESPI_PC_READY_MASK 0x01u; +#define MCHP_ESPI_PC_READY 0x01u; + +/* OOB Ready */ +#define MCHP_ESPI_OOB_READY_MASK 0x01u; +#define MCHP_ESPI_OOB_READY 0x01u; + +/* FC Ready */ +#define MCHP_ESPI_FC_READY_MASK 0x01u; +#define MCHP_ESPI_FC_READY 0x01u; + +/* ESPI_RESET# Interrupt Status */ +#define MCHP_ESPI_RST_ISTS_MASK 0x03u; +#define MCHP_ESPI_RST_ISTS_POS 0u +#define MCHP_ESPI_RST_ISTS BIT(MCHP_ESPI_RST_ISTS_POS) +#define MCHP_ESPI_RST_ISTS_PIN_RO_POS 1ul +#define MCHP_ESPI_RST_ISTS_PIN_RO_HI BIT(MCHP_ESPI_RST_ISTS_PIN_RO_POS) + +/* ESPI_RESET# Interrupt Enable */ +#define MCHP_ESPI_RST_IEN_MASK 0x01ul +#define MCHP_ESPI_RST_IEN 0x01ul + +/* eSPI Platform Reset Source */ +#define MCHP_ESPI_PLTRST_SRC_MASK 0x01ul +#define MCHP_ESPI_PLTRST_SRC_POS 0ul +#define MCHP_ESPI_PLTRST_SRC_IS_PIN 0x01ul +#define MCHP_ESPI_PLTRST_SRC_IS_VW 0x00ul + +/* VW Ready */ +#define MCHP_ESPI_VW_READY_MASK 0x01ul +#define MCHP_ESPI_VW_READY 0x01ul + +/* SAF Erase Block size */ +#define MCHP_ESPI_SERASE_SZ_1K_BITPOS 0 +#define MCHP_ESPI_SERASE_SZ_2K_BITPOS 1 +#define MCHP_ESPI_SERASE_SZ_4K_BITPOS 2 +#define MCHP_ESPI_SERASE_SZ_8K_BITPOS 3 +#define MCHP_ESPI_SERASE_SZ_16K_BITPOS 4 +#define MCHP_ESPI_SERASE_SZ_32K_BITPOS 5 +#define MCHP_ESPI_SERASE_SZ_64K_BITPOS 6 +#define MCHP_ESPI_SERASE_SZ_128K_BITPOS 7 +#define MCHP_ESPI_SERASE_SZ_1K BIT(0) +#define MCHP_ESPI_SERASE_SZ_2K BIT(1) +#define MCHP_ESPI_SERASE_SZ_4K BIT(2) +#define MCHP_ESPI_SERASE_SZ_8K BIT(3) +#define MCHP_ESPI_SERASE_SZ_16K BIT(4) +#define MCHP_ESPI_SERASE_SZ_32K BIT(5) +#define MCHP_ESPI_SERASE_SZ_64K BIT(6) +#define MCHP_ESPI_SERASE_SZ_128K BIT(7) +#define MCHP_ESPI_SERASE_SZ(bitpos) BIT((bitpos) + 10u) + +/* VW Error Status */ +#define MCHP_ESPI_VW_ERR_STS_MASK 0x33ul +#define MCHP_ESPI_VW_ERR_STS_FATAL_POS 0u +#define MCHP_ESPI_VW_ERR_STS_FATAL_RO \ + BIT(MCHP_ESPI_VW_ERR_STS_FATAL_POS) + +#define MCHP_ESPI_VW_ERR_STS_FATAL_CLR_POS 1u +#define MCHP_ESPI_VW_ERR_STS_FATAL_CLR_WO \ + BIT(MCHP_ESPI_VW_ERR_STS_FATAL_CLR_POS) + +#define MCHP_ESPI_VW_ERR_STS_NON_FATAL_POS 4u +#define MCHP_ESPI_VW_ERR_STS_NON_FATAL_RO \ + BIT(MCHP_ESPI_VW_ERR_STS_NON_FATAL_POS) + +#define MCHP_ESPI_VW_ERR_STS_NON_FATAL_CLR_POS 5u +#define MCHP_ESPI_VW_ERR_STS_NON_FATAL_CLR_WO \ + BIT(MCHP_ESPI_VW_ERR_STS_NON_FATAL_CLR_POS) + +/* VW Channel Enable Status */ +#define MCHP_ESPI_VW_EN_STS_MASK 0x01ul +#define MCHP_ESPI_VW_EN_STS_RO 0x01ul + +/* + * MCHP_ESPI_IO_PC - eSPI IO Peripheral Channel registers @ 0x400F3500 + */ + +/* Peripheral Channel Last Cycle length, type, and tag. */ +#define MCHP_ESPI_PC_LC_LEN_POS 0u +#define MCHP_ESPI_PC_LC_LEN_MASK0 0x0FFFul +#define MCHP_ESPI_PC_LC_LEN_MASK 0x0FFFul +#define MCHP_ESPI_PC_LC_TYPE_POS 12u +#define MCHP_ESPI_PC_LC_TYPE_MASK0 0xFFul +#define MCHP_ESPI_PC_LC_TYPE_MASK (0xFFul << 12) +#define MCHP_ESPI_PC_LC_TAG_POS 20u +#define MCHP_ESPI_PC_LC_TAG_MASK0 0x0Ful +#define MCHP_ESPI_PC_LC_TAG_MASK (0x0Ful << 20) + +/* + * Peripheral Channel Status + * Bus error, Channel enable change, and Bus master enable change. + */ +#define MCHP_ESPI_PC_STS_BUS_ERR_POS 16u /* RW1C */ +#define MCHP_ESPI_PC_STS_BUS_ERR BIT(MCHP_ESPI_PC_STS_BUS_ERR_POS) +#define MCHP_ESPI_PC_STS_EN_POS 24u /* RO */ +#define MCHP_ESPI_PC_STS_EN BIT(MCHP_ESPI_PC_STS_EN_POS) +#define MCHP_ESPI_PC_STS_EN_CHG_POS 25u /* RW1C */ +#define MCHP_ESPI_PC_STS_EN_CHG BIT(MCHP_ESPI_PC_STS_EN_CHG_POS) +#define MCHP_ESPI_PC_STS_BM_EN_POS 27u /* RO */ +#define MCHP_ESPI_PC_STS_BM_EN BIT(MCHP_ESPI_PC_STS_BM_EN_POS) +#define MCHP_ESPI_PC_STS_BM_EN_CHG_POS 28u /* RW1C */ +#define MCHP_ESPI_PC_STS_BM_EN_CHG BIT(MCHP_ESPI_PC_STS_BM_EN_CHG_POS) + +/* + * Peripheral Channel Interrupt Enables for + * Bus error, Channel enable change, and Bus master enable change. + * PC_LC_ADDR_LSW (@ 0x0000) Periph Chan Last Cycle address LSW + * PC_LC_ADDR_MSW (@ 0x0004) Periph Chan Last Cycle address MSW + * PC_LC_LEN_TYPE_TAG (@ 0x0008) Periph Chan Last Cycle length/type/tag + * PC_ERR_ADDR_LSW (@ 0x000C) Periph Chan Error Address LSW + * PC_ERR_ADDR_MSW (@ 0x0010) Periph Chan Error Address MSW + * PC_STATUS (@ 0x0014) Periph Chan Status + * PC_IEN (@ 0x0018) Periph Chan IEN + */ +#define MCHP_ESPI_PC_IEN_BUS_ERR_POS 16u +#define MCHP_ESPI_PC_IEN_BUS_ERR BIT(MCHP_ESPI_PC_IEN_BUS_ERR_POS) +#define MCHP_ESPI_PC_IEN_EN_CHG_POS 25u +#define MCHP_ESPI_PC_IEN_EN_CHG BIT(MCHP_ESPI_PC_IEN_BUS_ERR_POS) +#define MCHP_ESPI_PC_IEN_BM_EN_CHG_POS 28u +#define MCHP_ESPI_PC_IEN_BM_EN_CHG BIT(MCHP_ESPI_PC_IEN_BUS_ERR_POS) + +/*---- ESPI_IO_LTR - eSPI IO LTR registers ----*/ +#define MCHP_ESPI_LTR_STS_TX_DONE_POS 0u /* RW1C */ +#define MCHP_ESPI_LTR_STS_TX_DONE BIT(MCHP_ESPI_LTR_STS_TX_DONE_POS) +#define MCHP_ESPI_LTR_STS_OVRUN_POS 3u /* RW1C */ +#define MCHP_ESPI_LTR_STS_OVRUN BIT(MCHP_ESPI_LTR_STS_OVRUN_POS) +#define MCHP_ESPI_LTR_STS_HDIS_POS 4u /* RW1C */ +#define MCHP_ESPI_LTR_STS_HDIS BIT(MCHP_ESPI_LTR_STS_HDIS_POS) +#define MCHP_ESPI_LTR_STS_TX_BUSY_POS 8u /* RO */ +#define MCHP_ESPI_LTR_STS_TX_BUSY BIT(MCHP_ESPI_LTR_STS_TX_BUSY_POS) + +#define MCHP_ESPI_LTR_IEN_TX_DONE_POS 0u +#define MCHP_ESPI_LTR_IEN_TX_DONE BIT(MCHP_ESPI_LTR_IEN_TX_DONE_POS) + +#define MCHP_ESPI_LTR_CTRL_START_POS 0u +#define MCHP_ESPI_LTR_CTRL_START BIT(MCHP_ESPI_LTR_CTRL_START_POS) +#define MCHP_ESPI_LTR_CTRL_TAG_POS 8u +#define MCHP_ESPI_LTR_CTRL_TAG_MASK0 0x0Ful +#define MCHP_ESPI_LTR_CTRL_TAG_MASK \ + SHLU32(MCHP_ESPI_LTR_CTRL_TAG_MASK0, MCHP_ESPI_LTR_CTRL_TAG_POS) + +#define MCHP_ESPI_LTR_MSG_VAL_POS 0u +#define MCHP_ESPI_LTR_MSG_VAL_MASK0 0x3FFul +#define MCHP_ESPI_LTR_MSG_VAL_MASK \ + SHLU32(MCHP_ESPI_LTR_MSG_VAL_MASK0, MCHP_ESPI_LTR_MSG_VAL_POS) +#define MCHP_ESPI_LTR_MSG_SC_POS 10u +#define MCHP_ESPI_LTR_MSG_SC_MASK0 0x07ul +#define MCHP_ESPI_LTR_MSG_SC_MASK \ + SHLU32(MCHP_ESPI_LTR_MSG_SC_MASK0, MCHP_ESPI_LTR_MSG_SC_POS) +#define MCHP_ESPI_LTR_MSG_RT_POS 13u +#define MCHP_ESPI_LTR_MSG_RT_MASK0 0x03ul +#define MCHP_ESPI_LTR_MSG_RT_MASK \ + SHLU32(MCHP_ESPI_LTR_MSG_RT_MASK0, MCHP_ESPI_LTR_MSG_RT_POS) +/* eSPI specification indicates RT field must be 00b */ +#define MCHP_ESPI_LTR_MSG_RT_VAL 0u +#define MCHP_ESPI_LTR_MSG_REQ_POS 15u +/* inifinite latency(default) */ +#define MCHP_ESPI_LTR_MSG_REQ_INF 0u +/* latency computed from VAL and SC(scale) fields */ +#define MCHP_ESPI_LTR_MSG_REQ_VAL BIT(MCHP_ESPI_LTR_MSG_REQ_POS) + +/*---- ESPI_IO_OOB - eSPI IO OOB registers ----*/ +#define MCHP_ESPI_OOB_RX_ADDR_LSW_MASK 0xFFFFFFFCul +#define MCHP_ESPI_OOB_TX_ADDR_LSW_MASK 0xFFFFFFFCul + +/* OOB RX_LEN register */ +/* Number of bytes received (RO) */ +#define MCHP_ESPI_OOB_RX_LEN_POS 0u +#define MCHP_ESPI_OOB_RX_LEN_MASK 0x1FFFul +/* Recieve buffer length field (RW) */ +#define MCHP_ESPI_OOB_RX_BUF_LEN_POS 16u +#define MCHP_ESPI_OOB_RX_BUF_LEN_MASK0 0x1FFFul +#define MCHP_ESPI_OOB_RX_BUF_LEN_MASK \ + SHLU32(MCHP_ESPI_OOB_RX_BUF_LEN_MASK0, MCHP_ESPI_OOB_RX_BUF_LEN_POS) + +/* OOB TX_LEN register */ +#define MCHP_ESPI_OOB_TX_MSG_LEN_POS 0u +#define MCHP_ESPI_OOB_TX_MSG_LEN_MASK 0x1FFFul + +/* OOB RX_CTRL */ +/* Set AVAIL bit to indicate SRAM Buffer and size has been configured */ +#define MCHP_ESPI_OOB_RX_CTRL_AVAIL_POS 0u /* WO */ +#define MCHP_ESPI_OOB_RX_CTRL_AVAIL BIT(MCHP_ESPI_OOB_RX_CTRL_AVAIL_POS) +#define MCHP_ESPI_OOB_RX_CTRL_CHEN_POS 9u /* RO */ +#define MCHP_ESPI_OOB_RX_CTRL_CHEN BIT(MCHP_ESPI_OOB_RX_CTRL_CHEN_POS) +/* Copy of eSPI OOB Capabilities max. payload size */ +#define MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_POS 16u /* RO */ +#define MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_MASK0 0x07u +#define MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_MASK \ + SHLU32(MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_MASK0, \ + MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_POS) + +/* OOB RX_IEN */ +#define MCHP_ESPI_OOB_RX_IEN_POS 0u +#define MCHP_ESPI_OOB_RX_IEN BIT(MCHP_ESPI_OOB_RX_IEN_POS) + +/* OOB RX_STS */ +#define MCHP_ESPI_OOB_RX_STS_DONE_POS 0u /* RW1C */ +#define MCHP_ESPI_OOB_RX_STS_DONE BIT(MCHP_ESPI_OOB_RX_STS_DONE_POS) +#define MCHP_ESPI_OOB_RX_STS_IBERR_POS 1u /* RW1C */ +#define MCHP_ESPI_OOB_RX_STS_IBERR BIT(MCHP_ESPI_OOB_RX_STS_IBERR_POS) +#define MCHP_ESPI_OOB_RX_STS_OVRUN_POS 2u /* RW1C */ +#define MCHP_ESPI_OOB_RX_STS_OVRUN BIT(MCHP_ESPI_OOB_RX_STS_OVRUN_POS) +#define MCHP_ESPI_OOB_RX_STS_RXEN_POS 3u /* RO */ +#define MCHP_ESPI_OOB_RX_STS_RXEN BIT(MCHP_ESPI_OOB_RX_STS_RXEN_POS) +#define MCHP_ESPI_OOB_RX_STS_TAG_POS 8u /* RO */ +#define MCHP_ESPI_OOB_RX_STS_TAG_MASK0 0x0Ful +#define MCHP_ESPI_OOB_RX_STS_TAG_MASK \ + SHLU32(MCHP_ESPI_OOB_RX_STS_TAG_MASK0, MCHP_ESPI_OOB_RX_STS_TAG_POS) + +#define MCHP_ESPI_OOB_RX_STS_ALL_RW1C 0x07ul +#define MCHP_ESPI_OOB_RX_STS_ALL 0x0Ful + +/* OOB TX_CTRL */ +#define MCHP_ESPI_OOB_TX_CTRL_START_POS 0u /* WO */ +#define MCHP_ESPI_OOB_TX_CTRL_START BIT(MCHP_ESPI_OOB_TX_CTRL_START_POS) +#define MCHP_ESPI_OOB_TX_CTRL_TAG_POS 8u /* RW */ +#define MCHP_ESPI_OOB_TX_CTRL_TAG_MASK0 0x0Ful +#define MCHP_ESPI_OOB_TX_CTRL_TAG_MASK \ + SHLU32(MCHP_ESPI_OOB_TX_CTRL_TAG_MASK0, MCHP_ESPI_OOB_TX_CTRL_TAG_POS) + +/* OOB TX_IEN */ +#define MCHP_ESPI_OOB_TX_IEN_DONE_POS 0u +#define MCHP_ESPI_OOB_TX_IEN_DONE BIT(MCHP_ESPI_OOB_TX_IEN_DONE_POS) +#define MCHP_ESPI_OOB_TX_IEN_CHG_EN_POS 1u +#define MCHP_ESPI_OOB_TX_IEN_CHG_EN BIT(MCHP_ESPI_OOB_TX_IEN_CHG_EN_POS) +#define MCHP_ESPI_OOB_TX_IEN_ALL 0x03ul + +/* OOB TX_STS */ +#define MCHP_ESPI_OOB_TX_STS_DONE_POS 0u /* RW1C */ +#define MCHP_ESPI_OOB_TX_STS_DONE BIT(MCHP_ESPI_OOB_TX_STS_DONE_POS) +#define MCHP_ESPI_OOB_TX_STS_CHG_EN_POS 1u /* RW1C */ +#define MCHP_ESPI_OOB_TX_STS_CHG_EN BIT(MCHP_ESPI_OOB_TX_STS_CHG_EN_POS) +#define MCHP_ESPI_OOB_TX_STS_IBERR_POS 2u /* RW1C */ +#define MCHP_ESPI_OOB_TX_STS_IBERR BIT(MCHP_ESPI_OOB_TX_STS_IBERR_POS) +#define MCHP_ESPI_OOB_TX_STS_OVRUN_POS 3u /* RW1C */ +#define MCHP_ESPI_OOB_TX_STS_OVRUN BIT(MCHP_ESPI_OOB_TX_STS_OVRUN_POS) +#define MCHP_ESPI_OOB_TX_STS_BADREQ_POS 5u /* RW1C */ +#define MCHP_ESPI_OOB_TX_STS_BADREQ BIT(MCHP_ESPI_OOB_TX_STS_BADREQ_POS) +#define MCHP_ESPI_OOB_TX_STS_BUSY_POS 8u /* RO */ +#define MCHP_ESPI_OOB_TX_STS_BUSY BIT(MCHP_ESPI_OOB_TX_STS_BUSY_POS) +/* Read-only copy of OOB Channel Enabled bit */ +#define MCHP_ESPI_OOB_TX_STS_CHEN_POS 9u /* RO */ +#define MCHP_ESPI_OOB_TX_STS_CHEN BIT(MCHP_ESPI_OOB_TX_STS_CHEN_POS) + +#define MCHP_ESPI_OOB_TX_STS_ALL_RW1C 0x2Ful + +/*---- MCHP_ESPI_IO_FC - eSPI IO Flash channel registers ----*/ +/* FC MEM_ADDR_LSW */ +#define MCHP_ESPI_FC_MEM_ADDR_LSW_MASK 0xFFFFFFFCul + +/* FC CTRL */ +#define MCHP_ESPI_FC_CTRL_START_POS 0u /* WO */ +#define MCHP_ESPI_FC_CTRL_START BIT(MCHP_ESPI_FC_CTRL_START_POS) +#define MCHP_ESPI_FC_CTRL_FUNC_POS 2u /* RW */ +#define MCHP_ESPI_FC_CTRL_FUNC_MASK0 0x03ul +#define MCHP_ESPI_FC_CTRL_FUNC_MASK \ + SHLU32(MCHP_ESPI_FC_CTRL_FUNC_MASK0, MCHP_ESPI_FC_CTRL_FUNC_POS) +#define MCHP_ESPI_FC_CTRL_RD0 0x00ul +#define MCHP_ESPI_FC_CTRL_WR0 0x01ul +#define MCHP_ESPI_FC_CTRL_ERS0 0x02ul +#define MCHP_ESPI_FC_CTRL_ERL0 0x03ul +#define MCHP_ESPI_FC_CTRL_FUNC(f) \ + ((uint32_t)(f) & MCHP_ESPI_FC_CTRL_FUNC_MASK) + +#define MCHP_ESPI_FC_CTRL_TAG_POS 4u +#define MCHP_ESPI_FC_CTRL_TAG_MASK0 0x0Ful +#define MCHP_ESPI_FC_CTRL_TAG_MASK \ + SHLU32(MCHP_ESPI_FC_CTRL_TAG_MASK0, MCHP_ESPI_FC_CTRL_TAG_POS) + +#define MCHP_ESPI_FC_CTRL_TAG(t) \ + ((uint32_t)(t) & MCHP_ESPI_FC_CTRL_TAG_MASK) + +#define MCHP_ESPI_FC_CTRL_ABORT_POS 16u /* WO */ +#define MCHP_ESPI_FC_CTRL_ABORT BIT(MCHP_ESPI_FC_CTRL_ABORT_POS) + +/* FC IEN */ +#define MCHP_ESPI_FC_IEN_DONE_POS 0u +#define MCHP_ESPI_FC_IEN_DONE BIT(MCHP_ESPI_FC_IEN_DONE_POS) +#define MCHP_ESPI_FC_IEN_CHG_EN_POS 1u +#define MCHP_ESPI_FC_IEN_CHG_EN BIT(MCHP_ESPI_FC_IEN_CHG_EN_POS) + +/* FC CFG */ +#define MCHP_ESPI_FC_CFG_BUSY_POS 0u /* RO */ +#define MCHP_ESPI_FC_CFG_BUSY BIT(MCHP_ESPI_FC_CFG_BUSY_POS) +#define MCHP_ESPI_FC_CFG_ERBSZ_POS 2u /* RO */ +#define MCHP_ESPI_FC_CFG_ERBSZ_MASK0 0x07ul +#define MCHP_ESPI_FC_CFG_ERBSZ_MASK \ + SHLU32(MCHP_ESPI_FC_CFG_ERBSZ_MASK0, MCHP_ESPI_FC_CFG_ERBSZ_POS) +#define MCHP_ESPI_FC_CFG_ERBSZ_4K \ + SHLU32(0x01ul, MCHP_ESPI_FC_CFG_ERBSZ_POS) +#define MCHP_ESPI_FC_CFG_ERBSZ_64K \ + SHLU32(0x02ul, MCHP_ESPI_FC_CFG_ERBSZ_POS) +#define MCHP_ESPI_FC_CFG_ERBSZ_4K_64K \ + SHLU32(0x03ul, MCHP_ESPI_FC_CFG_ERBSZ_POS) +#define MCHP_ESPI_FC_CFG_ERBSZ_128K \ + SHLU32(0x04ul, MCHP_ESPI_FC_CFG_ERBSZ_POS) +#define MCHP_ESPI_FC_CFG_ERBSZ_256K \ + SHLU32(0x05ul, MCHP_ESPI_FC_CFG_ERBSZ_POS) +#define MCHP_ESPI_FC_CFG_MAXPLD_POS 8u /* RO */ +#define MCHP_ESPI_FC_CFG_MAXPLD_MASK0 0x07ul +#define MCHP_ESPI_FC_CFG_MAXPLD_MASK \ + SHLU32(MCHP_ESPI_FC_CFG_MAXPLD_MASK0, MCHP_ESPI_FC_CFG_MAXPLD_POS) +#define MCHP_ESPI_FC_CFG_MAXPLD_64B \ + SHLU32(0x01ul, MCHP_ESPI_FC_CFG_MAXPLD_POS) +#define MCHP_ESPI_FC_CFG_MAXPLD_128B \ + SHLU32(0x02ul, MCHP_ESPI_FC_CFG_MAXPLD_POS) +#define MCHP_ESPI_FC_CFG_MAXPLD_256B \ + SHLU32(0x03ul, MCHP_ESPI_FC_CFG_MAXPLD_POS) +#define MCHP_ESPI_FC_CFG_SAFS_SEL_POS 11u +#define MCHP_ESPI_FC_CFG_SAFS_SEL BIT(MCHP_ESPI_FC_CFG_SAFS_SEL_POS) +#define MCHP_ESPI_FC_CFG_MAXRD_POS 12u /* RO */ +#define MCHP_ESPI_FC_CFG_MAXRD_MASK0 0x07ul +#define MCHP_ESPI_FC_CFG_MAXRD_MASK \ + SHLU32(MCHP_ESPI_FC_CFG_MAXRD_MASK0, MCHP_ESPI_FC_CFG_MAXRD_POS) +#define MCHP_ESPI_FC_CFG_MAXRD_64B \ + SHLU32(0x01ul, MCHP_ESPI_FC_CFG_MAXRD_POS) +#define MCHP_ESPI_FC_CFG_MAXRD_128B \ + SHLU32(0x02ul, MCHP_ESPI_FC_CFG_MAXRD_POS) +#define MCHP_ESPI_FC_CFG_MAXRD_256B \ + SHLU32(0x03ul, MCHP_ESPI_FC_CFG_MAXRD_POS) +#define MCHP_ESPI_FC_CFG_MAXRD_512B \ + SHLU32(0x04ul, MCHP_ESPI_FC_CFG_MAXRD_POS) +#define MCHP_ESPI_FC_CFG_MAXRD_1K \ + SHLU32(0x05ul, MCHP_ESPI_FC_CFG_MAXRD_POS) +#define MCHP_ESPI_FC_CFG_MAXRD_2K \ + SHLU32(0x06ul, MCHP_ESPI_FC_CFG_MAXRD_POS) +#define MCHP_ESPI_FC_CFG_MAXRD_4K \ + SHLU32(0x07ul, MCHP_ESPI_FC_CFG_MAXRD_POS) +#define MCHP_ESPI_FC_CFG_FORCE_MS_POS 28u /* RW */ +#define MCHP_ESPI_FC_CFG_FORCE_MS_MASK0 0x03ul +#define MCHP_ESPI_FC_CFG_FORCE_MS_MASK \ + SHLU32(MCHP_ESPI_FC_CFG_FORCE_MS_MASK0, MCHP_ESPI_FC_CFG_FORCE_MS_POS) +/* Host (eSPI Master) can select MAFS or SAFS */ +#define MCHP_ESPI_FC_CFG_FORCE_NONE 0ul +/* EC forces eSPI slave HW to only allow MAFS */ +#define MCHP_ESPI_FC_CFG_FORCE_MAFS \ + SHLU32(0x02ul, MCHP_ESPI_FC_CFG_FORCE_MS_POS) +/* EC forces eSPI slave HW to only allow SAFS */ +#define MCHP_ESPI_FC_CFG_FORCE_SAFS \ + SHLU32(0x03ul, MCHP_ESPI_FC_CFG_FORCE_MS_POS) + +/* FC STS */ +#define MCHP_ESPI_FC_STS_CHAN_EN_POS 0u /* RO */ +#define MCHP_ESPI_FC_STS_CHAN_EN BIT(MCHP_ESPI_FC_STS_CHAN_EN_POS) + +#define MCHP_ESPI_FC_STS_CHAN_EN_CHG_POS 1u /* RW1C */ +#define MCHP_ESPI_FC_STS_CHAN_EN_CHG BIT(MCHP_ESPI_FC_STS_CHAN_EN_CHG_POS) + +#define MCHP_ESPI_FC_STS_DONE_POS 2u /* RW1C */ +#define MCHP_ESPI_FC_STS_DONE BIT(MCHP_ESPI_FC_STS_DONE_POS) +#define MCHP_ESPI_FC_STS_MDIS_POS 3u /* RW1C */ +#define MCHP_ESPI_FC_STS_MDIS BIT(MCHP_ESPI_FC_STS_MDIS_POS) +#define MCHP_ESPI_FC_STS_IBERR_POS 4u /* RW1C */ +#define MCHP_ESPI_FC_STS_IBERR BIT(MCHP_ESPI_FC_STS_IBERR_POS) +#define MCHP_ESPI_FC_STS_ABS_POS 5u /* RW1C */ +#define MCHP_ESPI_FC_STS_ABS BIT(MCHP_ESPI_FC_STS_ABS_POS) +#define MCHP_ESPI_FC_STS_OVRUN_POS 6u /* RW1C */ +#define MCHP_ESPI_FC_STS_OVRUN BIT(MCHP_ESPI_FC_STS_OVRUN_POS) +#define MCHP_ESPI_FC_STS_INC_POS 7u /* RW1C */ +#define MCHP_ESPI_FC_STS_INC BIT(MCHP_ESPI_FC_STS_INC_POS) +#define MCHP_ESPI_FC_STS_FAIL_POS 8u /* RW1C */ +#define MCHP_ESPI_FC_STS_FAIL BIT(MCHP_ESPI_FC_STS_FAIL_POS) +#define MCHP_ESPI_FC_STS_OVFL_POS 9u /* RW1C */ +#define MCHP_ESPI_FC_STS_OVFL BIT(MCHP_ESPI_FC_STS_OVFL_POS) +#define MCHP_ESPI_FC_STS_BADREQ_POS 11u /* RW1C */ +#define MCHP_ESPI_FC_STS_BADREQ BIT(MCHP_ESPI_FC_STS_BADREQ_POS) + +#define MCHP_ESPI_FC_STS_ALL_RW1C 0x0BFEul + +/*---- MCHP_ESPI_IO_BAR_HOST - eSPI IO Host visible BAR registers ----*/ + +/* + * IOBAR_INH_LSW/MSW 64-bit register: each bit = 1 inhibits an I/O BAR + * independent of the BAR's Valid bit. + * Logical Device Number = bit position. + */ +#define MCHP_ESPI_IOBAR_LDN_MBOX 0x00u +#define MCHP_ESPI_IOBAR_LDN_KBC 0x01u +#define MCHP_ESPI_IOBAR_LDN_ACPI_EC_0 0x02u +#define MCHP_ESPI_IOBAR_LDN_ACPI_EC_1 0x03u +#define MCHP_ESPI_IOBAR_LDN_ACPI_EC_2 0x04u +#define MCHP_ESPI_IOBAR_LDN_ACPI_EC_3 0x05u +#define MCHP_ESPI_IOBAR_LDN_ACPI_EC_4 0x06u +#define MCHP_ESPI_IOBAR_LDN_ACPI_PM1 0x07u +#define MCHP_ESPI_IOBAR_LDN_PORT92 0x08u +#define MCHP_ESPI_IOBAR_LDN_UART_0 0x09u +#define MCHP_ESPI_IOBAR_LDN_UART_1 0x0Au +#define MCHP_ESPI_IOBAR_LDN_IOC 0x0Du +#define MCHP_ESPI_IOBAR_LDN_MEM 0x0Eu +#define MCHP_ESPI_IOBAR_LDN_GLUE_LOG 0x0Fu +#define MCHP_ESPI_IOBAR_LDN_EMI_0 0x10u +#define MCHP_ESPI_IOBAR_LDN_EMI_1 0x11u +#define MCHP_ESPI_IOBAR_LDN_EMI_2 0x12u +#define MCHP_ESPI_IOBAR_LDN_RTC 0x14u +#define MCHP_ESPI_IOBAR_LDN_P80CAP_0 0x20u /* BDP Port80 Capture */ +#define MCHP_ESPI_IOBAR_LDN_P80CAP_1 0x21u /* BDP Alias Capture */ +#define MCHP_ESPI_IOBAR_LDN_T32B 0x2Fu +#define MCHP_ESPI_IOBAR_LDN_LASIC 0x30u + +/* + * IOBAR_INIT: Default address of I/O Plug and Play Super-IO index/data + * configuration registers. (Defaults to 0x2E/0x2F) + */ +#define MCHP_ESPI_IOBAR_INIT_DFLT 0x2Eul + +/* + * EC_IRQ: A write to bit[0] triggers EC SERIRQ. The actual + * SERIRQ slot is configured in MCHP_ESPI_IO_SIRQ.EC_SIRQ + */ +#define MCHP_ESPI_EC_IRQ_GEN (1ul << 0) + +/* 32-bit Host IO BAR */ +#define MCHP_ESPI_IO_BAR_HOST_VALID_POS 0u +#define MCHP_ESPI_IO_BAR_HOST_VALID \ + BIT(MCHP_ESPI_IO_BAR_HOST_VALID_POS) +#define MCHP_ESPI_IO_BAR_HOST_ADDR_POS 16u +#define MCHP_ESPI_IO_BAR_HOST_ADDR_MASK0 0xFFFFul +#define MCHP_ESPI_IO_BAR_HOST_ADDR_MASK 0xFFFF0000ul + +/* Offsets from first SIRQ */ +#define MCHP_ESPI_SIRQ_MBOX_SIRQ 0ul +#define MCHP_ESPI_SIRQ_MBOX_SMI 1ul +#define MCHP_ESPI_SIRQ_KBC_KIRQ 2ul +#define MCHP_ESPI_SIRQ_KBC_MIRQ 3ul +#define MCHP_ESPI_SIRQ_ACPI_EC0 4ul +#define MCHP_ESPI_SIRQ_ACPI_EC1 5ul +#define MCHP_ESPI_SIRQ_ACPI_EC2 6ul +#define MCHP_ESPI_SIRQ_ACPI_EC3 7ul +#define MCHP_ESPI_SIRQ_ACPI_EC4 8ul +#define MCHP_ESPI_SIRQ_UART0 9ul +#define MCHP_ESPI_SIRQ_UART1 10ul +#define MCHP_ESPI_SIRQ_EMI0_HOST 11ul +#define MCHP_ESPI_SIRQ_EMI0_E2H 12ul +#define MCHP_ESPI_SIRQ_EMI1_HOST 13ul +#define MCHP_ESPI_SIRQ_EMI1_E2H 14ul +#define MCHP_ESPI_SIRQ_EMI2_HOST 15ul +#define MCHP_ESPI_SIRQ_EMI2_E2H 16ul +#define MCHP_ESPI_SIRQ_RTC 17ul +#define MCHP_ESPI_SIRQ_EC 18ul +#define MCHP_ESPI_SIRQ_RSVD19 19ul +#define MCHP_ESPI_SIRQ_MAX 20ul + +/* + * Values for Logical Device SIRQ registers. + * Unless disabled each logical device must have a unique value + * programmed to its SIRQ register. + * Values 0x00u through 0x7Fu are sent using VWire host index 0x00 + * Values 0x80h through 0xFEh are sent using VWire host index 0x01 + * All registers reset default is 0xFFu (disabled). + */ +#define MCHP_ESPI_IO_SIRQ_DIS 0xFFu + +/* Interfaces to any C modules */ +#ifdef __cplusplus +extern "C" { +#endif + +/* Array indices for eSPI IO BAR Host and EC-only register structures */ +enum espi_io_bar_idx { + IOB_IOC = 0, + IOB_MEM, + IOB_MBOX, + IOB_KBC, + IOB_ACPI_EC0, + IOB_ACPI_EC1, + IOB_ACPI_EC2, + IOB_ACPI_EC3, + IOB_ACPI_EC4, + IOB_ACPI_PM1, + IOB_PORT92, + IOB_UART0, + IOB_UART1, + IOB_EMI0, + IOB_EMI1, + IOB_EMI2, + IOB_P80BD, + IOB_P80BD_ALIAS, + IOB_RTC, + IOB_RSVD19, + IOB_T32B, + IOB_RSVD21, + IOB_GLUE, + IOB_MAX +}; + +/** @brief Serial IRQ byte register indices */ +enum espi_io_sirq_idx { + SIRQ_MBOX = 0, SIRQ_MBOX_SMI, SIRQ_KBC_KIRQ, + SIRQ_KBC_MIRQ, SIRQ_ACPI_EC0_OBF, SIRQ_ACPI_EC1_OBF, + SIRQ_ACPI_EC2_OBF, SIRQ_ACPI_EC3_OBF, SIRQ_ACPI_EC4_OBF, + SIRQ_UART0, SIRQ_UART1, SIRQ_EMI0_HEV, + SIRQ_EMI0_E2H, SIRQ_EMI1_HEV, SIRQ_EMI1_E2H, + SIRQ_EMI2_HEV, SIRQ_EMI2_E2H, SIRQ_RTC, + SIRQ_EC, SIRQ_MAX +}; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _COMPONENT_ESPI_IO_H */ +/* end espi_io.h */ +/** @} + */ diff --git a/mec/mec172x/component/espi_mem.h b/mec/mec172x/component/espi_mem.h new file mode 100644 index 0000000..d723663 --- /dev/null +++ b/mec/mec172x/component/espi_mem.h @@ -0,0 +1,358 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file espi_mem.h + * MEC172x eSPI Memory Component definitions + */ +/** @defgroup MEC172x Peripherals eSPI MEM + */ + +#ifndef _COMPONENT_ESPI_MEM_H +#define _COMPONENT_ESPI_MEM_H + +#include +#include + +#include +#include + +/* eSPI Memory Component Bus Master registers @ 0x400F3A00 */ + +/* BM_STS */ +#define MCHP_ESPI_BM_STS_DONE_1_POS 0u /* RW1C */ +#define MCHP_ESPI_BM_STS_DONE_1 BIT(MCHP_ESPI_BM_STS_DONE_1_POS) +#define MCHP_ESPI_BM_STS_BUSY_1_POS 1u /* RO */ +#define MCHP_ESPI_BM_STS_BUSY_1 BIT(MCHP_ESPI_BM_STS_BUSY_1_POS) +#define MCHP_ESPI_BM_STS_AB_EC_1_POS 2u /* RW1C */ +#define MCHP_ESPI_BM_STS_AB_EC_1 BIT(MCHP_ESPI_BM_STS_AB_EC_1_POS) +#define MCHP_ESPI_BM_STS_AB_HOST_1_POS 3u /* RW1C */ +#define MCHP_ESPI_BM_STS_AB_HOST_1 BIT(MCHP_ESPI_BM_STS_AB_HOST_1_POS) +#define MCHP_ESPI_BM_STS_AB_CH2_1_POS 4u /* RW1C */ +#define MCHP_ESPI_BM_STS_CH2_AB_1 BIT(MCHP_ESPI_BM_STS_AB_CH2_1_POS) +#define MCHP_ESPI_BM_STS_OVFL_1_POS 5u /* RW1C */ +#define MCHP_ESPI_BM_STS_OVFL_1_CH2 BIT(MCHP_ESPI_BM_STS_OVFL_1_POS) +#define MCHP_ESPI_BM_STS_OVRUN_1_POS 6u /* RW1C */ +#define MCHP_ESPI_BM_STS_OVRUN_1_CH2 BIT(MCHP_ESPI_BM_STS_OVRUN_1_POS) +#define MCHP_ESPI_BM_STS_INC_1_POS 7u /* RW1C */ +#define MCHP_ESPI_BM_STS_INC_1 BIT(MCHP_ESPI_BM_STS_INC_1_POS) +#define MCHP_ESPI_BM_STS_FAIL_1_POS 8u /* RW1C */ +#define MCHP_ESPI_BM_STS_FAIL_1 BIT(MCHP_ESPI_BM_STS_FAIL_1_POS) +#define MCHP_ESPI_BM_STS_IBERR_1_POS 9u /* RW1C */ +#define MCHP_ESPI_BM_STS_IBERR_1 BIT(MCHP_ESPI_BM_STS_IBERR_1_POS) +#define MCHP_ESPI_BM_STS_BADREQ_1_POS 11u /* RW1C */ +#define MCHP_ESPI_BM_STS_BADREQ_1 BIT(MCHP_ESPI_BM_STS_BADREQ_1_POS) +#define MCHP_ESPI_BM_STS_DONE_2_POS 16u /* RW1C */ +#define MCHP_ESPI_BM_STS_DONE_2 BIT(MCHP_ESPI_BM_STS_DONE_2_POS) +#define MCHP_ESPI_BM_STS_BUSY_2_POS 17u /* RO */ +#define MCHP_ESPI_BM_STS_BUSY_2 BIT(MCHP_ESPI_BM_STS_BUSY_2_POS) +#define MCHP_ESPI_BM_STS_AB_EC_2_POS 18u /* RW1C */ +#define MCHP_ESPI_BM_STS_AB_EC_2 BIT(MCHP_ESPI_BM_STS_AB_EC_2_POS) +#define MCHP_ESPI_BM_STS_AB_HOST_2_POS 19u /* RW1C */ +#define MCHP_ESPI_BM_STS_AB_HOST_2 BIT(MCHP_ESPI_BM_STS_AB_HOST_2_POS) +#define MCHP_ESPI_BM_STS_AB_CH1_2_POS 20u /* RW1C */ +#define MCHP_ESPI_BM_STS_AB_CH1_2 BIT(MCHP_ESPI_BM_STS_AB_CH1_2_POS) +#define MCHP_ESPI_BM_STS_OVFL_2_POS 21u /* RW1C */ +#define MCHP_ESPI_BM_STS_OVFL_2_CH2 BIT(MCHP_ESPI_BM_STS_OVFL_2_POS) +#define MCHP_ESPI_BM_STS_OVRUN_2_POS 22u /* RW1C */ +#define MCHP_ESPI_BM_STS_OVRUN_CH2_2 BIT(MCHP_ESPI_BM_STS_OVRUN_2_POS) +#define MCHP_ESPI_BM_STS_INC_2_POS 23u /* RW1C */ +#define MCHP_ESPI_BM_STS_INC_2 BIT(MCHP_ESPI_BM_STS_INC_2_POS) +#define MCHP_ESPI_BM_STS_FAIL_2_POS 24u /* RW1C */ +#define MCHP_ESPI_BM_STS_FAIL_2 BIT(MCHP_ESPI_BM_STS_FAIL_2_POS) +#define MCHP_ESPI_BM_STS_IBERR_2_POS 25u /* RW1C */ +#define MCHP_ESPI_BM_STS_IBERR_2 BIT(MCHP_ESPI_BM_STS_IBERR_2_POS) +#define MCHP_ESPI_BM_STS_BADREQ_2_POS 27u /* RW1C */ +#define MCHP_ESPI_BM_STS_BADREQ_2 BIT(MCHP_ESPI_BM_STS_BADREQ_2_POS) + +#define MCHP_ESPI_BM_STS_ALL_RW1C_1 0x0BFDul +#define MCHP_ESPI_BM_STS_ALL_RW1C_2 0x0BFD0000ul + +/* BM_IEN */ +#define MCHP_ESPI_BM1_IEN_DONE_POS 0u +#define MCHP_ESPI_BM1_IEN_DONE BIT(MCHP_ESPI_BM1_IEN_DONE_POS) +#define MCHP_ESPI_BM2_IEN_DONE_POS 16u +#define MCHP_ESPI_BM2_IEN_DONE BIT(MCHP_ESPI_BM2_IEN_DONE_POS) + +/* BM_CFG */ +#define MCHP_ESPI_BM1_CFG_TAG_POS 0u +#define MCHP_ESPI_BM1_CFG_TAG_MASK0 0x0Ful +#define MCHP_ESPI_BM1_CFG_TAG_MASK 0x0Ful +#define MCHP_ESPI_BM2_CFG_TAG_POS 16u +#define MCHP_ESPI_BM2_CFG_TAG_MASK0 0x0Ful +#define MCHP_ESPI_BM2_CFG_TAG_MASK 0x0F0000ul + +/* BM1_CTRL */ +#define MCHP_ESPI_BM1_CTRL_START_POS 0u /* WO */ +#define MCHP_ESPI_BM1_CTRL_START BIT(MCHP_ESPI_BM1_CTRL_START_POS) +#define MCHP_ESPI_BM1_CTRL_ABORT_POS 1u /* WO */ +#define MCHP_ESPI_BM1_CTRL_ABORT BIT(MCHP_ESPI_BM1_CTRL_ABORT_POS) +#define MCHP_ESPI_BM1_CTRL_EN_INC_POS 2u /* RW */ +#define MCHP_ESPI_BM1_CTRL_EN_INC BIT(MCHP_ESPI_BM1_CTRL_EN_INC_POS) +#define MCHP_ESPI_BM1_CTRL_WAIT_NB2_POS 3u /* RW */ +#define MCHP_ESPI_BM1_CTRL_WAIT_NB2 BIT(MCHP_ESPI_BM1_CTRL_WAIT_NB2_POS) +#define MCHP_ESPI_BM1_CTRL_CTYPE_POS 8u +#define MCHP_ESPI_BM1_CTRL_CTYPE_MASK0 0x03ul +#define MCHP_ESPI_BM1_CTRL_CTYPE_MASK \ + SHLU32(MCHP_ESPI_BM1_CTRL_CTYPE_MASK0, MCHP_ESPI_BM1_CTRL_CTYPE_POS) +#define MCHP_ESPI_BM1_CTRL_CTYPE_RD_ADDR32 0x00ul +#define MCHP_ESPI_BM1_CTRL_CTYPE_WR_ADDR32 \ + SHLU32(0x01ul, MCHP_ESPI_BM1_CTRL_CTYPE_POS) +#define MCHP_ESPI_BM1_CTRL_CTYPE_RD_ADDR64 \ + SHLU32(0x02ul, MCHP_ESPI_BM1_CTRL_CTYPE_POS) +#define MCHP_ESPI_BM1_CTRL_CTYPE_WR_ADDR64 \ + SHLU32(0x03ul, MCHP_ESPI_BM1_CTRL_CTYPE_POS) +#define MCHP_ESPI_BM1_CTRL_LEN_POS 16u +#define MCHP_ESPI_BM1_CTRL_LEN_MASK0 0x1FFFul +#define MCHP_ESPI_BM1_CTRL_LEN_MASK 0x1FFF0000ul + +/* BM1_EC_ADDR_LSW */ +#define MCHP_ESPI_BM1_EC_ADDR_LSW_MASK 0xFFFFFFFCul + +/* BM2_CTRL */ +#define MCHP_ESPI_BM2_CTRL_START_POS 0u /* WO */ +#define MCHP_ESPI_BM2_CTRL_START BIT(MCHP_ESPI_BM2_CTRL_START_POS) +#define MCHP_ESPI_BM2_CTRL_ABORT_POS 1u /* WO */ +#define MCHP_ESPI_BM2_CTRL_ABORT BIT(MCHP_ESPI_BM2_CTRL_ABORT_POS) +#define MCHP_ESPI_BM2_CTRL_EN_INC_POS 2u /* RW */ +#define MCHP_ESPI_BM2_CTRL_EN_INC BIT(MCHP_ESPI_BM2_CTRL_EN_INC_POS) +#define MCHP_ESPI_BM2_CTRL_WAIT_NB2_POS 3u /* RW */ +#define MCHP_ESPI_BM2_CTRL_WAIT_NB2 BIT(MCHP_ESPI_BM2_CTRL_WAIT_NB2_POS) +#define MCHP_ESPI_BM2_CTRL_CTYPE_POS 8u +#define MCHP_ESPI_BM2_CTRL_CTYPE_MASK0 0x03ul +#define MCHP_ESPI_BM2_CTRL_CTYPE_MASK 0x0300ul +#define MCHP_ESPI_BM2_CTRL_CTYPE_RD_ADDR32 0x00ul +#define MCHP_ESPI_BM2_CTRL_CTYPE_WR_ADDR32 0x0100ul +#define MCHP_ESPI_BM2_CTRL_CTYPE_RD_ADDR64 0x0200ul +#define MCHP_ESPI_BM2_CTRL_CTYPE_WR_ADDR64 0x0300ul +#define MCHP_ESPI_BM2_CTRL_LEN_POS 16u +#define MCHP_ESPI_BM2_CTRL_LEN_MASK0 0x1FFFul +#define MCHP_ESPI_BM2_CTRL_LEN_MASK 0x1FFF0000ul + +/* BM2_EC_ADDR_LSW */ +#define MCHP_ESPI_BM2_EC_ADDR_LSW_MASK 0xFFFFFFFCul + +/* + * MCHP_ESPI_MEM_BAR_EC @ 0x400F3930 + * + * Half-word H0 of each EC Memory BAR contains + * Memory BAR memory address mask bits in bits[7:0] + * Logical Device Number in bits[13:8] + */ +#define MCHP_ESPI_EBAR_H0_MEM_MASK_POS 0u +#define MCHP_ESPI_EBAR_H0_MEM_MASK_MASK 0xFFul +#define MCHP_ESPI_EBAR_H0_LDN_POS 8u +#define MCHP_ESPI_EBAR_H0_LDN_MASK0 0x3Ful +#define MCHP_ESPI_EBAR_H0_LDN_MASK 0x3F00ul + +/* + * MCHP_ESPI_MEM_BAR_HOST @ 0x400F3B30 + * + * Each Host BAR contains: + * bit[0] (RW) = Valid bit + * bits[15:1] = Reserved, read-only 0 + * bits[47:16] (RW) = bits[31:0] of the Host Memory address. + */ + +/* Memory BAR Host address valid */ +#define MCHP_ESPI_HBAR_VALID_POS 0u +#define MCHP_ESPI_HBAR_VALID_MASK 0x01ul +/* + * Host address is in bits[47:16] of the HBAR + * HBAR's are spaced every 10 bytes (80 bits) but + * only implement bits[47:0] + */ +#define MCHP_ESPI_HBAR_VALID_OFS 0x00u /* byte 0 */ +/* 32-bit Host Address */ +#define MCHP_ESPI_HBAR_ADDR_B0_OFS 0x02u /* byte 2 */ +#define MCHP_ESPI_HBAR_ADDR_B1_OFS 0x03u /* byte 3 */ +#define MCHP_ESPI_HBAR_ADDR_B2_OFS 0x04u /* byte 4 */ +#define MCHP_ESPI_HBAR_ADDR_B3_OFS 0x05u /* byte 5 */ + +#define MCHP_EC_SRAM_BAR_H0_VALID_POS 0u +#define MCHP_EC_SRAM_BAR_H0_VALID_MASK0 0x01ul +#define MCHP_EC_SRAM_BAR_H0_VALID_MASK 0x01ul +#define MCHP_EC_SRAM_BAR_H0_VALID 0x01ul +#define MCHP_EC_SRAM_BAR_H0_ACCESS_POS 1u +#define MCHP_EC_SRAM_BAR_H0_ACCESS_MASK0 0x03ul +#define MCHP_EC_SRAM_BAR_H0_ACCESS_MASK 0x06ul +#define MCHP_EC_SRAM_BAR_H0_ACCESS_NONE 0x00ul +#define MCHP_EC_SRAM_BAR_H0_ACCESS_RO 0x02ul +#define MCHP_EC_SRAM_BAR_H0_ACCESS_WO 0x04ul +#define MCHP_EC_SRAM_BAR_H0_ACCESS_RW 0x06ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_POS 4u +#define MCHP_EC_SRAM_BAR_H0_SIZE_MASK0 0x0Ful +#define MCHP_EC_SRAM_BAR_H0_SIZE_MASK 0xF0ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_1B 0x00ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_2B 0x10ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_4B 0x20ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_8B 0x30ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_16B 0x40ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_32B 0x50ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_64B 0x60ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_128B 0x70ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_256B 0x80ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_512B 0x90ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_1KB 0xA0ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_2KB 0xB0ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_4KB 0xC0ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_8KB 0xD0ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_16KB 0xE0ul +#define MCHP_EC_SRAM_BAR_H0_SIZE_32KB 0xF0ul +/* EC and Host SRAM BAR start offset of EC or Host memory address */ +#define MCHP_EC_SRAM_BAR_MADDR_OFS1 2ul +#define MCHP_EC_SRAM_BAR_MADDR_OFS2 4ul + +/* Interfaces to any C modules */ +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief index values for eSPI Memory BAR EC-only and Host register banks + * Memory BAR's are 80 bits (10 bytes) and are packed. Safe access is 16-bit. + * These index values are for an array of 16-bit registers. + */ +enum espi_mbar_idx { + MBAR_MBX_H0 = 0, /*! (@ 0x0000) Mailbox LD Mem BAR b[15:0] */ + MBAR_MBX_H1, /*! (@ 0x0002) Mailbox LD Mem BAR b[31:16] */ + MBAR_MBX_H2, /*! (@ 0x0004) Mailbox LD Mem BAR b[47:32] */ + MBAR_MBX_H3, /*! (@ 0x0006) Mailbox LD Mem BAR b[63:48] */ + MBAR_MBX_H4, /*! (@ 0x0008) Mailbox LD Mem BAR b[79:64] */ + MBAR_ACPI_EC_0_H0, /*! (@ 0x000A) ACPI EC0 LD Mem BAR b[15:0] */ + MBAR_ACPI_EC_0_H1, /*! (@ 0x000C) ACPI EC0 LD Mem BAR b[31:16] */ + MBAR_ACPI_EC_0_H2, /*! (@ 0x000E) ACPI EC0 LD Mem BAR b[47:32] */ + MBAR_ACPI_EC_0_H3, /*! (@ 0x0010) ACPI EC0 LD Mem BAR b[63:48] */ + MBAR_ACPI_EC_0_H4, /*! (@ 0x0012) ACPI EC0 LD Mem BAR b[79:64] */ + MBAR_ACPI_EC_1_H0, /*! (@ 0x0014) ACPI EC1 LD Mem BAR b[15:0] */ + MBAR_ACPI_EC_1_H1, /*! (@ 0x0016) ACPI EC1 LD Mem BAR b[31:16] */ + MBAR_ACPI_EC_1_H2, /*! (@ 0x0018) ACPI EC1 LD Mem BAR b[47:32] */ + MBAR_ACPI_EC_1_H3, /*! (@ 0x001A) ACPI EC1 LD Mem BAR b[63:48] */ + MBAR_ACPI_EC_1_H4, /*! (@ 0x001C) ACPI EC1 LD Mem BAR b[79:64] */ + MBAR_ACPI_EC_2_H0, /*! (@ 0x001E) ACPI EC2 LD Mem BAR b[15:0] */ + MBAR_ACPI_EC_2_H1, /*! (@ 0x0020) ACPI EC2 LD Mem BAR b[31:16] */ + MBAR_ACPI_EC_2_H2, /*! (@ 0x0022) ACPI EC2 LD Mem BAR b[47:32] */ + MBAR_ACPI_EC_2_H3, /*! (@ 0x0024) ACPI EC2 LD Mem BAR b[63:48] */ + MBAR_ACPI_EC_2_H4, /*! (@ 0x0026) ACPI EC2 LD Mem BAR b[79:64] */ + MBAR_ACPI_EC_3_H0, /*! (@ 0x0028) ACPI EC3 LD Mem BAR b[15:0] */ + MBAR_ACPI_EC_3_H1, /*! (@ 0x002A) ACPI EC3 LD Mem BAR b[31:16] */ + MBAR_ACPI_EC_3_H2, /*! (@ 0x002C) ACPI EC3 LD Mem BAR b[47:32] */ + MBAR_ACPI_EC_3_H3, /*! (@ 0x002E) ACPI EC3 LD Mem BAR b[63:48] */ + MBAR_ACPI_EC_3_H4, /*! (@ 0x0030) ACPI EC3 LD Mem BAR b[79:64] */ + MBAR_ACPI_EC_4_H0, /*! (@ 0x0032) ACPI EC4 LD Mem BAR b[15:0] */ + MBAR_ACPI_EC_4_H1, /*! (@ 0x0034) ACPI EC4 LD Mem BAR b[31:16] */ + MBAR_ACPI_EC_4_H2, /*! (@ 0x0036) ACPI EC4 LD Mem BAR b[47:32] */ + MBAR_ACPI_EC_4_H3, /*! (@ 0x0038) ACPI EC4 LD Mem BAR b[63:48] */ + MBAR_ACPI_EC_4_H4, /*! (@ 0x003A) ACPI EC4 LD Mem BAR b[79:64] */ + MBAR_EMI_0_H0, /*! (@ 0x003C) EMI0 LD Mem BAR b[15:0] */ + MBAR_EMI_0_H1, /*! (@ 0x003E) EMI0 LD Mem BAR b[31:16] */ + MBAR_EMI_0_H2, /*! (@ 0x0040) EMI0 LD Mem BAR b[47:32] */ + MBAR_EMI_0_H3, /*! (@ 0x0042) EMI0 LD Mem BAR b[63:48] */ + MBAR_EMI_0_H4, /*! (@ 0x0044) EMI0 LD Mem BAR b[79:64] */ + MBAR_EMI_1_H0, /*! (@ 0x0046) EMI1 LD Mem BAR b[15:0] */ + MBAR_EMI_1_H1, /*! (@ 0x0048) EMI1 LD Mem BAR b[31:16] */ + MBAR_EMI_1_H2, /*! (@ 0x004A) EMI1 LD Mem BAR b[47:32] */ + MBAR_EMI_1_H3, /*! (@ 0x004C) EMI1 LD Mem BAR b[63:48] */ + MBAR_EMI_1_H4, /*! (@ 0x004E) EMI1 LD Mem BAR b[79:64] */ + MBAR_EMI_2_H0, /*! (@ 0x0050) EMI1 LD Mem BAR b[15:0] */ + MBAR_EMI_2_H1, /*! (@ 0x0052) EMI1 LD Mem BAR b[31:16] */ + MBAR_EMI_2_H2, /*! (@ 0x0054) EMI1 LD Mem BAR b[47:32] */ + MBAR_EMI_2_H3, /*! (@ 0x0058) EMI1 LD Mem BAR b[63:48] */ + MBAR_EMI_2_H4, /*! (@ 0x005A) EMI1 LD Mem BAR b[79:64] */ + MBAR_MAX +}; + +/* + * eSPI Memory Component SRAM 0 and 1 EC BAR's @ 0x400F39A0 + * bit[0] = Valid + * bits[2:1] = Access + * bit[3] = reserved, read-only 0 + * bits[7:4] = Size as power of 2 + * bits[15:8] = reserved, read-only 0 + * bits[47:16] = Base address of EC SRAM mapped to this BAR must be + * aligned on Size boundary. + */ +enum espi_sram_bar_index { + MBAR_SRAM_0_H0 = 0, /*! (@ 0x000C) SRAM0 BAR Internal b[15:0] */ + MBAR_SRAM_0_H1, /*! (@ 0x000E) SRAM0 BAR Internal b[31:16] */ + MBAR_SRAM_0_H2, /*! (@ 0x0010) SRAM0 BAR Internal b[47:32] */ + MBAR_SRAM_0_H3, /*! (@ 0x0012) SRAM0 BAR Internal b[63:48] */ + MBAR_SRAM_0_H4, /*! (@ 0x0014) SRAM0 BAR Internal b[79:64] */ + MBAR_SRAM_1_H0, /*! (@ 0x0016) SRAM1 BAR Internal b[15:0] */ + MBAR_SRAM_1_H1, /*! (@ 0x0018) SRAM1 BAR Internal b[31:16] */ + MBAR_SRAM_1_H2, /*! (@ 0x001A) SRAM1 BAR Internal b[47:32] */ + MBAR_SRAM_1_H3, /*! (@ 0x001C) SRAM1 BAR Internal b[63:48] */ + MBAR_SRAM_1_H4, /*! (@ 0x001E) SRAM1 BAR Internal b[79:64] */ + MBAR_SRAM_MAX +}; + +/* + * eSPI Memory Component SRAM 0 and 1 Host BAR's @ 0x400F3BA0 + * bit[0] = Read-Only copy of EC BAR Valid bit + * bits[2:1] = Read-Only copy of EC BAR Access field + * bit[3] = reserved, read-only 0 + * bits[7:4] = Read-Only copy of EC Size field + * bits[15:8] = reserved, read-only 0 + * bits[47:16] = R/W. Base address in Host memory space for this BAR. + */ + +enum mec_espi_sram_bar_size { + MCHP_ESPI_SRAM_SZ_1B = 0, + MCHP_ESPI_SRAM_SZ_2B, + MCHP_ESPI_SRAM_SZ_4B, + MCHP_ESPI_SRAM_SZ_8B, + MCHP_ESPI_SRAM_SZ_16B, + MCHP_ESPI_SRAM_SZ_32B, + MCHP_ESPI_SRAM_SZ_64B, + MCHP_ESPI_SRAM_SZ_128B, + MCHP_ESPI_SRAM_SZ_256B, + MCHP_ESPI_SRAM_SZ_512B, + MCHP_ESPI_SRAM_SZ_1KB, + MCHP_ESPI_SRAM_SZ_2KB, + MCHP_ESPI_SRAM_SZ_4KB, + MCHP_ESPI_SRAM_SZ_8KB, + MCHP_ESPI_SRAM_SZ_16KB, + MCHP_ESPI_SRAM_SZ_32KB +}; + +enum mec_espi_sram_bar_access { + MCHP_ESPI_SRAM_ACCESS_NONE = 0, + MCHP_ESPI_SRAM_ACCESS_RO, + MCHP_ESPI_SRAM_ACCESS_WO, + MCHP_ESPI_SRAM_ACCESS_RW +}; + +enum mec_espi_sram_bar_valid { + MCHP_ESPI_SRAM_BAR_NOT_VALID = 0, + MCHP_ESPI_SRAM_BAR_VALID +}; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _COMPONENT_ESPI_MEM_H */ +/* end espi_mem.h */ +/** @} + */ diff --git a/mec/mec172x/component/espi_saf.h b/mec/mec172x/component/espi_saf.h new file mode 100644 index 0000000..c439f49 --- /dev/null +++ b/mec/mec172x/component/espi_saf.h @@ -0,0 +1,499 @@ +/* + * Copyright (c) 2021 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file Header with definitions for MCHP eSPI SAF registers + */ + +#ifndef _COMPONENT_ESPI_SAF_H_ +#define _COMPONENT_ESPI_SAF_H_ + +#include +#include + +#include +#include + +#define MCHP_ESPI_SAF_BASE_ADDR 0x40008000u +#define MCHP_ESPI_SAF_COMM_BASE_ADDR 0x40071000u + +/* SAF hardware supports up to 2 external SPI flash devices */ +#define MCHP_ESPI_SAF_CS_MAX 2 + +/* Three TAG Map registers */ +#define MCHP_ESPI_SAF_TAGMAP_MAX 3 +/* 17 protection regions */ +#define MCHP_ESPI_SAF_PR_MAX 17 + +#define MCHP_SAF_FL_CM_PRF_CS0_OFS 0x1b0u +#define MCHP_SAF_FL_CM_PRF_CS1_OFS 0x1b2u + +#define MCHP_ESPI_SAF_BASE 0x40008000u +#define MCHP_ESPI_SAF_COMM_BASE 0x40071000u +#define MCHP_ESPI_SAF_COMM_MODE_OFS 0x2b8u +#define MCHP_ESPI_SAF_COMM_MODE_ADDR (MCHP_ESPI_SAF_COMM_BASE_ADDR + \ + MCHP_ESPI_SAF_COMM_MODE_OFS) + +/* SAF Protection region described by 4 32-bit registers. 17 regions */ +#define MCHP_ESPI_SAF_PROT_MAX 17u + +/* SAF Communication Mode register */ +#define MCHP_SAF_COMM_MODE_REG REG32(MCHP_ESPI_SAF_COMM_MODE_ADDR) + +/* + * Interrupt connections + * HW bug: SAF interrupts do not have direct NVIC connections. + */ +#define MCHP_SAF_GIRQ 18u +#define MCHP_SAF_GIRQ_ECP_DONE_POS 9 +#define MCHP_SAF_GIRQ_ERROR_POS 10 +#define MCHP_SAF_GIRQ_ECP_DONE_BIT BIT(MCHP_SAF_GIRQ_ECP_DONE_POS) +#define MCHP_SAF_GIRQ_ERROR_BIT BIT(MCHP_SAF_GIRQ_ERROR_POS) + +/* Register bit definitions */ + +/* SAF EC Portal Command register */ +#define MCHP_SAF_ECP_CMD_OFS 0x18u +#define MCHP_SAF_ECP_CMD_MASK 0xFF00FFFFu +#define MCHP_SAF_ECP_CMD_PUT_POS 0 +#define MCHP_SAF_ECP_CMD_PUT_MASK 0xFFu +#define MCHP_SAF_ECP_CMD_PUT_FLASH_NP 0x0Au +#define MCHP_SAF_ECP_CMD_CTYPE_POS 8 +#define MCHP_SAF_ECP_CMD_CTYPE_READ0 0x00u +#define MCHP_SAF_ECP_CMD_CTYPE_WRITE0 0x01u +#define MCHP_SAF_ECP_CMD_CTYPE_ERASE0 0x02u +#define MCHP_SAF_ECP_CMD_CTYPE_MAX0 0x03u +#define MCHP_SAF_ECP_CMD_CTYPE_MASK 0xFF00ul +#define MCHP_SAF_ECP_CMD_CTYPE_READ 0x0000ul +#define MCHP_SAF_ECP_CMD_CTYPE_WRITE 0x0100ul +#define MCHP_SAF_ECP_CMD_CTYPE_ERASE 0x0200ul +#define MCHP_SAF_ECP_CMD_LEN_POS 24 +#define MCHP_SAF_ECP_CMD_LEN_MASK0 0xFFu +#define MCHP_SAF_ECP_CMD_LEN_MASK 0xFF000000ul +/* Read/Write request size (1 <= reqlen <= 64) bytes */ +#define MCHP_SAF_ECP_CMD_RW_LEN_MIN 1 +#define MCHP_SAF_ECP_CMD_RW_LEN_MAX 64 +/* Only three erase sizes are supported encoded as */ +#define MCHP_SAF_ECP_CMD_ERASE_4K 0x00 +#define MCHP_SAF_ECP_CMD_ERASE_32K BIT(24) +#define MCHP_SAF_ECP_CMD_ERASE_64K BIT(25) + +/* SAF EC Portal Flash Address register */ +#define MCHP_SAF_ECP_FLAR_OFS 0x1Cu +#define MCHP_SAF_ECP_FLAR_MASK 0xFFFFFFFFU + +/* SAF EC Portal Start register */ +#define MCHP_SAF_ECP_START_OFS 0x20u +#define MCHP_SAF_ECP_START_MASK 0x01u +#define MCHP_SAF_ECP_START BIT(0) + +/* SAF EC Portal Buffer Address register */ +#define MCHP_SAF_ECP_BFAR_OFS 0x24u +#define MCHP_SAF_ECP_BFAR_MASK 0xFFFFFFFCu + +/* SAF EC Portal Status register */ +#define MCHP_SAF_ECP_STS_OFS 0x28u +#define MCHP_SAF_ECP_STS_MASK 0x1FFu +#define MCHP_SAF_ECP_STS_ERR_MASK 0x1FCu +#define MCHP_SAF_ECP_STS_DONE BIT(0) +#define MCHP_SAF_ECP_STS_DONE_TST BIT(1) +#define MCHP_SAF_ECP_STS_TMOUT BIT(2) +#define MCHP_SAF_ECP_STS_OOR BIT(3) +#define MCHP_SAF_ECP_STS_AV BIT(4) +#define MCHP_SAF_ECP_STS_BND_4K BIT(5) +#define MCHP_SAF_ECP_STS_ERSZ BIT(6) +#define MCHP_SAF_ECP_STS_ST_OVFL BIT(7) +#define MCHP_SAF_ECP_STS_BAD_REQ BIT(8) + +/* SAF EC Portal Interrupt Enable register */ +#define MCHP_SAF_ECP_INTEN_OFS 0x2Cu +#define MCHP_SAF_ECP_INTEN_MASK 0x01u +#define MCHP_SAF_ECP_INTEN_DONE BIT(0) + +/* SAF Flash Configuratin Size Limit register */ +#define MCHP_SAF_FL_CFG_SIZE_LIM_OFS 0x30u +#define MCHP_SAF_FL_CFG_SIZE_LIM_MASK 0xFFFFFFFFu + +/* SAF Flash Configuration Threshold register */ +#define MCHP_SAF_FL_CFG_THRH_OFS 0x34u +#define MCHP_SAF_FL_CFG_THRH_MASK 0xFFFFFFFFu + +/* SAF Flash Configuration Miscellaneous register */ +#define MCHP_SAF_FL_CFG_MISC_OFS 0x38u +#define MCHP_SAF_FL_CFG_MISC_MASK 0x000030F3u +#define MCHP_SAF_FL_CFG_MISC_PFOE_MASK 0x03u +#define MCHP_SAF_FL_CFG_MISC_PFOE_DFLT 0x00u +#define MCHP_SAF_FL_CFG_MISC_PFOE_EXP 0x03u +#define MCHP_SAF_FL_CFG_MISC_CS0_4BM BIT(4) +#define MCHP_SAF_FL_CFG_MISC_CS1_4BM BIT(5) +#define MCHP_SAF_FL_CFG_MISC_CS0_CPE BIT(6) +#define MCHP_SAF_FL_CFG_MISC_CS1_CPE BIT(7) +#define MCHP_SAF_FL_CFG_MISC_SAF_EN BIT(12) +#define MCHP_SAF_FL_CFG_MISC_SAF_LOCK BIT(13) + +/* SAF eSPI Monitor Status register */ +#define MCHP_SAF_ESPI_MON_STATUS_OFS 0x3Cu +#define MCHP_SAF_ESPI_MON_STATUS_MASK 0x1Fu +#define MCHP_SAF_ESPI_MON_STS_TMOUT BIT(0) +#define MCHP_SAF_ESPI_MON_STS_OOR BIT(1) +#define MCHP_SAF_ESPI_MON_STS_AV BIT(2) +#define MCHP_SAF_ESPI_MON_STS_BND_4K BIT(3) +#define MCHP_SAF_ESPI_MON_STS_ERSZ BIT(4) + +/* SAF eSPI Monitor Interrupt Enable register */ +#define MCHP_SAF_ESPI_MON_INTEN_OFS 0x40u +#define MCHP_SAF_ESPI_MON_INTEN_MASK 0x1Fu +#define MCHP_SAF_ESPI_MON_INTEN_TMOUT BIT(0) +#define MCHP_SAF_ESPI_MON_INTEN_OOR BIT(1) +#define MCHP_SAF_ESPI_MON_INTEN_AV BIT(2) +#define MCHP_SAF_ESPI_MON_INTEN_BND_4K BIT(3) +#define MCHP_SAF_ESPI_MON_INTEN_ERSZ BIT(4) + +/* SAF EC Portal Busy register */ +#define MCHP_SAF_ECP_BUSY_OFS 0x44u +#define MCHP_SAF_ECP_BUSY_MASK 0x01u +#define MCHP_SAF_ECP_BUSY BIT(0) + +/* SAF CS0/CS1 Opcode A registers */ +#define MCHP_SAF_CS0_OPA_OFS 0x4Cu +#define MCHP_SAF_CS1_OPA_OFS 0x5Cu +#define MCHP_SAF_CS_OPA_MASK 0xFFFFFFFFu +#define MCHP_SAF_CS_OPA_WE_POS 0 +#define MCHP_SAF_CS_OPA_WE_MASK 0xFFul +#define MCHP_SAF_CS_OPA_SUS_POS 8 +#define MCHP_SAF_CS_OPA_SUS_MASK 0xFF00ul +#define MCHP_SAF_CS_OPA_RSM_POS 16 +#define MCHP_SAF_CS_OPA_RSM_MASK 0xFF0000ul +#define MCHP_SAF_CS_OPA_POLL1_POS 24 +#define MCHP_SAF_CS_OPA_POLL1_MASK 0xFF000000ul + +/* SAF CS0/CS1 Opcode B registers */ +#define MCHP_SAF_CS0_OPB_OFS 0x50u +#define MCHP_SAF_CS1_OPB_OFS 0x60u +#define MCHP_SAF_CS_OPB_OFS 0xFFFFFFFFu +#define MCHP_SAF_CS_OPB_ER0_POS 0 +#define MCHP_SAF_CS_OPB_ER0_MASK 0xFFu +#define MCHP_SAF_CS_OPB_ER1_POS 8 +#define MCHP_SAF_CS_OPB_ER1_MASK 0xFF00ul +#define MCHP_SAF_CS_OPB_ER2_POS 16 +#define MCHP_SAF_CS_OPB_ER2_MASK 0xFF0000ul +#define MCHP_SAF_CS_OPB_PGM_POS 24 +#define MCHP_SAF_CS_OPB_PGM_MASK 0xFF000000ul + +/* SAF CS0/CS1 Opcode C registers */ +#define MCHP_SAF_CS0_OPC_OFS 0x54u +#define MCHP_SAF_CS1_OPC_OFS 0x64u +#define MCHP_SAF_CS_OPC_MASK 0xFFFFFFFFu +#define MCHP_SAF_CS_OPC_RD_POS 0 +#define MCHP_SAF_CS_OPC_RD_MASK 0xFFu +#define MCHP_SAF_CS_OPC_MNC_POS 8 +#define MCHP_SAF_CS_OPC_MNC_MASK 0xFF00ul +#define MCHP_SAF_CS_OPC_MC_POS 16 +#define MCHP_SAF_CS_OPC_MC_MASK 0xFF0000ul +#define MCHP_SAF_CS_OPC_POLL2_POS 24 +#define MCHP_SAF_CS_OPC_POLL2_MASK 0xFF000000ul + +/* SAF CS0/CS1 registers */ +#define MCHP_SAF_CS0_DESCR_OFS 0x58u +#define MCHP_SAF_CS1_DESCR_OFS 0x68u +#define MCHP_SAF_CS_DESCR_MASK 0x0000FF0Fu +#define MCHP_SAF_CS_DESCR_ENTC_POS 0 +#define MCHP_SAF_CS_DESCR_ENTC_MASK 0x0Fu +#define MCHP_SAF_CS_DESCR_RDC_POS 8 +#define MCHP_SAF_CS_DESCR_RDC_MASK 0x0F00ul +#define MCHP_SAF_CS_DESCR_SZC_POS 12 +#define MCHP_SAF_CS_DESCR_SZC_MASK 0xF000ul + +/* SAF Flash Configuration General Descriptors register */ +#define MCHP_SAF_FL_CFG_GEN_DESCR_OFS 0x6Cu +#define MCHP_SAF_FL_CFG_GEN_DESCR_MASK 0x0000FF0Fu +/* value for standard 16 descriptor programming */ +#define MCHP_SAF_FL_CFG_GEN_DESCR_STD 0x0000EE0Cu +#define MCHP_SAF_FL_CFG_GEN_DESCR_EXC_POS 0 +#define MCHP_SAF_FL_CFG_GEN_DESCR_EXC_MASK 0x0Fu +#define MCHP_SAF_FL_CFG_GEN_DESCR_POLL1_POS 8 +#define MCHP_SAF_FL_CFG_GEN_DESCR_POLL1_MASK \ + SHLU32(0x0Fu, MCHP_SAF_FL_CFG_GEN_DESCR_POLL1_POS) + +#define MCHP_SAF_FL_CFG_GEN_DESCR_POLL2_POS 12 +#define MCHP_SAF_FL_CFG_GEN_DESCR_POLL2_MASK \ + SHLU32(0x0Fu, MCHP_SAF_FL_CFG_GEN_DESCR_POLL2_POS) + +/* SAF Protection Lock register */ +#define MCHP_SAF_PROT_LOCK_OFS 0x70u +#define MCHP_SAF_PROT_LOCK_MASK 0x1FFFFu +#define MCHP_SAF_PROT_LOCK0 BIT(0) +#define MCHP_SAF_PROT_LOCK1 BIT(1) +#define MCHP_SAF_PROT_LOCK2 BIT(2) +#define MCHP_SAF_PROT_LOCK3 BIT(3) +#define MCHP_SAF_PROT_LOCK4 BIT(4) +#define MCHP_SAF_PROT_LOCK5 BIT(5) +#define MCHP_SAF_PROT_LOCK6 BIT(6) +#define MCHP_SAF_PROT_LOCK7 BIT(7) +#define MCHP_SAF_PROT_LOCK8 BIT(8) +#define MCHP_SAF_PROT_LOCK9 BIT(9) +#define MCHP_SAF_PROT_LOCK10 BIT(10) +#define MCHP_SAF_PROT_LOCK11 BIT(11) +#define MCHP_SAF_PROT_LOCK12 BIT(12) +#define MCHP_SAF_PROT_LOCK13 BIT(13) +#define MCHP_SAF_PROT_LOCK14 BIT(14) +#define MCHP_SAF_PROT_LOCK15 BIT(15) +#define MCHP_SAF_PROT_LOCK16 BIT(16) + +/* SAF Protection Dirty register */ +#define MCHP_SAF_PROT_DIRTY_OFS 0x74u +#define MCHP_SAF_PROT_DIRTY_MASK 0xFFFu +#define MCHP_SAF_PROT_DIRTY0 BIT(0) +#define MCHP_SAF_PROT_DIRTY1 BIT(1) +#define MCHP_SAF_PROT_DIRTY2 BIT(2) +#define MCHP_SAF_PROT_DIRTY3 BIT(3) +#define MCHP_SAF_PROT_DIRTY4 BIT(4) +#define MCHP_SAF_PROT_DIRTY5 BIT(5) +#define MCHP_SAF_PROT_DIRTY6 BIT(6) +#define MCHP_SAF_PROT_DIRTY7 BIT(7) +#define MCHP_SAF_PROT_DIRTY8 BIT(8) +#define MCHP_SAF_PROT_DIRTY9 BIT(9) +#define MCHP_SAF_PROT_DIRTY10 BIT(10) +#define MCHP_SAF_PROT_DIRTY11 BIT(11) + +/* SAF Tag Map 0 register */ +#define MCHP_SAF_TAG_MAP0_OFS 0x78u +#define MCHP_SAF_TAG_MAP0_MASK 0x77777777u +#define MCHP_SAF_TAG_MAP0_DFLT 0x23221100u +#define MCHP_SAF_TAG_MAP0_STM0_POS 0 +#define MCHP_SAF_TAG_MAP0_STM0_MASK 0x07u +#define MCHP_SAF_TAG_MAP0_STM1_POS 4 +#define MCHP_SAF_TAG_MAP0_STM1_MASK \ + SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP0_STM1_POS) +#define MCHP_SAF_TAG_MAP0_STM2_POS 8 +#define MCHP_SAF_TAG_MAP0_STM2_MASK \ + SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM2_POS) +#define MCHP_SAF_TAG_MAP0_STM3_POS 12 +#define MCHP_SAF_TAG_MAP0_STM3_MASK \ + SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM3_POS) +#define MCHP_SAF_TAG_MAP0_STM4_POS 16 +#define MCHP_SAF_TAG_MAP0_STM4_MASK \ + SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM4_POS) +#define MCHP_SAF_TAG_MAP0_STM5_POS 20 +#define MCHP_SAF_TAG_MAP0_STM5_MASK \ + SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM5_POS) +#define MCHP_SAF_TAG_MAP0_STM6_POS 24 +#define MCHP_SAF_TAG_MAP0_STM6_MASK \ + SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM6_POS) +#define MCHP_SAF_TAG_MAP0_STM7_POS 28 +#define MCHP_SAF_TAG_MAP0_STM7_MASK \ + SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM7_POS) + +/* SAF Tag Map 1 register */ +#define MCHP_SAF_TAG_MAP1_OFS 0x7Cu +#define MCHP_SAF_TAG_MAP1_MASK 0x77777777u +#define MCHP_SAF_TAG_MAP1_DFLT 0x77677767u +#define MCHP_SAF_TAG_MAP1_STM8_POS 0 +#define MCHP_SAF_TAG_MAP1_STM8_MASK 0x07u +#define MCHP_SAF_TAG_MAP1_STM9_POS 4 +#define MCHP_SAF_TAG_MAP1_STM9_MASK \ + SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STM9_POS) +#define MCHP_SAF_TAG_MAP1_STMA_POS 8 +#define MCHP_SAF_TAG_MAP1_STMA_MASK \ + SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMA_POS) +#define MCHP_SAF_TAG_MAP1_STMB_POS 12 +#define MCHP_SAF_TAG_MAP1_STMB_MASK \ + SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMB_POS) +#define MCHP_SAF_TAG_MAP1_STMC_POS 16 +#define MCHP_SAF_TAG_MAP1_STMC_MASK \ + SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMC_POS) +#define MCHP_SAF_TAG_MAP1_STMD_POS 20 +#define MCHP_SAF_TAG_MAP1_STMD_MASK \ + SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMD_POS) +#define MCHP_SAF_TAG_MAP1_STME_POS 24 +#define MCHP_SAF_TAG_MAP1_STME_MASK \ + SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STME_POS) +#define MCHP_SAF_TAG_MAP1_STMF_POS 28 +#define MCHP_SAF_TAG_MAP1_STMF_MASK \ + SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMF_POS) + +/* SAF Tag Map 2 register */ +#define MCHP_SAF_TAG_MAP2_OFS 0x80u +#define MCHP_SAF_TAG_MAP2_MASK 0x80000007u +#define MCHP_SAF_TAG_MAP2_DFLT 0x00000005u +#define MCHP_SAF_TAG_MAP2_SM_EC_POS 0 +#define MCHP_SAF_TAG_MAP2_SM_EC_MASK 0x07u +#define MCHP_SAF_TAG_MAP2_LOCK_POS 31 +#define MCHP_SAF_TAG_MAP2_LOCK BIT(MCHP_SAF_TAG_MAP2_LOCK_POS) + +/* SAF Protection Region Start registers */ +#define MCHP_SAF_PROT_RG0_START_OFS 0x84u +#define MCHP_SAF_PROT_RG1_START_OFS 0x94u +#define MCHP_SAF_PROT_RG2_START_OFS 0xA4u +#define MCHP_SAF_PROT_RG3_START_OFS 0xB4u +#define MCHP_SAF_PROT_RG4_START_OFS 0xC4u +#define MCHP_SAF_PROT_RG5_START_OFS 0xD4u +#define MCHP_SAF_PROT_RG6_START_OFS 0xE4u +#define MCHP_SAF_PROT_RG7_START_OFS 0xF4u +#define MCHP_SAF_PROT_RG8_START_OFS 0x104u +#define MCHP_SAF_PROT_RG9_START_OFS 0x114u +#define MCHP_SAF_PROT_RG10_START_OFS 0x124u +#define MCHP_SAF_PROT_RG11_START_OFS 0x134u +#define MCHP_SAF_PROT_RG12_START_OFS 0x144u +#define MCHP_SAF_PROT_RG13_START_OFS 0x154u +#define MCHP_SAF_PROT_RG14_START_OFS 0x164u +#define MCHP_SAF_PROT_RG15_START_OFS 0x174u +#define MCHP_SAF_PROT_RG16_START_OFS 0x184u +#define MCHP_SAF_PROT_RG_START_MASK 0xfffffu +#define MCHP_SAF_PROT_RG_START_DFLT 0x07fffu + +/* SAF Protection Region Limit registers */ +#define MCHP_SAF_PROT_RG0_LIMIT_OFS 0x88u +#define MCHP_SAF_PROT_RG1_LIMIT_OFS 0x98u +#define MCHP_SAF_PROT_RG2_LIMIT_OFS 0xA8u +#define MCHP_SAF_PROT_RG3_LIMIT_OFS 0xB8u +#define MCHP_SAF_PROT_RG4_LIMIT_OFS 0xC8u +#define MCHP_SAF_PROT_RG5_LIMIT_OFS 0xD8u +#define MCHP_SAF_PROT_RG6_LIMIT_OFS 0xE8u +#define MCHP_SAF_PROT_RG7_LIMIT_OFS 0xF8u +#define MCHP_SAF_PROT_RG8_LIMIT_OFS 0x108u +#define MCHP_SAF_PROT_RG9_LIMIT_OFS 0x118u +#define MCHP_SAF_PROT_RG10_LIMIT_OFS 0x128u +#define MCHP_SAF_PROT_RG11_LIMIT_OFS 0x138u +#define MCHP_SAF_PROT_RG12_LIMIT_OFS 0x148u +#define MCHP_SAF_PROT_RG13_LIMIT_OFS 0x158u +#define MCHP_SAF_PROT_RG14_LIMIT_OFS 0x168u +#define MCHP_SAF_PROT_RG15_LIMIT_OFS 0x178u +#define MCHP_SAF_PROT_RG16_LIMIT_OFS 0x188u +#define MCHP_SAF_PROT_RG_LIMIT_MASK 0xfffffu +#define MCHP_SAF_PROT_RG_LIMIT_DFLT 0 + +/* SAF Protection Region Write Bitmap registers */ +#define MCHP_SAF_PROT_RG0_WBM_OFS 0x8Cu +#define MCHP_SAF_PROT_RG1_WBM_OFS 0x9Cu +#define MCHP_SAF_PROT_RG2_WBM_OFS 0xACu +#define MCHP_SAF_PROT_RG3_WBM_OFS 0xBCu +#define MCHP_SAF_PROT_RG4_WBM_OFS 0xCCu +#define MCHP_SAF_PROT_RG5_WBM_OFS 0xDCu +#define MCHP_SAF_PROT_RG6_WBM_OFS 0xEFu +#define MCHP_SAF_PROT_RG7_WBM_OFS 0xFCu +#define MCHP_SAF_PROT_RG8_WBM_OFS 0x10Cu +#define MCHP_SAF_PROT_RG9_WBM_OFS 0x11Cu +#define MCHP_SAF_PROT_RG10_WBM_OFS 0x12Cu +#define MCHP_SAF_PROT_RG11_WBM_OFS 0x13Cu +#define MCHP_SAF_PROT_RG12_WBM_OFS 0x14Cu +#define MCHP_SAF_PROT_RG13_WBM_OFS 0x15Cu +#define MCHP_SAF_PROT_RG14_WBM_OFS 0x16Cu +#define MCHP_SAF_PROT_RG15_WBM_OFS 0x17Cu +#define MCHP_SAF_PROT_RG16_WBM_OFS 0x18Cu +#define MCHP_SAF_PROT_RG_WBM_MASK 0xFFu +#define MCHP_SAF_PROT_RG_WBM0 BIT(0) +#define MCHP_SAF_PROT_RG_WBM1 BIT(1) +#define MCHP_SAF_PROT_RG_WBM2 BIT(2) +#define MCHP_SAF_PROT_RG_WBM3 BIT(3) +#define MCHP_SAF_PROT_RG_WBM4 BIT(4) +#define MCHP_SAF_PROT_RG_WBM5 BIT(5) +#define MCHP_SAF_PROT_RG_WBM6 BIT(6) +#define MCHP_SAF_PROT_RG_WBM7 BIT(7) + +/* SAF Protection Region Read Bitmap registers */ +#define MCHP_SAF_PROT_RG0_RBM_OFS 0x90u +#define MCHP_SAF_PROT_RG1_RBM_OFS 0xA0u +#define MCHP_SAF_PROT_RG2_RBM_OFS 0xB0u +#define MCHP_SAF_PROT_RG3_RBM_OFS 0xC0u +#define MCHP_SAF_PROT_RG4_RBM_OFS 0xD0u +#define MCHP_SAF_PROT_RG5_RBM_OFS 0xE0u +#define MCHP_SAF_PROT_RG6_RBM_OFS 0xF0u +#define MCHP_SAF_PROT_RG7_RBM_OFS 0x100u +#define MCHP_SAF_PROT_RG8_RBM_OFS 0x110u +#define MCHP_SAF_PROT_RG9_RBM_OFS 0x120u +#define MCHP_SAF_PROT_RG10_RBM_OFS 0x130u +#define MCHP_SAF_PROT_RG11_RBM_OFS 0x140u +#define MCHP_SAF_PROT_RG12_RBM_OFS 0x150u +#define MCHP_SAF_PROT_RG13_RBM_OFS 0x160u +#define MCHP_SAF_PROT_RG14_RBM_OFS 0x170u +#define MCHP_SAF_PROT_RG15_RBM_OFS 0x180u +#define MCHP_SAF_PROT_RG16_RBM_OFS 0x190u +#define MCHP_SAF_PROT_RG_RBM_MASK 0xFFu +#define MCHP_SAF_PROT_RG_RBM0 BIT(0) +#define MCHP_SAF_PROT_RG_RBM1 BIT(1) +#define MCHP_SAF_PROT_RG_RBM2 BIT(2) +#define MCHP_SAF_PROT_RG_RBM3 BIT(3) +#define MCHP_SAF_PROT_RG_RBM4 BIT(4) +#define MCHP_SAF_PROT_RG_RBM5 BIT(5) +#define MCHP_SAF_PROT_RG_RBM6 BIT(6) +#define MCHP_SAF_PROT_RG_RBM7 BIT(7) + +/* SAF Poll Timeout register */ +#define MCHP_SAF_POLL_TMOUT_OFS 0x194u +#define MCHP_SAF_POLL_TMOUT_MASK 0x3FFFFu +#define MCHP_SAF_POLL_TMOUT_5S 0x28000u + +/* SAF Poll Interval register */ +#define MCHP_SAF_POLL_INTRVL_OFS 0x198u +#define MCHP_SAF_POLL_INTRVL_MASK 0xFFFFu + +/* SAF Suspend Resume Interval register */ +#define MCHP_SAF_SUS_RSM_INTRVL_OFS 0x19Cu +#define MCHP_SAF_SUS_RSM_INTRVL_MASK 0xFFFFu + +/* SAF Consecutive Read Timeout register */ +#define MCHP_SAF_CRD_TMOUT_OFS 0x1A0u +#define MCHP_SAF_CRD_TMOUT_MASK 0xFFFFFu + +/* SAF Flash CS0/CS1 Configuration Poll2 Mask registers */ +#define MCHP_SAF_FL0_CFG_P2M_OFS 0x1A4u +#define MCHP_SAF_FL1_CFG_P2M_OFS 0x1A6u +#define MCHP_SAF_FL_CFG_P2M_MASK 0xFFFFu + +/* SAF Flash Configuration Special Mode register */ +#define MCHP_SAF_FL_CFG_SPM_OFS 0x1A8u +#define MCHP_SAF_FL_CFG_SPM_MASK 0x01u +#define MCHP_SAF_FL_CFG_SPM_DIS_SUSP BIT(0) + +/* SAF Suspend Check Delay register */ +#define MCHP_SAF_SUS_CHK_DLY_OFS 0x1ACu +#define MCHP_SAF_SUS_CHK_DLY_MASK 0xFFFFFu + +/* SAF Flash 0/1 Continuous Mode Prefix registers */ +#define MCHP_SAF_FL_CM_PRF_OFS 0x1B0u +#define MCHP_SAF_FL_CM_PRF_MASK 0xFFFFu +#define MCHP_SAF_FL_CM_PRF_CS_OP_POS 0 +#define MCHP_SAF_FL_CM_PRF_CS_OP_MASK 0xFFu +#define MCHP_SAF_FL_CM_PRF_CS_DAT_POS 8 +#define MCHP_SAF_FL_CM_PRF_CS_DAT_MASK \ + SHLU32(MCHP_SAF_FL_CM_PRF_CS_OP_MASK, MCHP_SAF_FL_CM_PRF_CS_DAT_POS) + +/* SAF DnX Protection Bypass register */ +#define MCHP_SAF_DNX_PROT_BYP_OFS 0x1B4u +#define MCHP_SAF_DNX_PROT_BYP_MASK 0xFFFFFFFFu + +/* SAF Communication Mode */ +#define MCHP_SAF_COMM_MODE_MASK 0x01u +/* Allow pre-fetch from flash devices */ +#define MCHP_SAF_COMM_MODE_PF_EN BIT(0) + +/* SAF TAG numbers[0:0xF] */ +#define MCHP_SAF_TAG_M0T0 0u +#define MCHP_SAF_TAG_M0T1 1u +#define MCHP_SAF_TAG_M1T0 2u +#define MCHP_SAF_TAG_M1T1 3u +#define MCHP_SAF_TAG_M2T0 4u +#define MCHP_SAF_TAG_M2T1 5u +#define MCHP_SAF_TAG_M3T0 6u +#define MCHP_SAF_TAG_M2T2 7u +#define MCHP_SAF_TAG_M6T0 9u +#define MCHP_SAF_TAG_M6T1 0x0Du +#define MCHP_SAF_TAG_MAX 0x10u + +/* SAF Master numbers */ +#define MCHP_SAF_MSTR_CS_INIT 0u +#define MCHP_SAF_MSTR_CPU 1u +#define MCHP_SAF_MSTR_CS_ME 2u +#define MCHP_SAF_MSTR_CS_LAN 3u +#define MCHP_SAF_MSTR_UNUSED4 4u +#define MCHP_SAF_MSTR_EC_FW 5u +#define MCHP_SAF_MSTR_CS_IE 6u +#define MCHP_SAF_MSTR_UNUSED7 7u +#define MCHP_SAF_MSTR_MAX 8u +#define MCHP_SAF_MSTR_ALL 0xFFu + +#endif /* _COMPONENT_ESPI_SAF_H_ */ diff --git a/mec/mec172x/component/espi_vw.h b/mec/mec172x/component/espi_vw.h new file mode 100644 index 0000000..1b37949 --- /dev/null +++ b/mec/mec172x/component/espi_vw.h @@ -0,0 +1,635 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file espi_vw.h + * MEC172x eSPI Virtual Wire definitions + */ +/** @defgroup MEC172x Peripherals eSPI VW + */ + +#ifndef _COMPONENT_ESPI_VW_H +#define _COMPONENT_ESPI_VW_H + +#include +#include + +#include +#include + +/*------------------------------------------------------------------*/ + +/* Master to Slave VW register: 96-bit (3 32 bit registers) */ +/* 32-bit word 0 (bits[31:0]) */ +#define ESPI_M2SW0_OFS 0ul +#define ESPI_M2SW0_IDX_POS 0 +#define ESPI_M2SW0_IDX_MASK 0xFFu +#define ESPI_M2SW0_MTOS_SRC_POS 8u +#define ESPI_M2SW0_MTOS_SRC_MASK0 0x03u +#define ESPI_M2SW0_MTOS_SRC_MASK 0x300u +#define ESPI_M2SW0_MTOS_SRC_ESPI_RST 0ul +#define ESPI_M2SW0_MTOS_SRC_SYS_RST 0x100u +#define ESPI_M2SW0_MTOS_SRC_SIO_RST 0x200u +#define ESPI_M2SW0_MTOS_SRC_PLTRST 0x300u +#define ESPI_M2SW0_MTOS_STATE_POS 12u +#define ESPI_M2SW0_MTOS_STATE_MASK0 0x0Ful +#define ESPI_M2SW0_MTOS_STATE_MASK 0xF000ul +/* 32-bit word 1 (bits[63:32]) */ +#define ESPI_M2SW1_OFS 4ul +#define ESPI_M2SW1_SRC0_SEL_POS 0 +#define ESPI_M2SW1_SRC_SEL_MASK0 0x0Ful +#define ESPI_M2SW1_SRC0_SEL_MASK 0x0Ful +#define ESPI_M2SW1_SRC1_SEL_POS 8 +#define ESPI_M2SW1_SRC1_SEL_MASK 0x0F00ul +#define ESPI_M2SW1_SRC2_SEL_POS 16 +#define ESPI_M2SW1_SRC2_SEL_MASK 0x0F0000ul +#define ESPI_M2SW1_SRC3_SEL_POS 24 +#define ESPI_M2SW1_SRC3_SEL_MASK 0x0F000000ul +/* 0 <= n < 4 */ +#define ESPI_M2SW1_SRC_SEL_POS(n) ((n) * 8U) +#define ESPI_M2SW1_SRC_SEL_MASK(n) SHLU32(0xFu, ((n) * 8U)) +#define ESPI_M2SW1_SRC_SEL_VAL(n, v) SHLU32(((v) & 0xFu), ((n) * 8U)) +/* 32-bit word 2 (bits[95:64]) */ +#define ESPI_M2SW2_OFS 8ul +#define ESPI_M2SW2_SRC_MASK0 0x0Ful +#define ESPI_M2SW2_SRC0_POS 0 +#define ESPI_M2SW2_SRC0_MASK 0x0Ful +#define ESPI_M2SW2_SRC1_POS 8u +#define ESPI_M2SW2_SRC1_MASK 0x0F00ul +#define ESPI_M2SW2_SRC2_POS 16u +#define ESPI_M2SW2_SRC2_MASK 0x0F0000ul +#define ESPI_M2SW2_SRC3_POS 24u +#define ESPI_M2SW2_SRC3_MASK 0x0F000000ul +/* 0 <= n < 4 */ +#define ESPI_M2SW2_SRC_POS(n) ((n) * 8U) +#define ESPI_M2SW2_SRC_MASK(n) SHLU32(0xFu, ((n) * 8U)) +#define ESPI_M2SW2_SRC_VAL(n, v) SHLU32(((v) & 0xFu), ((n) * 8U)) + +/* + * Zero based values used for above SRC_SEL fields. + * These values select the interrupt sensitivity for the VWire. + * Example: Set SRC1 to Level High + * + * r = read MSVW1 register + * r &= ESPI_M2SW1_SRC_SEL_MASK(1) + * r |= ESPI_MSVW1_SRC_SEL_VAL(1, ESPI_IRQ_SEL_LVL_HI) + * write r to MSVW1 register + */ +#define ESPI_IRQ_SEL_LVL_LO 0 +#define ESPI_IRQ_SEL_LVL_HI 1 +#define ESPI_IRQ_SEL_DIS 4 +/* NOTE: Edge trigger modes allow VWires to wake from deep sleep */ +#define ESPI_IRQ_SEL_REDGE 0x0Du +#define ESPI_IRQ_SEL_FEDGE 0x0Eu +#define ESPI_IRQ_SEL_BEDGE 0x0Fu + +/* Slave to Master VW register: 64-bit (2 32 bit registers) */ +/* 32-bit word 0 (bits[31:0]) */ +#define ESPI_S2MW0_OFS 0 +#define ESPI_S2MW0_IDX_POS 0 +#define ESPI_S2MW0_IDX_MASK 0xFFu +#define ESPI_S2MW0_STOM_POS 8u +#define ESPI_S2MW0_STOM_SRC_POS 8u +#define ESPI_S2MW0_STOM_MASK0 0xF3u +#define ESPI_S2MW0_STOM_MASK 0xF300u +#define ESPI_S2MW0_STOM_SRC_MASK0 0x03ul +#define ESPI_S2MW0_STOM_SRC_MASK 0x0300ul +#define ESPI_S2MW0_STOM_SRC_ESPI_RST 0ul +#define ESPI_S2MW0_STOM_SRC_SYS_RST 0x0100ul +#define ESPI_S2MW0_STOM_SRC_SIO_RST 0x0200ul +#define ESPI_S2MW0_STOM_SRC_PLTRST 0x0300ul +#define ESPI_S2MW0_STOM_STATE_POS 12u +#define ESPI_S2MW0_STOM_STATE_MASK0 0x0Ful +#define ESPI_S2MW0_STOM_STATE_MASK 0x0F000ul +#define ESPI_S2MW0_CHG0_POS 16u +#define ESPI_S2MW0_CHG0 BIT(ESPI_S2MW0_CHG0_POS) +#define ESPI_S2MW0_CHG1_POS 17u +#define ESPI_S2MW0_CHG1 BIT(ESPI_S2MW0_CHG1_POS) +#define ESPI_S2MW0_CHG2_POS 18u +#define ESPI_S2MW0_CHG2 BIT(ESPI_S2MW0_CHG2_POS) +#define ESPI_S2MW0_CHG3_POS 19u +#define ESPI_S2MW0_CHG3 BIT(ESPI_S2MW0_CHG3_POS) +#define ESPI_S2MW0_CHG_ALL_POS 16u +#define ESPI_S2MW0_CHG_ALL_MASK0 0x0Ful +#define ESPI_S2MW0_CHG_ALL_MASK 0x0F0000ul +/* 0 <= n < 4 */ +#define ESPI_S2MW1_CHG_POS(n) ((n) + 16u) +#define ESPI_S2MW1_CHG(v, n) \ + (((uint32_t)(v) >> ESPI_S2MW1_CHG_POS(n)) & 0x01) + +/* 32-bit word 1 (bits[63:32]) */ +#define ESPI_S2MW1_OFS 4ul +#define ESPI_S2MW1_SRC0_POS 0u +#define ESPI_S2MW1_SRC0 BIT(ESPI_S2MW1_SRC0_POS) +#define ESPI_S2MW1_SRC1_POS 8u +#define ESPI_S2MW1_SRC1 BIT(ESPI_S2MW1_SRC1_POS) +#define ESPI_S2MW1_SRC2_POS 16u +#define ESPI_S2MW1_SRC2 BIT(ESPI_S2MW1_SRC2_POS) +#define ESPI_S2MW1_SRC3_POS 24u +#define ESPI_S2MW1_SRC3 BIT(ESPI_S2MW1_SRC3_POS) +/* 0 <= n < 4 */ +#define ESPI_S2MW1_SRC_POS(n) SHLU32((n), 3) +#define ESPI_S2MW1_SRC(v, n) \ + SHLU32(((uint32_t)(v) & 0x01), (ESPI_S2MW1_SRC_POS(n))) + +/* =========================================================================*/ +/* ================ ESPI_VW ================ */ +/* =========================================================================*/ + +/** + * @brief eSPI Virtual Wires (ESPI_VW) + */ + +#define ESPI_MSVW_IDX_MAX 10u +#define ESPI_SMVW_IDX_MAX 10u + +#define ESPI_NUM_MSVW 11u +#define ESPI_NUM_SMVW 11u + +/* + * ESPI MSVW interrupts + */ +#define MEC_ESPI_MSVW_00_06_GIRQ 24u +#define MEC_ESPI_MSVW_00_06_NVIC 15u + +#define MEC_ESPI_MSVW00_SRC0_POS 0u +#define MEC_ESPI_MSVW00_SRC1_POS 1u +#define MEC_ESPI_MSVW00_SRC2_POS 2u +#define MEC_ESPI_MSVW00_SRC3_POS 3u +#define MEC_ESPI_MSVW01_SRC0_POS 4u +#define MEC_ESPI_MSVW01_SRC1_POS 5u +#define MEC_ESPI_MSVW01_SRC2_POS 6u +#define MEC_ESPI_MSVW01_SRC3_POS 7u +#define MEC_ESPI_MSVW02_SRC0_POS 8u +#define MEC_ESPI_MSVW02_SRC1_POS 9u +#define MEC_ESPI_MSVW02_SRC2_POS 10u +#define MEC_ESPI_MSVW02_SRC3_POS 11u +#define MEC_ESPI_MSVW03_SRC0_POS 12u +#define MEC_ESPI_MSVW03_SRC1_POS 13u +#define MEC_ESPI_MSVW03_SRC2_POS 14u +#define MEC_ESPI_MSVW03_SRC3_POS 15u +#define MEC_ESPI_MSVW04_SRC0_POS 16u +#define MEC_ESPI_MSVW04_SRC1_POS 17u +#define MEC_ESPI_MSVW04_SRC2_POS 16u +#define MEC_ESPI_MSVW04_SRC3_POS 19u +#define MEC_ESPI_MSVW05_SRC0_POS 20u +#define MEC_ESPI_MSVW05_SRC1_POS 21u +#define MEC_ESPI_MSVW05_SRC2_POS 22u +#define MEC_ESPI_MSVW05_SRC3_POS 23u +#define MEC_ESPI_MSVW06_SRC0_POS 24u +#define MEC_ESPI_MSVW06_SRC1_POS 25u +#define MEC_ESPI_MSVW06_SRC2_POS 26u +#define MEC_ESPI_MSVW06_SRC3_POS 27u + +#define MEC_ESPI_MSVW00_SRC0_VAL BIT(MEC_ESPI_MSVW00_SRC0_POS) +#define MEC_ESPI_MSVW00_SRC1_VAL BIT(MEC_ESPI_MSVW00_SRC1_POS) +#define MEC_ESPI_MSVW00_SRC2_VAL BIT(MEC_ESPI_MSVW00_SRC2_POS) +#define MEC_ESPI_MSVW00_SRC3_VAL BIT(MEC_ESPI_MSVW00_SRC3_POS) +#define MEC_ESPI_MSVW01_SRC0_VAL BIT(MEC_ESPI_MSVW01_SRC0_POS) +#define MEC_ESPI_MSVW01_SRC1_VAL BIT(MEC_ESPI_MSVW01_SRC1_POS) +#define MEC_ESPI_MSVW01_SRC2_VAL BIT(MEC_ESPI_MSVW01_SRC2_POS) +#define MEC_ESPI_MSVW01_SRC3_VAL BIT(MEC_ESPI_MSVW01_SRC3_POS) +#define MEC_ESPI_MSVW02_SRC0_VAL BIT(MEC_ESPI_MSVW02_SRC0_POS) +#define MEC_ESPI_MSVW02_SRC1_VAL BIT(MEC_ESPI_MSVW02_SRC1_POS) +#define MEC_ESPI_MSVW02_SRC2_VAL BIT(MEC_ESPI_MSVW02_SRC2_POS) +#define MEC_ESPI_MSVW02_SRC3_VAL BIT(MEC_ESPI_MSVW02_SRC3_POS) +#define MEC_ESPI_MSVW03_SRC0_VAL BIT(MEC_ESPI_MSVW03_SRC0_POS) +#define MEC_ESPI_MSVW03_SRC1_VAL BIT(MEC_ESPI_MSVW03_SRC1_POS) +#define MEC_ESPI_MSVW03_SRC2_VAL BIT(MEC_ESPI_MSVW03_SRC2_POS) +#define MEC_ESPI_MSVW03_SRC3_VAL BIT(MEC_ESPI_MSVW03_SRC3_POS) +#define MEC_ESPI_MSVW04_SRC0_VAL BIT(MEC_ESPI_MSVW04_SRC0_POS) +#define MEC_ESPI_MSVW04_SRC1_VAL BIT(MEC_ESPI_MSVW04_SRC1_POS) +#define MEC_ESPI_MSVW04_SRC2_VAL BIT(MEC_ESPI_MSVW04_SRC2_POS) +#define MEC_ESPI_MSVW04_SRC3_VAL BIT(MEC_ESPI_MSVW04_SRC3_POS) +#define MEC_ESPI_MSVW05_SRC0_VAL BIT(MEC_ESPI_MSVW05_SRC0_POS) +#define MEC_ESPI_MSVW05_SRC1_VAL BIT(MEC_ESPI_MSVW05_SRC1_POS) +#define MEC_ESPI_MSVW05_SRC2_VAL BIT(MEC_ESPI_MSVW05_SRC2_POS) +#define MEC_ESPI_MSVW05_SRC3_VAL BIT(MEC_ESPI_MSVW05_SRC3_POS) +#define MEC_ESPI_MSVW06_SRC0_VAL BIT(MEC_ESPI_MSVW06_SRC0_POS) +#define MEC_ESPI_MSVW06_SRC1_VAL BIT(MEC_ESPI_MSVW06_SRC1_POS) +#define MEC_ESPI_MSVW06_SRC2_VAL BIT(MEC_ESPI_MSVW06_SRC2_POS) +#define MEC_ESPI_MSVW06_SRC3_VAL BIT(MEC_ESPI_MSVW06_SRC3_POS) + +/* + * 0 <= v <= 6 + * 0 <= s <= 3 + */ +#define MEC_ESPI_MSVW_00_06_GIRQ_POS(v, s) \ + (((uint32_t)(v) * 4U) + (uint32_t)(s)) + +#define MEC_ESPI_VSVW_07_10_GIRQ 25u +#define MEC_ESPI_VSVW_07_10_NVIC 16u + +#define MEC_ESPI_MSVW07_SRC0_POS 0u +#define MEC_ESPI_MSVW07_SRC1_POS 1u +#define MEC_ESPI_MSVW07_SRC2_POS 2u +#define MEC_ESPI_MSVW07_SRC3_POS 3u +#define MEC_ESPI_MSVW08_SRC0_POS 4u +#define MEC_ESPI_MSVW08_SRC1_POS 5u +#define MEC_ESPI_MSVW08_SRC2_POS 6u +#define MEC_ESPI_MSVW08_SRC3_POS 7u +#define MEC_ESPI_MSVW09_SRC0_POS 8u +#define MEC_ESPI_MSVW09_SRC1_POS 9u +#define MEC_ESPI_MSVW09_SRC2_POS 10u +#define MEC_ESPI_MSVW09_SRC3_POS 11u +#define MEC_ESPI_MSVW10_SRC0_POS 12u +#define MEC_ESPI_MSVW10_SRC1_POS 13u +#define MEC_ESPI_MSVW10_SRC2_POS 14u +#define MEC_ESPI_MSVW10_SRC3_POS 15u + +/* + * 7 <= v <= 10 + * 0 <= s <= 3 + */ +#define MEC_ESPI_MSVW_07_10_GIRQ_POS(v, s) \ + ((((uint32_t)(v) - 7ul) * 4U) + (uint32_t)(s)) + +/* Master-to-Slave VW byte indices(offsets) */ +#define MSVW_INDEX_OFS 0u +#define MSVW_MTOS_OFS 1u +#define MSVW_SRC0_ISEL_OFS 4u +#define MSVW_SRC1_ISEL_OFS 5u +#define MSVW_SRC2_ISEL_OFS 6u +#define MSVW_SRC3_ISEL_OFS 7u +#define MSVW_SRC0_OFS 8u +#define MSVW_SRC1_OFS 9u +#define MSVW_SRC2_OFS 10u +#define MSVW_SRC3_OFS 11u + +/* Slave-to-Master VW byte indices(offsets) */ +#define SMVW_INDEX_OFS 0u +#define SMVW_STOM_OFS 1u +#define SMVW_CHANGED_OFS 2u +#define SMVW_SRC0_OFS 4u +#define SMVW_SRC1_OFS 5u +#define SMVW_SRC2_OFS 6u +#define SMVW_SRC3_OFS 7u + + +/* Master-to-Slave Virtual Wire 96-bit register */ +#define MEC_MSVW_SRC0_IRQ_SEL_POS 0u +#define MEC_MSVW_SRC1_IRQ_SEL_POS 8u +#define MEC_MSVW_SRC2_IRQ_SEL_POS 16u +#define MEC_MSVW_SRC3_IRQ_SEL_POS 24u + +#define MEC_MSVW_SRC_IRQ_SEL_MASK0 0x0Ful +#define MEC_MSVW_SRC0_IRQ_SEL_MASK \ + SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC0_IRQ_SEL_POS) +#define MEC_MSVW_SRC1_IRQ_SEL_MASK \ + SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC1_IRQ_SEL_POS) +#define MEC_MSVW_SRC2_IRQ_SEL_MASK \ + SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC2_IRQ_SEL_POS) +#define MEC_MSVW_SRC3_IRQ_SEL_MASK \ + SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC3_IRQ_SEL_POS) + +#define MEC_MSVW_SRC_IRQ_SEL_LVL_LO 0x00ul +#define MEC_MSVW_SRC_IRQ_SEL_LVL_HI 0x01ul +#define MEC_MSVW_SRC_IRQ_SEL_DIS 0x04ul +#define MEC_MSVW_SRC_IRQ_SEL_EDGE_FALL 0x0Dul +#define MEC_MSVW_SRC_IRQ_SEL_EDGE_RISE 0x0Eul +#define MEC_MSVW_SRC_IRQ_SEL_EDGE_BOTH 0x0Ful + +/* + * 0 <= src <= 3 + * isel = MEC_MSVW_SRC_IRQ_SEL_LVL_LO, ... + */ +#define MEC_MSVW_SRC_IRQ_SEL_VAL(src, isel) \ + ((uint32_t)(isel) << ((src) * 8U)) + +#define MEC_MSVW_SRC0_POS 0ul +#define MEC_MSVW_SRC1_POS 8ul +#define MEC_MSVW_SRC2_POS 16ul +#define MEC_MSVW_SRC3_POS 24ul + +#define MEC_MSVW_SRC_MASK0 0x01ul + +#define MEC_MSVW_SRC0_MASK BIT(0) +#define MEC_MSVW_SRC1_MASK BIT(8) +#define MEC_MSVW_SRC2_MASK BIT(16) +#define MEC_MSVW_SRC3_MASK BIT(24) + +/* + * 0 <= src <= 3 + * val = 0 or 1 + */ +#define MEC_MSVW_SRC_VAL(src, val) \ + ((uint32_t)(val & 0x01u) << ((src) * 8U)) + +/* Slave-to-Master Virtual Wire 64-bit register */ + +/* MSVW helper inline functions */ + +/* Interfaces to any C modules */ +#ifdef __cplusplus +extern "C" { +#endif + +enum espi_msvw_src { + MSVW_SRC0 = 0u, + MSVW_SRC1, + MSVW_SRC2, + MSVW_SRC3 +}; + +enum espi_smvw_src { + SMVW_SRC0 = 0u, + SMVW_SRC1, + SMVW_SRC2, + SMVW_SRC3 +}; + +enum espi_msvw_irq_sel { + MSVW_IRQ_SEL_LVL_LO = 0x00ul, + MSVW_IRQ_SEL_LVL_HI = 0x01ul, + MSVW_IRQ_SEL_DIS = 0x04ul, + MSVW_IRQ_SEL_EDGE_FALL = 0x0Dul, + MSVW_IRQ_SEL_EDGE_RISE = 0x0Eul, + MSVW_IRQ_SEL_EDGE_BOTH = 0x0Ful +}; + +/* Used for both MSVW MTOS and SMVW STOM fields */ +enum espi_vw_rst_src { + VW_RST_SRC_ESPI_RESET = 0ul, + VW_RST_SRC_SYS_RESET, + VW_RST_SRC_SIO_RESET, + VW_RST_SRC_PLTRST, +}; + +/* Set/get the Host VWire index in specified MSVW register */ +static __attribute__ ((always_inline)) +inline void mec_espi_msvw_index_set(ESPI_MSVW_REG *p, uint8_t host_vw_index) +{ + p->INDEX = host_vw_index; +} + +static __attribute__ ((always_inline)) +inline uint8_t mec_espi_msvw_index_get(ESPI_MSVW_REG *p) +{ + return p->INDEX; +} + +/* + * This functions sets the two MTOS fields in a MSVW + * Reset source + * Reset value of SRC[3:0] + */ +static __attribute__ ((always_inline)) +inline void +mec_espi_msvw_mtos_set(ESPI_MSVW_REG *p, enum espi_vw_rst_src rst_src, + uint8_t rst_val) +{ + p->MTOS = (rst_src & 0x03u) | ((rst_val & 0x0Fu) << 4); +} + +/* + * Set the specified Master-to-Slave VWire's interrupt select field for + * the specified edge, level, or disabled. + * MSVW IRQ_SELECT is a 32-bit register where the four VWire's + * interrupt select fields are located on byte boundaries. + * Param p is a pointer to the 96-bit MSVW register. + * Param src is in [0:3] specifying one of the four VWire's. + * Param isel is the new value for the specified VWire's interrupt + * select field. IRQ_SELECT is the 32-bit word at bits[63:32] in the + * 96-bit MSVW register. + * IRQ_SELECT[3:0] = SRC0_IRQ_SELECT + * IRQ_SELECT[11:8] = SRC1_IRQ_SELECT + * IRQ_SELECT[19:16] = SRC1_IRQ_SELECT + * IRQ_SELECT[27:24] = SRC1_IRQ_SELECT + * The MSVW registers are byte accessible allowing us to avoid a + * read-modify-write. + */ +static __attribute__ ((always_inline)) +inline void +mec_espi_msvw_irq_sel_set(ESPI_MSVW_REG *p, enum espi_msvw_src src, + enum espi_msvw_irq_sel isel) +{ + volatile uint8_t *psrc = (volatile uint8_t *)&p->SRC_IRQ_SEL; + + *(psrc + (uintptr_t) src) = isel; +} + +/* + * Set all IRQ_SEL fields in a MSVW. + * Parameter isel_all must have IRQ_SEL fields at + * b[3:0], b[11:8], b[19:16], b[27:24]. + */ +static __attribute__ ((always_inline)) +inline void mec_espi_msvw_irq_sel_set_all(ESPI_MSVW_REG *p, uint32_t isel_all) +{ + p->SRC_IRQ_SEL = isel_all; +} + +/* + * Set the specified Master-to-Slave VWire state. + * MSVW.SRC is a 32-bit component at bits[95:64] where states of the + * four VWire's it controls are located on byte boundaries. + * Param p is a pointer to the 96-bit MSVW register. + * Param src is in [0:3] specifying one of the four VWire's. + * Param src_val is the new VWire state. + * SRC member is the 32-bit word at bits[95:64] in the MSVW structure. + * SRC[3:0] = SRC0 VWire state + * SRC[11:8] = SRC1 VWire state + * SRC[19:16] = SRC1 VWire state + * SRC[27:24] = SRC1 VWire state + * The MSVW registers are byte accessible allowing us to avoid a + * read-modify-write. + */ +static __attribute__ ((always_inline)) +inline void +mec_espi_msvw_set(ESPI_MSVW_REG *p, enum espi_msvw_src src, uint8_t src_val) +{ + volatile uint8_t *psrc = (volatile uint8_t *)&p->SRC; + + *(psrc + (uintptr_t) src) = src_val; +} + +static __attribute__ ((always_inline)) +inline uint8_t mec_espi_msvw_get(ESPI_MSVW_REG *p, enum espi_msvw_src src) +{ + return (uint8_t) ((p->SRC >> (src << 3)) & 0x01ul); +} + +/* + * Return 32-bit unsigned word containing all 4 MSVW SRC bits in + * bit positions 0, 8, 16, and 24. + */ +static __attribute__ ((always_inline)) +inline uint32_t mec_espi_msvw_get_all(ESPI_MSVW_REG *p) +{ + return p->SRC; +} + +/* + * Write 32-bit unsigned word containing all 4 MSVW SRC bits in + * bit positions 0, 8, 16, and 24. + * NOTE: eSPI master will only see changes to Master-to-Slave VWires + * if it requests reading them. + */ +static __attribute__ ((always_inline)) +inline void mec_espi_msvw_set_all(ESPI_MSVW_REG *p, uint32_t val) +{ + p->SRC = val; +} + +/* SMVW helper inline functions */ + +/* + * Set the Host VWire index this SMVW implements. + */ +static __attribute__ ((always_inline)) +inline void mec_espi_smvw_index_set(ESPI_SMVW_REG *p, uint8_t host_vw_index) +{ + p->INDEX = host_vw_index; +} + +/* + * Set the Host VWire index this SMVW implements. + */ +static __attribute__ ((always_inline)) +inline uint8_t mec_espi_smvw_index_get(ESPI_SMVW_REG *p) +{ + return p->INDEX; +} + +/* + * This functions sets the two STOM fields in a SMVW + * Reset source + * Reset value of SRC[3:0] + */ +static __attribute__ ((always_inline)) +inline void +mec_espi_msvw_stom_set(ESPI_SMVW_REG *p, enum espi_vw_rst_src rst_src, + uint8_t rst_bitmap) +{ + p->STOM = (rst_src & 0x03u) | ((rst_bitmap & 0x0Fu) << 4); +} + +/* + * Return SMVW source change bitmap + * b[3:0] = SRC[3:0] change where 1=change, 0=no change + * A SRC change bit == 1 indicates the EC has updated the corresponding + * SRC bit with a new value. HW will transmit all 4 SMVW bits when the + * eSPI bus becomes available. Once transmitted HW will clear SRC CHG bit(s). + */ +static __attribute__ ((always_inline)) +inline uint8_t mec_espi_smvw_get_chg(ESPI_SMVW_REG *p) +{ + return p->SRC_CHG; +} + +/* + * Return 32-bit unsigned word containing all 4 SMVW SRC bits in + * bit positions 0, 8, 16, and 24. + */ +static __attribute__ ((always_inline)) +inline uint32_t mec_espi_smvw_get_all(ESPI_SMVW_REG *p) +{ + return p->SRC; +} + +/* + * Write 32-bit unsigned word containing all 4 SMVW SRC bits in + * bit positions 0, 8, 16, and 24. + */ +static __attribute__ ((always_inline)) +inline void mec_espi_smvw_set_all(ESPI_SMVW_REG *p, uint32_t new_srcs) +{ + p->SRC = new_srcs; +} + +/* + * Write 32-bit unsigned word containing all 4 SMVW SRC bits in + * bit positions 0, 8, 16, and 24 from bitmap where + * bitmap[0] -> SRC bit[0] + * bitmap[1] -> SRC bit[8] + * bitmap[2] -> SRC bit[16] + * bitmap[3] -> SRC bit[24] + */ +static __attribute__ ((always_inline)) +inline void mec_espi_smvw_set_all_bitmap(ESPI_SMVW_REG *p, uint8_t src_bitmap) +{ + uint32_t i, srcs; + + srcs = 0ul; + for (i = 0; i < 4ul; i++) { + if (src_bitmap & (1ul << i)) { + srcs |= (1ul << (i * 8U)); + } + } + + p->SRC = srcs; +} + +/* + * Get the specified Slave-to-Master VWire state. + * SMVW.SRC is a 32-bit register located at bits[63:32] where the four + * VWire's it controls are located on byte boundaries. + * Param p is a pointer to the 64-bit SMVW register. + * Param src is in [0:3] specifying one of the four VWire's. + * Param src_val is the new VWire state. + * SRC member is the 32-bit word at bits[63:32] in the SMVW structure. + * SRC[3:0] = SRC0 VWire state + * SRC[11:8] = SRC1 VWire state + * SRC[19:16] = SRC1 VWire state + * SRC[27:24] = SRC1 VWire state + */ +static __attribute__ ((always_inline)) +inline uint8_t mec_espi_smvw_get(ESPI_SMVW_REG *p, enum espi_smvw_src src) +{ + return (uint8_t) ((p->SRC >> (src * 8U)) & 0x01ul); +} + +/* + * Set the specified Slave-to-Master VWire state. + * SMVW.SRC is a 32-bit register located at bits[63:32] where the four + * VWire's it controls are located on byte boundaries. + * Param p is a pointer to the 64-bit SMVW register. + * Param src is in [0:3] specifying one of the four VWire's. + * Param src_val is the new VWire state. + * SRC member is the 32-bit word at bits[63:32] in the SMVW structure. + * SRC[3:0] = SRC0 VWire state + * SRC[11:8] = SRC1 VWire state + * SRC[19:16] = SRC1 VWire state + * SRC[27:24] = SRC1 VWire state + * The SMVW registers are byte accessible allowing us to avoid a + * read-modify-write. + */ +static __attribute__ ((always_inline)) +inline void +mec_espi_smvw_set(ESPI_SMVW_REG *p, enum espi_smvw_src src, uint8_t new_val) +{ + volatile uint8_t *p8 = (volatile uint8_t *)&p->SRC; + + *(p8 + (uintptr_t) src) = new_val; +} + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _COMPONENT_ESPI_VW_H */ +/* end espi_vw.h */ +/** @} + */ diff --git a/mec/mec172x/component/global_cfg.h b/mec/mec172x/component/global_cfg.h new file mode 100644 index 0000000..12024b3 --- /dev/null +++ b/mec/mec172x/component/global_cfg.h @@ -0,0 +1,157 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file global_cfg.h + * MEC172x Global Configuration Registers + */ +/** @defgroup MEC172x Peripherals GlobalConfig + */ + +#ifndef _COMPONENT_GLOBAL_CFG_H +#define _COMPONENT_GLOBAL_CFG_H + +#include +#include + +#include +#include + +/* ===================================================================*/ +/* ================ Global Config ============= */ +/* ===================================================================*/ + +#define MCHP_GCFG_BASE_ADDR 0x400FFF00ul + +/* + * Device and Revision ID 32-bit register + * b[7:0] = Revision + * b[15:8] = Device Sub-ID + * b[31:16] = Device ID + * This register can be accesses as bytes or a single 32-bit read from + * the EC. Host access byte access via the Host visible configuration + * register space at 0x2E/0x2F(default). + */ +#define MCHP_GCFG_DEV_ID_REG32_OFS 0x1Cu +#define MCHP_GCFG_DEV_ID_REG_MASK 0xFFFFFFFFul +#define MCHP_GCFG_REV_ID_POS 0 +#define MCHP_GCFG_DID_REV_MASK0 0xFFul +#define MCHP_GCFG_DID_REV_MASK 0xFFul +#define MCHP_GCFG_DID_SUB_ID_POS 8 +#define MCHP_GCFG_DID_SUB_ID_MASK0 0xFFul +#define MCHP_GCFG_DID_SUB_ID_MASK \ + SHLU32(MCHP_GCFG_DID_SUB_ID_MASK0, MCHP_GCFG_DID_SUB_ID_POS) +#define MCHP_GCFG_DID_DEV_ID_POS 16 +#define MCHP_GCFG_DID_DEV_ID_MASK0 0xFFFFul +#define MCHP_GCFG_DID_DEV_ID_MASK \ + SHLU32(MCHP_GCFG_DID_DEV_ID_MASK0, MCHP_GCFG_DID_DEV_ID_POS) + +/* Byte[0] at offset 0x1C is the 8-bit revision ID */ +#define MCHP_GCFG_REV_ID_REG_OFS 0x1Cu +#define MCHP_GCFG_REV_A1 0x02u +#define MCHP_GCFG_REV_B0 0x03u + +/* + * Byte[1] at offset 0x1D is the 8-bit Sub-ID + * bits[3:0] = package type + * bits[7:4] = chip family + */ +#define MCHP_GCFG_SUB_ID_OFS 0x1Du +#define MCHP_GCFG_SUB_ID_PKG_POS 0u +#define MCHP_GCFG_SUB_ID_PKG_MASK0 0x0Fu +#define MCHP_GCFG_SUB_ID_PKG_MASK 0x0Fu +#define MCHP_GCFG_SUB_ID_PKG_UNDEF 0x00u +#define MCHP_GCFG_SUB_ID_PKG_64_PIN 0x01u +#define MCHP_GCFG_SUB_ID_PKG_84_PIN 0x02u +#define MCHP_GCFG_SUB_ID_PKG_128_PIN 0x03u +#define MCHP_GCFG_SUB_ID_PKG_144_PIN 0x04u +#define MCHP_GCFG_SUB_ID_PKG_176_PIN 0x07u +/* chip family field */ +#define MCHP_GCFG_SUB_ID_FAM_POS 4u +#define MCHP_GCFG_SUB_ID_FAM_MASK0 0x0Fu +#define MCHP_GCFG_SUB_ID_FAM_MASK 0xF0u +#define MCHP_GCFG_SUB_ID_FAM_UNDEF 0x00u +#define MCHP_GCFG_SUB_ID_FAM_1 0x01u +#define MCHP_GCFG_SUB_ID_FAM_2 0x02u +#define MCHP_GCFG_SUB_ID_FAM_3 0x03u +#define MCHP_GCFG_SUB_ID_FAM_4 0x04u +#define MCHP_GCFG_SUB_ID_FAM_5 0x05u +#define MCHP_GCFG_SUB_ID_FAM_6 0x06u +#define MCHP_GCFG_SUB_ID_FAM_7 0x07u + +#define MCHP_GCFG_DEV_ID_LSB_OFS 0x1Eu +#define MCHP_GCFG_DEV_ID_MSB_OFS 0x1Fu +#define MCHP_GCFG_DEV_ID_172X 0x0022u +#define MCHP_GCFG_DEV_ID_172X_LSB 0x22u +#define MCHP_GCFG_DEV_ID_172X_MSB 0x00u + +/* SZ 144-pin package parts */ +#define MCHP_GCFG_DEVID_1723_144 0x00223400u +#define MCHP_GCFG_DEVID_1727_144 0x00227400u +/* LJ 176-pin package parts */ +#define MCHP_GCFG_DID_1721_176 0x00222700u +#define MCHP_GCFG_DID_1723_176 0x00223700u +#define MCHP_GCFG_DID_1727_176 0x00227700u + +/* Legacy Device ID value */ +#define MCHP_CCFG_LEGACY_DID_REG_OFS 0x20 +#define MCHP_GCFG_LEGACY_DEV_ID 0xFE + +/* + * Host access via configuration port (default I/O locations 0x2E/0x2F) + */ +#define MCHP_HOST_CFG_INDEX_IO_DFLT 0x2E +#define MCHP_HOST_CFG_DATA_IO_DFLT 0x2F +#define MCHP_HOST_CFG_UNLOCK 0x55 +#define MCHP_HOST_CFG_LOCK 0xAA +/* + * Logical Device Configuration Indices. + */ +#define MCHP_HOST_CFG_LDN_IDX 0x07 +#define MCHP_HOST_CFG_LD_ACTIVATE_IDX 0x30 +#define MCHP_HOST_CFG_LD_BASE_ADDR_IDX 0x34 +#define MCHP_HOST_CFG_LD_CFG_SEL_IDX 0xF0 + + +/* Read 32-bit Device, Sub, and Revision ID */ +#define MCHP_DEVICE_REV_ID() \ + REG32(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_DEV_ID_REG32_OFS) + +/* Read 16-bit Device ID */ +#define MCHP_DEVICE_ID() \ + REG16(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_DEV_ID_LSB_OFS) + +/* Read 8-bit Sub ID */ +#define MCHP_DEV_SUB_ID() \ + REG8(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_SUB_ID_OFS) + +/* Read 8-bit Revision ID */ +#define MCHP_REVISION_ID() \ + REG8(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_REV_ID_REG_OFS) + +#endif /* #ifndef _COMPONENT_GLOBAL_CFG_H */ +/* end global_cfg.h */ +/** @} + */ diff --git a/mec/mec172x/component/glue.h b/mec/mec172x/component/glue.h new file mode 100644 index 0000000..3ee1b0e --- /dev/null +++ b/mec/mec172x/component/glue.h @@ -0,0 +1,81 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file glue.h + * MEC172x Glue Logic controller registers + */ +/** @defgroup MEC172x Peripherals Glue Logic + */ + +#ifndef _COMPONENT_GLUE_H +#define _COMPONENT_GLUE_H + +#include +#include + +#include +#include + +#define MCHP_GLUE_0_BASE_ADDR 0x400F3C00ul + +#define MCHP_GLUE_GIRQ 21u +#define MCHP_GLUE_NVIC_GIRQ 13u +#define MCHP_GLUE_POS 26u +#define MCHP_GLUE_NVIC 172u +#define MCHP_GLUE_GIRQ_VAL BIT(MCHP_GLUE_POS) + +/* Glue runtime S0ix state detection register at 0x04 */ +#define MCHP_GLUE_S0IX_DET_OFS 0x04u +#define MCHP_GLUE_S0IX_DET_MASK 0x01u +#define MCHP_GLUE_S0IX_DET_EN BIT(0) + +/* EC-only registers */ + +/* Glue PWRGD State source configuration at 0x10C */ +#define MCHP_GLUE_PGSC_OFS 0x10Cu +#define MCHP_GLUE_PGSC_MSK 0x03u +#define MCHP_GLUE_PGSC_PG2_PG 0x00u +#define MCHP_GLUE_PGSC_PG2_S0IX 0x01u +#define MCHP_GLUE_PGSC_PG2_PG_AND_S0IX 0x03u + +/* Glue S0ix State Detection Configuration at 0x110 */ +#define MCHP_GLUE_S0SDC_OFS 0x110u +#define MCHP_GLUE_S0SDC_MASK 0x3Fu +#define MCHP_GLUE_S0SDC_SRC_POS 0 +#define MCHP_GLUE_S0SDC_SRC_MSK 0x03u +#define MCHP_GLUE_S0SDC_SRC_LO 0x00 +#define MCHP_GLUE_S0SDC_SRC_SLP_S0 0x01 +#define MCHP_GLUE_S0SDC_SRC_C10 0x02 +#define MCHP_GLUE_S0SDC_SRC_C10_SLP_S0 0x03 +#define MCHP_GLUE_S0SDC_SLP_S0_INV BIT(2) +#define MCHP_GLUE_S0SDC_C10_INV BIT(3) +#define MCHP_GLUE_S0SDC_C10_VW BIT(4) +#define MCHP_GLUE_S0SDC_FW_PGSEL BIT(5) + +#endif /* #ifndef _COMPONENT_GLUE_H */ +/* end glue.h */ +/** @} + */ diff --git a/mec/mec172x/component/gpio.h b/mec/mec172x/component/gpio.h new file mode 100644 index 0000000..7fad27f --- /dev/null +++ b/mec/mec172x/component/gpio.h @@ -0,0 +1,529 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file gpio.h + * MEC172x GPIO definitions + */ +/** @defgroup MEC172x Peripherals GPIO + */ + +#ifndef _COMPONENT_GPIO_H +#define _COMPONENT_GPIO_H + +#include +#include + +#include +#include + +#define NUM_MCHP_GPIO_PORTS 6u +#define MAX_NUM_MCHP_GPIO (NUM_MCHP_GPIO_PORTS * 32u) + +#define MCHP_GPIO_CTRL_BASE 0x40081000ul +#define MCHP_GPIO_PARIN_OFS 0x0300ul +#define MCHP_GPIO_PAROUT_OFS 0x0380ul +#define MCHP_GPIO_LOCK_OFS 0x03E8ul +#define MCHP_GPIO_CTRL2_OFS 0x0500ul + +#define MCHP_GPIO_PARIN_BASE (MCHP_GPIO_CTRL_BASE + MCHP_GPIO_PARIN_OFS) +#define MCHP_GPIO_PAROUT_BASE (MCHP_GPIO_CTRL_BASE + MCHP_GPIO_PAROUT_OFS) +#define MCHP_GPIO_LOCK_BASE (MCHP_GPIO_CTRL_BASE + MCHP_GPIO_LOCK_OFS) +#define MCHP_GPIO_CTRL2_BASE (MCHP_GPIO_CTRL_BASE + MCHP_GPIO_CTRL2_OFS) + +/* + * !!! MEC data sheet pin numbering is octal !!! + * n = pin number in octal or the equivalent in decimal or hex + * Example: GPIO135 + * n = 0135 or n = 0x5D or n = 93 + */ +#define MCHP_GPIO_CTRL_ADDR(n) \ + ((uintptr_t)(MCHP_GPIO_CTRL_BASE) + ((uintptr_t)(n) * 4U)) + +#define MCHP_GPIO_CTRL2_ADDR(n) \ + ((uintptr_t)(MCHP_GPIO_CTRL2_BASE + MCHP_GPIO_CTRL2_OFS) + \ + ((uintptr_t)(n) * 4U)) + +/* + * GPIO Parallel In registers. + * Each register contains 32 GPIO's + * PARIN0 for GPIO_0000 - 0037 + * PARIN1 for GPIO_0040 - 0077 + * PARIN2 for GPIO_0100 - 0137 + * PARIN3 for GPIO_0140 - 0177 + * PARIN4 for GPIO_0200 - 0237 + * PARIN5 for GPIO_0240 - 0277 + */ +#define MCHP_GPIO_PARIN_ADDR(n) ((uintptr_t)(MCHP_GPIO_BASE_ADDR) + \ + (uintptr_t)(MCHP_GPIO_PARIN_OFS) + ((n) * 4U)) + +#define MCHP_GPIO_PARIN0_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) + \ + (uintptr_t)(MCHP_GPIO_PARIN_OFS)) + +#define MCHP_GPIO_PARIN1_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) + \ + (uintptr_t)(MCHP_GPIO_PARIN_OFS) +0x04ul) + +#define MCHP_GPIO_PARIN2_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) + \ + (uintptr_t)(MCHP_GPIO_PARIN_OFS) +0x08ul) + +#define MCHP_GPIO_PARIN3_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) + \ + (uintptr_t)(MCHP_GPIO_PARIN_OFS) +0x0Cul) + +#define MCHP_GPIO_PARIN4_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) + \ + (uintptr_t)(MCHP_GPIO_PARIN_OFS) +0x10ul) + +#define MCHP_GPIO_PARIN5_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) + \ + (uintptr_t)(MCHP_GPIO_PARIN_OFS) +0x14ul) + +/* + * GPIO Parallel Out registers. + * Each register contains 32 GPIO's + * PAROUT0 for GPIO_0000 - 0037 + * PAROUT1 for GPIO_0040 - 0077 + * PAROUT2 for GPIO_0100 - 0137 + * PAROUT3 for GPIO_0140 - 0177 + * PAROUT4 for GPIO_0200 - 0237 + * PAROUT5 for GPIO_0240 - 0277 + */ +#define MCHP_GPIO_PAROUT_ADDR(n) ((uintptr_t)(MCHP_GPIO_BASE_ADDR) + \ + (uintptr_t)(MCHP_GPIO_PAROUT_OFS) + \ + ((n) * 4U)) + +#define MCHP_GPIO_PAROUT0_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) + \ + (uintptr_t)(MCHP_GPIO_PAROUT_OFS)) + +#define MCHP_GPIO_PAROUT1_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) + \ + (uintptr_t)(MCHP_GPIO_PAROUT_OFS) +0x04ul) + +#define MCHP_GPIO_PAROUT2_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) + \ + (uintptr_t)(MCHP_GPIO_PAROUT_OFS) +0x08ul) + +#define MCHP_GPIO_PAROUT3_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) + \ + (uintptr_t)(MCHP_GPIO_PAROUT_OFS) +0x0Cul) + +#define MCHP_GPIO_PAROUT4_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) + \ + (uintptr_t)(MCHP_GPIO_PAROUT_OFS) +0x10ul) + +#define MCHP_GPIO_PAROUT5_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) + \ + (uintptr_t)(MCHP_GPIO_PAROUT_OFS) +0x14ul) + +/* + * MEC172XH-B0-SZ (144-pin) + */ +#define MCHP_GPIO_PORT_A_BITMAP 0x7FFFFF9Dul /* GPIO_0000 - 0036 GIRQ11 */ +#define MCHP_GPIO_PORT_B_BITMAP 0x0FFFFFFDul /* GPIO_0040 - 0076 GIRQ10 */ +#define MCHP_GPIO_PORT_C_BITMAP 0x07FF3CF7ul /* GPIO_0100 - 0136 GIRQ09 */ +#define MCHP_GPIO_PORT_D_BITMAP 0x272EFFFFul /* GPIO_0140 - 0176 GIRQ08 */ +#define MCHP_GPIO_PORT_E_BITMAP 0x00DE00FFul /* GPIO_0200 - 0236 GIRQ12 */ +#define MCHP_GPIO_PORT_F_BITMAP 0x0000397Ful /* GPIO_0240 - 0276 GIRQ26 */ + +#define MCHP_GPIO_PORT_A_DRVSTR_BITMAP 0x7FFFFF9Dul +#define MCHP_GPIO_PORT_B_DRVSTR_BITMAP 0x0FFFFFFDul +#define MCHP_GPIO_PORT_C_DRVSTR_BITMAP 0x07FF3CF7ul +#define MCHP_GPIO_PORT_D_DRVSTR_BITMAP 0x272EFFFFul +#define MCHP_GPIO_PORT_E_DRVSTR_BITMAP 0x00DE00FFul +#define MCHP_GPIO_PORT_F_DRVSTR_BITMAP 0x0000397Ful + +/* GPIO Port to ECIA GIRQ mapping */ +#define MCHP_GPIO_PORT_A_GIRQ 11u +#define MCHP_GPIO_PORT_B_GIRQ 10u +#define MCHP_GPIO_PORT_C_GIRQ 9u +#define MCHP_GPIO_PORT_D_GIRQ 8u +#define MCHP_GPIO_PORT_E_GIRQ 12u +#define MCHP_GPIO_PORT_F_GIRQ 26u + +/* + * GPIO Port GIRQ to NVIC external input + * GPIO GIRQ's are always aggregated. + */ +#define MCHP_GPIO_PORT_A_NVIC 3u +#define MCHP_GPIO_PORT_B_NVIC 2u +#define MCHP_GPIO_PORT_C_NVIC 1u +#define MCHP_GPIO_PORT_D_NVIC 0u +#define MCHP_GPIO_PORT_E_NVIC 4u +#define MCHP_GPIO_PORT_F_NVIC 17u + +/* 32-bit Control register */ +#define MCHP_GPIO_CTRL_MASK 0x0101FFFFul +/* bits[15:0] of Control register */ +#define MCHP_GPIO_CTRL_CFG_MASK 0xFFFFul + +/* Disable interrupt detect and pad */ +#define MCHP_GPIO_CTRL_DIS_PIN 0x8040ul + +#define MCHP_GPIO_CTRL_DFLT 0x8040ul +#define MCHP_GPIO_CTRL_DFLT_MASK 0xfffful + +#define GPIO000_CTRL_DFLT 0x1040ul +#define GPIO062_CTRL_DFLT 0x8240ul +#define GPIO116_CTRL_DFLT 0x0041ul +#define GPIO161_CTRL_DFLT 0x1040ul +#define GPIO162_CTRL_DFLT 0x1040ul +#define GPIO170_CTRL_DFLT 0x0041ul +#define GPIO234_CTRL_DFLT 0x1040ul + +/* GPIO Control register field definitions. */ + +/* bits[1:0] internal pull up/down selection */ +#define MCHP_GPIO_CTRL_PUD_POS 0u +#define MCHP_GPIO_CTRL_PUD_MASK0 0x03ul +#define MCHP_GPIO_CTRL_PUD_MASK 0x03ul +#define MCHP_GPIO_CTRL_PUD_NONE 0x00ul +#define MCHP_GPIO_CTRL_PUD_PU 0x01ul +#define MCHP_GPIO_CTRL_PUD_PD 0x02ul +/* Repeater(keeper) mode */ +#define MCHP_GPIO_CTRL_PUD_RPT 0x03ul + +/* bits[3:2] power gating */ +#define MCHP_GPIO_CTRL_PWRG_POS 2u +#define MCHP_GPIO_CTRL_PWRG_MASK0 0x03ul +#define MCHP_GPIO_CTRL_PWRG_VTR_IO 0x00U +#define MCHP_GPIO_CTRL_PWRG_VCC_IO SHLU32(1U, MCHP_GPIO_CTRL_PWRG_POS) +#define MCHP_GPIO_CTRL_PWRG_OFF SHLU32(2U, MCHP_GPIO_CTRL_PWRG_POS) +#define MCHP_GPIO_CTRL_PWRG_RSVD SHLU32(3U, MCHP_GPIO_CTRL_PWRG_POS) +#define MCHP_GPIO_CTRL_PWRG_MASK SHLU32(3U, MCHP_GPIO_CTRL_PWRG_POS) + +/* bits[7:4] interrupt detection mode */ +#define MCHP_GPIO_CTRL_IDET_POS 4u +#define MCHP_GPIO_CTRL_IDET_MASK0 0x0Ful +#define MCHP_GPIO_CTRL_IDET_LVL_LO 0x00U +#define MCHP_GPIO_CTRL_IDET_LVL_HI SHLU32(1U, MCHP_GPIO_CTRL_IDET_POS) +#define MCHP_GPIO_CTRL_IDET_DISABLE SHLU32(4U, MCHP_GPIO_CTRL_IDET_POS) +#define MCHP_GPIO_CTRL_IDET_REDGE SHLU32(0xDU, MCHP_GPIO_CTRL_IDET_POS) +#define MCHP_GPIO_CTRL_IDET_FEDGE SHLU32(0xEU, MCHP_GPIO_CTRL_IDET_POS) +#define MCHP_GPIO_CTRL_IDET_BEDGE SHLU32(0xFU, MCHP_GPIO_CTRL_IDET_POS) +#define MCHP_GPIO_CTRL_IDET_MASK SHLU32(0xFU, MCHP_GPIO_CTRL_IDET_POS) + +/* bit[8] output buffer type: push-pull or open-drain */ +#define MCHP_GPIO_CTRL_BUFT_POS 8u +#define MCHP_GPIO_CTRL_BUFT_MASK BIT(MCHP_GPIO_CTRL_BUFT_POS) +#define MCHP_GPIO_CTRL_BUFT_OPENDRAIN BIT(MCHP_GPIO_CTRL_BUFT_POS) +#define MCHP_GPIO_CTRL_BUFT_PUSHPULL 0x00U + +/* bit[9] direction */ +#define MCHP_GPIO_CTRL_DIR_POS 9u +#define MCHP_GPIO_CTRL_DIR_MASK BIT(MCHP_GPIO_CTRL_DIR_POS) +#define MCHP_GPIO_CTRL_DIR_OUTPUT BIT(MCHP_GPIO_CTRL_DIR_POS) +#define MCHP_GPIO_CTRL_DIR_INPUT 0U + +/* + * bit[10] Alternate output disable. Default==0(alternate output enabled) + * GPIO output value is controlled by bit[16] of this register. + * Set bit[10]=1 if you wish to control pin output using the parallel + * GPIO output register bit for this pin. + */ +#define MCHP_GPIO_CTRL_AOD_POS 10u +#define MCHP_GPIO_CTRL_AOD_MASK BIT(MCHP_GPIO_CTRL_AOD_POS) +#define MCHP_GPIO_CTRL_AOD_DIS BIT(MCHP_GPIO_CTRL_AOD_POS) + +/* bit[11] GPIO function output polarity */ +#define MCHP_GPIO_CTRL_POL_POS 11u +#define MCHP_GPIO_CTRL_POL_INVERT BIT(MCHP_GPIO_CTRL_POL_POS) + +/* bits[14:12] pin mux (fucntion) */ +#define MCHP_GPIO_CTRL_MUX_POS 12u +#define MCHP_GPIO_CTRL_MUX_MASK0 0x07ul +#define MCHP_GPIO_CTRL_MUX_MASK SHLU32(0x7U, MCHP_GPIO_CTRL_MUX_POS) +#define MCHP_GPIO_CTRL_MUX_F0 0x00U +#define MCHP_GPIO_CTRL_MUX_GPIO MCHP_GPIO_CTRL_MUX_F0 +#define MCHP_GPIO_CTRL_MUX_F1 SHLU32(1U, MCHP_GPIO_CTRL_MUX_POS) +#define MCHP_GPIO_CTRL_MUX_F2 SHLU32(2U, MCHP_GPIO_CTRL_MUX_POS) +#define MCHP_GPIO_CTRL_MUX_F3 SHLU32(3U, MCHP_GPIO_CTRL_MUX_POS) +#define MCHP_GPIO_CTRL_MUX_F4 SHLU32(4U, MCHP_GPIO_CTRL_MUX_POS) +#define MCHP_GPIO_CTRL_MUX_F5 SHLU32(5U, MCHP_GPIO_CTRL_MUX_POS) +#define MCHP_GPIO_CTRL_MUX_F6 SHLU32(6U, MCHP_GPIO_CTRL_MUX_POS) +#define MCHP_GPIO_CTRL_MUX_F7 SHLU32(7U, MCHP_GPIO_CTRL_MUX_POS) +#define MCHP_GPIO_CTRL_MUX(n) SHLU32(((n) & 0x7u), MCHP_GPIO_CTRL_MUX_POS) + +/* + * bit[15] Disables input pad leaving output pad enabled + * Useful for reducing power consumption of output only pins. + */ +#define MCHP_GPIO_CTRL_INPAD_DIS_POS 15u +#define MCHP_GPIO_CTRL_INPAD_DIS_MASK BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS) +#define MCHP_GPIO_CTRL_INPAD_DIS BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS) + +/* bit[16]: Alternate output pin value. Enabled when bit[10]==0(default) */ +#define MCHP_GPIO_CTRL_OUTVAL_POS 16u +#define MCHP_GPIO_CTRL_OUTV_HI BIT(MCHP_GPIO_CTRL_OUTVAL_POS) + +/* bit[24] Input pad value. Always live unless input pad is powered down */ +#define MCHP_GPIO_CTRL_INPAD_VAL_POS 24u +#define MCHP_GPIO_CTRL_INPAD_VAL_HI BIT(MCHP_GPIO_CTRL_INPAD_VAL_POS) + +#define MCHP_GPIO_CTRL_DRIVE_OD_HI \ + (MCHP_GPIO_CTRL_BUFT_OPENDRAIN + MCHP_GPIO_CTRL_DIR_OUTPUT + \ + MCHP_GPIO_CTRL_MUX_GPIO + MCHP_GPIO_CTRL_OUTV_HI) + +/* + * Each GPIO pin implements a second control register. + * GPIO Control 2 register selects pin drive strength and slew rate. + * bit[0] = slew rate: 0=slow, 1=fast + * bits[5:4] = drive strength + * 00b = 2mA (default) + * 01b = 4mA + * 10b = 8mA + * 11b = 12mA + */ +#define MCHP_GPIO_CTRL2_OFFSET 0x0500ul +#define MCHP_GPIO_CTRL2_SLEW_POS 0ul +#define MCHP_GPIO_CTRL2_SLEW_MASK 0x01ul +#define MCHP_GPIO_CTRL2_SLEW_SLOW 0ul +#define MCHP_GPIO_CTRL2_SLEW_FAST BIT(MCHP_GPIO_CTRL2_SLEW_POS) +#define MCHP_GPIO_CTRL2_DRV_STR_POS 4ul +#define MCHP_GPIO_CTRL2_DRV_STR_MASK 0x30ul +#define MCHP_GPIO_CTRL2_DRV_STR_2MA 0x00ul +#define MCHP_GPIO_CTRL2_DRV_STR_4MA 0x10ul +#define MCHP_GPIO_CTRL2_DRV_STR_8MA 0x20ul +#define MCHP_GPIO_CTRL2_DRV_STR_12MA 0x30ul + +/* Interfaces to any C modules */ +#ifdef __cplusplus +extern "C" { +#endif + +/* GPIO pin numbers SZ (144-pin) package */ +enum mec_gpio_idx { + MCHP_GPIO_0000_ID = 0, + MCHP_GPIO_0002_ID = 2, + MCHP_GPIO_0003_ID, + MCHP_GPIO_0004_ID, + MCHP_GPIO_0007_ID = 7, + MCHP_GPIO_0010_ID, + MCHP_GPIO_0011_ID, + MCHP_GPIO_0012_ID, + MCHP_GPIO_0013_ID, + MCHP_GPIO_0014_ID, + MCHP_GPIO_0015_ID, + MCHP_GPIO_0016_ID, + MCHP_GPIO_0017_ID, + MCHP_GPIO_0020_ID, + MCHP_GPIO_0021_ID, + MCHP_GPIO_0022_ID, + MCHP_GPIO_0023_ID, + MCHP_GPIO_0024_ID, + MCHP_GPIO_0025_ID, + MCHP_GPIO_0026_ID, + MCHP_GPIO_0027_ID, + MCHP_GPIO_0030_ID, + MCHP_GPIO_0031_ID, + MCHP_GPIO_0032_ID, + MCHP_GPIO_0033_ID, + MCHP_GPIO_0034_ID, + MCHP_GPIO_0035_ID, + MCHP_GPIO_0036_ID, + MCHP_GPIO_0040_ID = 32, + MCHP_GPIO_0042_ID = 34, + MCHP_GPIO_0043_ID, + MCHP_GPIO_0044_ID, + MCHP_GPIO_0045_ID, + MCHP_GPIO_0046_ID, + MCHP_GPIO_0047_ID, + MCHP_GPIO_0050_ID, + MCHP_GPIO_0051_ID, + MCHP_GPIO_0052_ID, + MCHP_GPIO_0053_ID, + MCHP_GPIO_0054_ID, + MCHP_GPIO_0055_ID, + MCHP_GPIO_0056_ID, + MCHP_GPIO_0057_ID, + MCHP_GPIO_0060_ID, + MCHP_GPIO_0061_ID, + MCHP_GPIO_0062_ID, + MCHP_GPIO_0063_ID, + MCHP_GPIO_0064_ID, + MCHP_GPIO_0065_ID, + MCHP_GPIO_0066_ID, + MCHP_GPIO_0067_ID, + MCHP_GPIO_0070_ID, + MCHP_GPIO_0071_ID, + MCHP_GPIO_0072_ID, + MCHP_GPIO_0073_ID, + MCHP_GPIO_0100_ID = 64, + MCHP_GPIO_0101_ID, + MCHP_GPIO_0102_ID, + MCHP_GPIO_0104_ID = 68, + MCHP_GPIO_0105_ID, + MCHP_GPIO_0106_ID, + MCHP_GPIO_0107_ID, + MCHP_GPIO_0112_ID = 74, + MCHP_GPIO_0113_ID, + MCHP_GPIO_0114_ID, + MCHP_GPIO_0115_ID, + MCHP_GPIO_0120_ID = 80, + MCHP_GPIO_0121_ID, + MCHP_GPIO_0122_ID, + MCHP_GPIO_0123_ID, + MCHP_GPIO_0124_ID, + MCHP_GPIO_0125_ID, + MCHP_GPIO_0126_ID, + MCHP_GPIO_0127_ID, + MCHP_GPIO_0130_ID, + MCHP_GPIO_0131_ID, + MCHP_GPIO_0132_ID, + MCHP_GPIO_0140_ID = 96, + MCHP_GPIO_0141_ID, + MCHP_GPIO_0142_ID, + MCHP_GPIO_0143_ID, + MCHP_GPIO_0144_ID, + MCHP_GPIO_0145_ID, + MCHP_GPIO_0146_ID, + MCHP_GPIO_0147_ID, + MCHP_GPIO_0150_ID, + MCHP_GPIO_0151_ID, + MCHP_GPIO_0152_ID, + MCHP_GPIO_0153_ID, + MCHP_GPIO_0154_ID, + MCHP_GPIO_0155_ID, + MCHP_GPIO_0156_ID, + MCHP_GPIO_0157_ID, + MCHP_GPIO_0161_ID = 113, + MCHP_GPIO_0162_ID, + MCHP_GPIO_0165_ID = 117, + MCHP_GPIO_0170_ID = 120, + MCHP_GPIO_0171_ID, + MCHP_GPIO_0175_ID = 125, + MCHP_GPIO_0200_ID = 128, + MCHP_GPIO_0201_ID, + MCHP_GPIO_0202_ID, + MCHP_GPIO_0203_ID, + MCHP_GPIO_0204_ID, + MCHP_GPIO_0205_ID, + MCHP_GPIO_0206_ID, + MCHP_GPIO_0207_ID, + MCHP_GPIO_0221_ID = 145, + MCHP_GPIO_0222_ID, + MCHP_GPIO_0223_ID, + MCHP_GPIO_0224_ID, + MCHP_GPIO_0226_ID = 150, + MCHP_GPIO_0227_ID, + MCHP_GPIO_0240_ID = 160, + MCHP_GPIO_0241_ID, + MCHP_GPIO_0242_ID, + MCHP_GPIO_0243_ID, + MCHP_GPIO_0244_ID, + MCHP_GPIO_0245_ID, + MCHP_GPIO_0246_ID, + MCHP_GPIO_0254_ID = 172, + MCHP_GPIO_0255_ID, + MCHP_GPIO_MAX_ID +}; + +#define MCHP_GPIO_PIN2PORT(pin_id) ((uint32_t)(pin_id) >> 5) + +#define MAX_MCHP_GPIO_BANK 6ul +#define MCHP_GPIO_LOCK5_IDX 0ul +#define MCHP_GPIO_LOCK4_IDX 1ul +#define MCHP_GPIO_LOCK3_IDX 2ul +#define MCHP_GPIO_LOCK2_IDX 3ul +#define MCHP_GPIO_LOCK1_IDX 4ul +#define MCHP_GPIO_LOCK0_IDX 5ul +#define MCHP_GPIO_LOCK_MAX_IDX 6ul + +/* Helper functions */ +enum mchp_gpio_pud { + MCHP_GPIO_NO_PUD = 0ul, + MCHP_GPIO_PU_EN = 1ul, + MCHP_GPIO_PD_EN = 2ul, + MCHP_GPIO_RPT_EN = 3ul, +}; + +enum mchp_gpio_pwrgate { + MCHP_GPIO_PWRGT_VTR = 0ul, + MCHP_GPIO_PWRGT_VCC = 1ul, + MCHP_GPIO_PWRGD_OFF = 2ul, +}; + +enum mchp_gpio_idet { + MCHP_GPIO_IDET_LO_LVL = 0x00ul, + MCHP_GPIO_IDET_HI_LVL = 0x01ul, + MCHP_GPIO_IDET_DIS = 0x04ul, + MCHP_GPIO_IDET_RISING_EDGE = 0x0Dul, + MCHP_GPIO_IDET_FALLING_EDGE = 0x0Eul, + MCHP_GPIO_IDET_BOTH_EDGES = 0x0Ful +}; + +enum mchp_gpio_outbuf { + MCHP_GPIO_PUSH_PULL = 0ul, + MCHP_GPIO_OPEN_DRAIN = 1ul, +}; + +enum mchp_gpio_dir { + MCHP_GPIO_DIR_IN = 0ul, + MCHP_GPIO_DIR_OUT = 1ul, +}; + +enum mchp_gpio_parout_en { + MCHP_GPIO_PAROUT_DIS = 0ul, + MCHP_GPIO_PAROUT_EN = 1ul, +}; + +enum mchp_gpio_pol { + MCHP_GPIO_POL_NORM = 0ul, + MCHP_GPIO_POL_INV = 1ul, +}; + +enum mchp_gpio_mux { + MCHP_GPIO_MUX_GPIO = 0u, + MCHP_GPIO_MUX_FUNC1, + MCHP_GPIO_MUX_FUNC2, + MCHP_GPIO_MUX_FUNC3, + MCHP_GPIO_MUX_FUNC4, + MCHP_GPIO_MUX_FUNC5, + MCHP_GPIO_MUX_FUNC6, + MCHP_GPIO_MUX_FUNC7, + MCHP_GPIO_MUX_MAX +}; + +enum mchp_gpio_inpad_ctrl { + MCHP_GPIO_INPAD_CTRL_EN = 0ul, + MCHP_GPIO_INPAD_CTRL_DIS = 1ul, +}; + +enum mchp_gpio_alt_out { + MCHP_GPIO_ALT_OUT_LO = 0ul, + MCHP_GPIO_ALT_OUT_HI = 1ul, +}; + +enum mchp_gpio_slew { + MCHP_GPIO_SLEW_SLOW = 0ul, + MCHP_GPIO_SLEW_FAST = 1ul, +}; + +enum mchp_gpio_drv_str { + MCHP_GPIO_DRV_STR_2MA = 0ul, + MCHP_GPIO_DRV_STR_4MA = 1ul, + MCHP_GPIO_DRV_STR_8MA = 2ul, + MCHP_GPIO_DRV_STR_12MA = 3ul, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _COMPONENT_GPIO_H */ +/* end gpio.h */ +/** @} + */ diff --git a/mec/mec172x/component/gpspi.h b/mec/mec172x/component/gpspi.h new file mode 100644 index 0000000..be169ab --- /dev/null +++ b/mec/mec172x/component/gpspi.h @@ -0,0 +1,194 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file gpspi.h + * MEC172x General purpose SPI definitions + */ +/** @defgroup MEC172x Peripherals GPSPI + */ + +#ifndef COMPONENT_GPSPI_H +#define COMPONENT_GPSPI_H + +#include +#include + +#include "regaccess.h" + +/* General Purpose SPI (GPSPI) */ +#define MCHP_GPSPI_BASE 0x40009400ul + +/* Offset between instances of the Basic Timer blocks */ +#define MCHP_GPSPI_INSTANCE_OFS 0x80U + +/* 0 <= n < MCHP_GPSPI_MAX_INSTANCE */ +#define MCHP_GPSPI_ADDR(n) \ + (MCHP_GPSPI_BASE + ((uint32_t)(n) * MCHP_GPSPI_INSTANCE_OFS)) + +#define MCHP_GPSPI_0_ADDR 0x40009400ul +#define MCHP_GPSPI_1_ADDR 0x40009480ul + +/* GPSPI interrupt routing */ +#define MCHP_GPSPI_0_GIRQ 18u +#define MCHP_GPSPI_1_GIRQ 18u + +/* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ +#define MCHP_GPSPI_0_GIRQ_TXBE_POS 2u +#define MCHP_GPSPI_0_GIRQ_RXBF_POS 3u +#define MCHP_GPSPI_1_GIRQ_TXBE_POS 4u +#define MCHP_GPSPI_1_GIRQ_RXBF_POS 5u + +/* GIRQ Source, Enable-Set/Clear, Result register values */ +#define MCHP_GPSPI_0_GIRQ_TXBE_VAL 0x04U +#define MCHP_GPSPI_0_GIRQ_RXBF_VAL 0x08U +#define MCHP_GPSPI_0_GIRQ_ALL_VAL 0x0Cu + +#define MCHP_GPSPI_1_GIRQ_TXBE_VAL 0x10U +#define MCHP_GPSPI_1_GIRQ_RXBF_VAL 0x20U +#define MCHP_GPSPI_1_GIRQ_ALL_VAL 0x30U + +/* GPSPI GIRQ aggregated NVIC input */ +#define MCHP_GPSPI_0_NVIC_AGGR 10u +#define MCHP_GPSPI_1_NVIC_AGGR 10u + +/* GPSPI direct NVIC inputs */ +#define MCHP_GPSPI_0_NVIC_DIRECT_TXBE 92u +#define MCHP_GPSPI_0_NVIC_DIRECT_RXBF 93u +#define MCHP_GPSPI_1_NVIC_DIRECT_TXBE 94u +#define MCHP_GPSPI_1_NVIC_DIRECT_RXBF 95u + +/* Block Enable register */ +#define MCHP_GPSPI_BLK_EN_REG_OFS 0x00ul +#define MCHP_GPSPI_BLK_EN_REG_MASK 0x01ul +#define MCHP_GPSPI_BLK_EN_ON 0x01ul + +/* Control register */ +#define MCHP_GPSPI_CTRL_REG_OFS 0x04ul +#define MCHP_GPSPI_CTRL_REG_MASK 0x7Ful +#define MCHP_GPSPI_CTRL_MSBF 0x00u +#define MCHP_GPSPI_CTRL_LSBF 0x01u +#define MCHP_GPSPI_CTRL_BIOEN_OUT 0x00u +#define MCHP_GPSPI_CTRL_BIOEN_IN 0x02u +#define MCHP_GPSPI_CTRL_SPDIN_MASK 0x0Cu +#define MCHP_GPSPI_CTRL_SPDIN_FD 0x00u +#define MCHP_GPSPI_CTRL_SPDIN_HD 0x04u +#define MCHP_GPSPI_CTRL_SPDIN_DUAL 0x08u +#define MCHP_GPSPI_CTRL_SRST 0x10u +#define MCHP_GPSPI_CTRL_AUTO_READ 0x20u +#define MCHP_GPSPI_CTRL_CS_ASSERT 0x40u + +/* Status register (read-only) */ +#define MCHP_GPSPI_STS_REG_OFS 0x08ul +#define MCHP_GPSPI_STS_REG_MASK 0x07u +#define MCHP_GPSPI_STS_ALL 0x07u +#define MCHP_GPSPI_STS_TXBE 0x01u +#define MCHP_GPSPI_STS_RXBF 0x02u +/* + * Active indicates GPSPI is in process of moving data to/from its + * internal shift register. It will also be set for the condition + * of RX overrun where CPU has not read the byte in RX Data before + * another byte is ready to be moved from internal shift register + * into RX data. + */ +#define MCHP_GPSPI_STS_ACTIVE 0x04u + +/* + * GPSPI hardware shared one internal shift register between + * TX and RX paths. Before writing TX Data software must insure + * RX Data is empty, all received data has been cleared. Actually + * software should not write TX Data unitl both RXBF and Active + * status are cleared. + */ + +/* + * TX Data register + * Write clears TXBE status. + * Do not write if TXBE == 0. + */ +#define MCHP_GPSPI_TXD_REG_OFS 0x0Cul +#define MCHP_GPSPI_TXD_REG_MASK 0xFFu + +/* + * RX Data register + * Read clears RXBF status. + */ +#define MCHP_GPSPI_RXD_REG_OFS 0x10ul +#define MCHP_GPSPI_RXD_REG_MASK 0xFFu + +/* SPI Clock Control register */ +#define MCHP_GPSPI_CC_REG_OFS 0x14ul +#define MCHP_GPSPI_CC_REG_MASK 0x17u +/* + * Select when GPSPI transmit data is valid on SPDOUT pin. + * 0 = TX data transmit begines before first clock edge. + * Receiver device should sample on first and following odd numbered + * clock edges. + * 1 = TX data transmit begins on first clock edge. + * Receiver device should sample on second and following even numbered + * clock edges. + */ +#define MCHP_GPSPI_CC_TCLKPH_ODD 0x00u +#define MCHP_GPSPI_CC_TCLKPH_EVEN 0x01u +/* + * Select when GPSPI samples received data on SPDIN pin(s). + * 0 = Valid data expected on first SPI clock edge. Data sampled on the + * the first and following odd clock edges. + * 1 = Valid data expected after first clock edge. Data sampled on the + * second and following even clock edges. + */ +#define MCHP_GPSPI_CC_RCLKPH_ODD 0x00u +#define MCHP_GPSPI_CC_RCLKPH_EVEN 0x02u + +/* SPI clock pin idle state */ +#define MCHP_GPSPI_CC_CLK_IDLE_LO 0x00u +#define MCHP_GPSPI_CC_CLK_IDLE_HI 0x04u + +/* GPSPI internal clock source */ +#define MCHP_GPSPI_CC_CLK_SRC_48M 0x00u +#define MCHP_GPSPI_CC_CLK_SRC_2M 0x10u + +/* SPI Clock Generator register */ +#define MCHP_GPSPI_CG_REG_OFS 0x18ul +#define MCHP_GPSPI_CG_REG_MASK 0x3Fu +#define MCHP_GPSPI_CG_PRLD_MASK 0x3Fu + +/* + * SPI Clock frequency + * Clock source of 48Mhz or 2MHz is selected in the Clock Control register. + * Preload value is set in bits[5:0] of Clock Generator register. + * SPI_CLK_Freq = (CLOCK_SRC_FREQ / 2 * PRELOAD) + * Examples: + * 24MHz SPI clock: Clock Source bit=0(48MHz) and PRELOAD=1 + * 12MHz SPI clock: Clock Source bit=0(48MHz) and PRELOAD=2 + * 1MHz SPI clock: two choices. + Clock Source bit=0(48MHz) and PRELOAD=24 + Clock Source bit=1(2MHz) and PRELOAD=1 + */ + +#endif /* #ifndef COMPONENT_GPSPI_H */ +/* end gpspi.h */ +/** @} + */ diff --git a/mec/mec172x/component/i2c_smb.h b/mec/mec172x/component/i2c_smb.h new file mode 100644 index 0000000..60f92cc --- /dev/null +++ b/mec/mec172x/component/i2c_smb.h @@ -0,0 +1,433 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file i2c_smb.h + * MEC1721 I2C-SMB register definitions + */ +/** @defgroup MEC172x Peripherals I2C-SMB + */ + +#ifndef _COMPONENT_I2C_SMB_H +#define _COMPONENT_I2C_SMB_H + +#include +#include + +#include +#include + +#define MCHP_I2C_BAUD_CLK_HZ 16000000UL + +#define MCHP_I2C_SMB_INST_SPACING 0x400ul +#define MCHP_I2C_SMB_INST_SPACING_P2 10u + +#define MCHP_I2C_SMB0_BASE_ADDR 0x40004000ul +#define MCHP_I2C_SMB1_BASE_ADDR 0x40004400ul +#define MCHP_I2C_SMB2_BASE_ADDR 0x40004800ul +#define MCHP_I2C_SMB3_BASE_ADDR 0x40004C00ul +#define MCHP_I2C_SMB4_BASE_ADDR 0x40005000ul + +/* 0 <= n < MCHP_I2C_SMB_MAX_INSTANCES */ +#define MCHP_I2C_SMB_BASE_ADDR(n) \ + ((MCHP_I2C_SMB0_BASE_ADDR) + \ + ((uint32_t)(n) * (MCHP_I2C_SMB_INST_SPACING))) + +/* + * Offset 0x00 + * Control and Status register + * Write to Control + * Read from Status + * Size 8-bit + */ +#define MCHP_I2C_SMB_CTRL_OFS 0x00ul +#define MCHP_I2C_SMB_CTRL_MASK 0xCFul +#define MCHP_I2C_SMB_CTRL_ACK BIT(0) +#define MCHP_I2C_SMB_CTRL_STO BIT(1) +#define MCHP_I2C_SMB_CTRL_STA BIT(2) +#define MCHP_I2C_SMB_CTRL_ENI BIT(3) +/* bits [5:4] reserved */ +#define MCHP_I2C_SMB_CTRL_ESO BIT(6) +#define MCHP_I2C_SMB_CTRL_PIN BIT(7) +/* Status Read-only */ +#define MCHP_I2C_SMB_STS_OFS 0x00ul +#define MCHP_I2C_SMB_STS_NBB BIT(0) +#define MCHP_I2C_SMB_STS_LAB BIT(1) +#define MCHP_I2C_SMB_STS_AAS BIT(2) +#define MCHP_I2C_SMB_STS_LRB_AD0 BIT(3) +#define MCHP_I2C_SMB_STS_BER BIT(4) +#define MCHP_I2C_SMB_STS_EXT_STOP BIT(5) +#define MCHP_I2C_SMB_STS_SAD BIT(6) +#define MCHP_I2C_SMB_STS_PIN BIT(7) + +/* + * Offset 0x04 + * Own Address b[7:0] = Slave address 1 + * b[14:8] = Slave address 2 + */ +#define MCHP_I2C_SMB_OWN_ADDR_OFS 0x04ul +#define MCHP_I2C_SMB_OWN_ADDR2_OFS 0x05ul +#define MCHP_I2C_SMB_OWN_ADDR_MASK 0x7F7Ful + +/* + * Offset 0x08 + * Data register, 8-bit + * Data to be shifted out or shifted in. + */ +#define MCHP_I2C_SMB_DATA_OFS 0x08ul + +/* Offset 0x0C Leader Command register + */ +#define MCHP_I2C_SMB_MSTR_CMD_OFS 0x0Cul +#define MCHP_I2C_SMB_MSTR_CMD_RD_CNT_OFS 0x0Ful /* byte 3 */ +#define MCHP_I2C_SMB_MSTR_CMD_WR_CNT_OFS 0x0Eul /* byte 2 */ +#define MCHP_I2C_SMB_MSTR_CMD_OP_OFS 0x0Dul /* byte 1 */ +#define MCHP_I2C_SMB_MSTR_CMD_M_OFS 0x0Cul /* byte 0 */ +#define MCHP_I2C_SMB_MSTR_CMD_MASK 0xFFFF3FF3ul +/* 32-bit definitions */ +#define MCHP_I2C_SMB_MSTR_CMD_MRUN BIT(0) +#define MCHP_I2C_SMB_MSTR_CMD_MPROCEED BIT(1) +#define MCHP_I2C_SMB_MSTR_CMD_START0 BIT(8) +#define MCHP_I2C_SMB_MSTR_CMD_STARTN BIT(9) +#define MCHP_I2C_SMB_MSTR_CMD_STOP BIT(10) +#define MCHP_I2C_SMB_MSTR_CMD_PEC_TERM BIT(11) +#define MCHP_I2C_SMB_MSTR_CMD_READM BIT(12) +#define MCHP_I2C_SMB_MSTR_CMD_READ_PEC BIT(13) +#define MCHP_I2C_SMB_MSTR_CMD_RD_CNT_POS 24u +#define MCHP_I2C_SMB_MSTR_CMD_WR_CNT_POS 16u +/* byte 0 definitions */ +#define MCHP_I2C_SMB_MSTR_CMD_B0_MRUN BIT(0) +#define MCHP_I2C_SMB_MSTR_CMD_B0_MPROCEED BIT(1) +/* byte 1 definitions */ +#define MCHP_I2C_SMB_MSTR_CMD_B1_START0 BIT((8 - 8)) +#define MCHP_I2C_SMB_MSTR_CMD_B1_STARTN BIT((9 - 8)) +#define MCHP_I2C_SMB_MSTR_CMD_B1_STOP BIT((10 - 8)) +#define MCHP_I2C_SMB_MSTR_CMD_B1_PEC_TERM BIT((11 - 8)) +#define MCHP_I2C_SMB_MSTR_CMD_B1_READM BIT((12 - 8)) +#define MCHP_I2C_SMB_MSTR_CMD_B1_READ_PEC BIT((13 - 8)) + +/* Offset 0x10 Follower Command register */ +#define MCHP_I2C_SMB_SLV_CMD_OFS 0x10ul +#define MCHP_I2C_SMB_SLV_CMD_MASK 0x00FFFF07ul +#define MCHP_I2C_SMB_SLV_CMD_SRUN BIT(0) +#define MCHP_I2C_SMB_SLV_CMD_SPROCEED BIT(1) +#define MCHP_I2C_SMB_SLV_CMD_SEND_PEC BIT(2) +#define MCHP_I2C_SMB_SLV_WR_CNT_POS 8u +#define MCHP_I2C_SMB_SLV_RD_CNT_POS 16u + +/* Offset 0x14 PEC CRC register, 8-bit read-write */ +#define MCHP_I2C_SMB_PEC_CRC_OFS 0x14ul + +/* Offset 0x18 Repeated Start Hold Time register, 8-bit read-write */ +#define MCHP_I2C_SMB_RSHT_OFS 0x18ul + +/* Offset 0x20 Completion register, 32-bit */ +#define MCHP_I2C_SMB_CMPL_OFS 0x20ul +#define MCHP_I2C_SMB_CMPL_MASK 0xE33B7F7Cul +#define MCHP_I2C_SMB_CMPL_RW1C_MASK 0xE1397F00ul +#define MCHP_I2C_SMB_CMPL_DTEN BIT(2) +#define MCHP_I2C_SMB_CMPL_MCEN BIT(3) +#define MCHP_I2C_SMB_CMPL_SCEN BIT(4) +#define MCHP_I2C_SMB_CMPL_BIDEN BIT(5) +#define MCHP_I2C_SMB_CMPL_TIMERR BIT(6) +#define MCHP_I2C_SMB_CMPL_DTO_RWC BIT(8) +#define MCHP_I2C_SMB_CMPL_MCTO_RWC BIT(9) +#define MCHP_I2C_SMB_CMPL_SCTO_RWC BIT(10) +#define MCHP_I2C_SMB_CMPL_CHDL_RWC BIT(11) +#define MCHP_I2C_SMB_CMPL_CHDH_RWC BIT(12) +#define MCHP_I2C_SMB_CMPL_BER_RWC BIT(13) +#define MCHP_I2C_SMB_CMPL_LAB_RWC BIT(14) +#define MCHP_I2C_SMB_CMPL_SNAKR_RWC BIT(16) +#define MCHP_I2C_SMB_CMPL_STR_RO BIT(17) +#define MCHP_I2C_SMB_CMPL_SPROT_RWC BIT(19) +#define MCHP_I2C_SMB_CMPL_RPT_RD_RWC BIT(20) +#define MCHP_I2C_SMB_CMPL_RPT_WR_RWC BIT(21) +#define MCHP_I2C_SMB_CMPL_MNAKX_RWC BIT(24) +#define MCHP_I2C_SMB_CMPL_MTR_RO BIT(25) +#define MCHP_I2C_SMB_CMPL_IDLE_RWC BIT(29) +#define MCHP_I2C_SMB_CMPL_MDONE_RWC BIT(30) +#define MCHP_I2C_SMB_CMPL_SDONE_RWC BIT(31) + +/* Offset 0x24 Idle Scaling register */ +#define MCHP_I2C_SMB_IDLSC_OFS 0x24ul +#define MCHP_I2C_SMB_IDLSC_DLY_OFS 0x24ul +#define MCHP_I2C_SMB_IDLSC_BUS_OFS 0x26ul +#define MCHP_I2C_SMB_IDLSC_MASK 0x0FFF0FFFul +#define MCHP_I2C_SMB_IDLSC_BUS_MIN_POS 0u +#define MCHP_I2C_SMB_IDLSC_DLY_POS 16u + +/* + * Offset 0x28 Configure register */ +#define MCHP_I2C_SMB_CFG_OFS 0x28ul +#define MCHP_I2C_SMB_CFG_MASK 0xF00F5FBFul +#define MCHP_I2C_SMB_CFG_PORT_SEL_POS 0 +#define MCHP_I2C_SMB_CFG_PORT_SEL_MASK 0x0Ful +#define MCHP_I2C_SMB_CFG_TCEN BIT(4) +#define MCHP_I2C_SMB_CFG_SLOW_CLK BIT(5) +#define MCHP_I2C_SMB_CFG_PCEN BIT(7) +#define MCHP_I2C_SMB_CFG_FEN BIT(8) +#define MCHP_I2C_SMB_CFG_RESET BIT(9) +#define MCHP_I2C_SMB_CFG_ENAB BIT(10) +#define MCHP_I2C_SMB_CFG_DSA BIT(11) +#define MCHP_I2C_SMB_CFG_FAIR BIT(12) +#define MCHP_I2C_SMB_CFG_GC_EN BIT(14) +#define MCHP_I2C_SMB_CFG_FLUSH_SXBUF_WO BIT(16) +#define MCHP_I2C_SMB_CFG_FLUSH_SRBUF_WO BIT(17) +#define MCHP_I2C_SMB_CFG_FLUSH_MXBUF_WO BIT(18) +#define MCHP_I2C_SMB_CFG_FLUSH_MRBUF_WO BIT(19) +#define MCHP_I2C_SMB_CFG_EN_AAS BIT(28) +#define MCHP_I2C_SMB_CFG_ENIDI BIT(29) +#define MCHP_I2C_SMB_CFG_ENMI BIT(30) +#define MCHP_I2C_SMB_CFG_ENSI BIT(31) + +/* Offset 0x2C Bus Clock register */ +#define MCHP_I2C_SMB_BUS_CLK_OFS 0x2Cul +#define MCHP_I2C_SMB_BUS_CLK_MASK 0x0000FFFFul +#define MCHP_I2C_SMB_BUS_CLK_LO_POS 0u +#define MCHP_I2C_SMB_BUS_CLK_HI_POS 8u + +/* Offset 0x30 Block ID register, 8-bit read-only */ +#define MCHP_I2C_SMB_BLOCK_ID_OFS 0x30ul +#define MCHP_I2C_SMB_BLOCK_ID_MASK 0xFFul + +/* Offset 0x34 Block Revision register, 8-bit read-only */ +#define MCHP_I2C_SMB_BLOCK_REV_OFS 0x34ul +#define MCHP_I2C_SMB_BLOCK_REV_MASK 0xFFul + +/* Offset 0x38 Bit-Bang Control register, 8-bit read-write */ +#define MCHP_I2C_SMB_BB_OFS 0x38ul +#define MCHP_I2C_SMB_BB_MASK 0x7Ful +#define MCHP_I2C_SMB_BB_EN BIT(0) +#define MCHP_I2C_SMB_BB_SCL_DIR_IN 0U +#define MCHP_I2C_SMB_BB_SCL_DIR_OUT BIT(1) +#define MCHP_I2C_SMB_BB_SDA_DIR_IN 0U +#define MCHP_I2C_SMB_BB_SDA_DIR_OUT BIT(2) +#define MCHP_I2C_SMB_BB_CL_TRI BIT(3) +#define MCHP_I2C_SMB_BB_DAT_TRI BIT(4) +#define MCHP_I2C_SMB_BB_IN_POS 5u +#define MCHP_I2C_SMB_BB_IN_MASK0 0x03u +#define MCHP_I2C_SMB_BB_IN_MASK SHLU32(0x03u, 5) +#define MCHP_I2C_SMB_BB_CLKI_RO BIT(5) +#define MCHP_I2C_SMB_BB_DATI_RO BIT(6) + +/* Offset 0x40 Data Timing register */ +#define MCHP_I2C_SMB_DATA_TM_OFS 0x40ul +#define MCHP_I2C_SMB_DATA_TM_MASK 0xFFFFFFFFul +#define MCHP_I2C_SMB_DATA_TM_DATA_HOLD_POS 0u +#define MCHP_I2C_SMB_DATA_TM_DATA_HOLD_MASK 0xFFul +#define MCHP_I2C_SMB_DATA_TM_DATA_HOLD_MASK0 0xFFul +#define MCHP_I2C_SMB_DATA_TM_RESTART_POS 8u +#define MCHP_I2C_SMB_DATA_TM_RESTART_MASK 0xFF00ul +#define MCHP_I2C_SMB_DATA_TM_RESTART_MASK0 0xFFul +#define MCHP_I2C_SMB_DATA_TM_STOP_POS 16u +#define MCHP_I2C_SMB_DATA_TM_STOP_MASK 0xFF0000ul +#define MCHP_I2C_SMB_DATA_TM_STOP_MASK0 0xFFul +#define MCHP_I2C_SMB_DATA_TM_FSTART_POS 24u +#define MCHP_I2C_SMB_DATA_TM_FSTART_MASK 0xFF000000ul +#define MCHP_I2C_SMB_DATA_TM_FSTART_MASK0 0xFFul + +/* Offset 0x44 Time-out Scaling register */ +#define MCHP_I2C_SMB_TMTSC_OFS 0x44ul +#define MCHP_I2C_SMB_TMTSC_MASK 0xFFFFFFFFul +#define MCHP_I2C_SMB_TMTSC_CLK_HI_POS 0u +#define MCHP_I2C_SMB_TMTSC_CLK_HI_MASK 0xFFul +#define MCHP_I2C_SMB_TMTSC_CLK_HI_MASK0 0xFFul +#define MCHP_I2C_SMB_TMTSC_SLV_POS 8u +#define MCHP_I2C_SMB_TMTSC_SLV_MASK 0xFF00ul +#define MCHP_I2C_SMB_TMTSC_SLV_MASK0 0xFFul +#define MCHP_I2C_SMB_TMTSC_MSTR_POS 16u +#define MCHP_I2C_SMB_TMTSC_MSTR_MASK 0xFF0000ul +#define MCHP_I2C_SMB_TMTSC_MSTR_MASK0 0xFFul +#define MCHP_I2C_SMB_TMTSC_BUS_POS 24u +#define MCHP_I2C_SMB_TMTSC_BUS_MASK 0xFF000000ul +#define MCHP_I2C_SMB_TMTSC_BUS_MASK0 0xFFul + +/* Offset 0x48 Follower Transmit Buffer register 8-bit read-write */ +#define MCHP_I2C_SMB_SLV_TX_BUF_OFS 0x48ul + +/* Offset 0x4C Follower Receive Buffer register 8-bit read-write */ +#define MCHP_I2C_SMB_SLV_RX_BUF_OFS 0x4Cul + +/* Offset 0x50 Leader Transmit Buffer register 8-bit read-write */ +#define MCHP_I2C_SMB_MTR_TX_BUF_OFS 0x50ul + +/* Offset 0x54 Leader Receive Buffer register 8-bit read-write */ +#define MCHP_I2C_SMB_MTR_RX_BUF_OFS 0x54ul + +/* Offset 0x58 I2C FSM read-only */ +#define MCHP_I2C_SMB_I2C_FSM_OFS 0x58ul + +/* Offset 0x5C SMB Netork layer FSM read-only */ +#define MCHP_I2C_SMB_FSM_OFS 0x5Cul + +/* Offset 0x60 Wake Status register */ +#define MCHP_I2C_SMB_WAKE_STS_OFS 0x60ul +#define MCHP_I2C_SMB_WAKE_STS_START_RWC BIT(0) + +/* Offset 0x64 Wake Enable register */ +#define MCHP_I2C_SMB_WAKE_EN_OFS 0x64ul +#define MCHP_I2C_SMB_WAKE_EN BIT(0) + +/* Offset 0x68 */ +#define MCHP_I2C_SMB_WAKE_SYNC_OFS 0x68ul +#define MCHP_I2C_SMB_WAKE_FAST_RESYNC_EN BIT(0) + +/* I2C GIRQ and NVIC mapping */ +#define MCHP_I2C_SMB_GIRQ 13u +#define MCHP_I2C_SMB_GIRQ_IDX (13u - 8u) +#define MCHP_I2C_SMB_NVIC_GIRQ 5u +#define MCHP_I2C_SMB0_NVIC_DIRECT 20u +#define MCHP_I2C_SMB1_NVIC_DIRECT 21u +#define MCHP_I2C_SMB2_NVIC_DIRECT 22u +#define MCHP_I2C_SMB3_NVIC_DIRECT 23u +#define MCHP_I2C_SMB4_NVIC_DIRECT 158u + +#define MCHP_I2C_SMB_GIRQ_SRC_ADDR 0x4000E064ul +#define MCHP_I2C_SMB_GIRQ_SET_EN_ADDR 0x4000E068ul +#define MCHP_I2C_SMB_GIRQ_RESULT_ADDR 0x4000E06Cul +#define MCHP_I2C_SMB_GIRQ_CLR_EN_ADDR 0x4000E070ul + +#define MCHP_I2C_SMB0_GIRQ_POS 0u +#define MCHP_I2C_SMB1_GIRQ_POS 1u +#define MCHP_I2C_SMB2_GIRQ_POS 2u +#define MCHP_I2C_SMB3_GIRQ_POS 3u +#define MCHP_I2C_SMB4_GIRQ_POS 4u + +#define MCHP_I2C_SMB0_GIRQ_VAL BIT(0) +#define MCHP_I2C_SMB1_GIRQ_VAL BIT(1) +#define MCHP_I2C_SMB2_GIRQ_VAL BIT(2) +#define MCHP_I2C_SMB3_GIRQ_VAL BIT(3) +#define MCHP_I2C_SMB4_GIRQ_VAL BIT(4) + +/* Register access by controller base address */ + +/* I2C Control register, write-only */ +#define MCHP_I2C_SMB_CTRL_WO(ba) REG8(ba) +/* I2C Status register, read-only */ +#define MCHP_I2C_SMB_STS_RO(ba) REG8(ba) + +#define MCHP_I2C_SMB_CTRL(ba) REG8_OFS(ba, MCHP_I2C_SMB_CTRL_OFS) + +/* Own Address register (slave addresses) */ +#define MCHP_I2C_SMB_OWN_ADDR(ba) \ + REG16_OFS(ba, MCHP_I2C_SMB_OWN_ADDR_OFS) +/* access bits[7:0] OWN_ADDRESS_1 */ +#define MCHP_I2C_SMB_OWN_ADDR1(ba) \ + REG8_OFS(ba, MCHP_I2C_SMB_OWN_ADDR_OFS) +/* access bits[15:8] OWN_ADDRESS_2 */ +#define MCHP_I2C_SMB_OWN_ADDR2(ba) \ + REG8_OFS(ba, (MCHP_I2C_SMB_OWN_ADDR_OFS + 1)) + +/* I2C Data register */ +#define MCHP_I2C_SMB_DATA(ba) \ + REG8_OFS(ba, MCHP_I2C_SMB_DATA_OFS) + +/* Network layer Master Command register */ +#define MCHP_I2C_SMB_MCMD(ba) REG32_OFS(ba, MCHP_I2C_SMB_MSTR_CMD_OFS) +#define MCHP_I2C_SMB_MCMD_MRP(ba) \ + REG8_OFS(ba, (MCHP_I2C_SMB_MSTR_CMD_OFS + 0ul)) +#define MCHP_I2C_SMB_MCMD_CTRL(ba) \ + REG8_OFS(ba, (MCHP_I2C_SMB_MSTR_CMD_OFS + 1ul)) +#define MCHP_I2C_SMB_MCMD_WCNT(ba) \ + REG8_OFS(ba, (MCHP_I2C_SMB_MSTR_CMD_OFS + 2ul)) +#define MCHP_I2C_SMB_MCMD_RCNT(ba) \ + REG8_OFS(ba, (MCHP_I2C_SMB_MSTR_CMD_OFS + 3ul)) + +/* Network layer Slave Command register */ +#define MCHP_I2C_SMB_SCMD(ba) REG32_OFS(ba, MCHP_I2C_SMB_SLV_CMD_OFS) +#define MCHP_I2C_SMB_SCMD_SRP(ba) \ + REG8_OFS(ba, (MCHP_I2C_SMB_SLV_CMD_OFS + 0ul)) +#define MCHP_I2C_SMB_SCMD_WCNT(ba) \ + REG8_OFS(ba, (MCHP_I2C_SMB_SLV_CMD_OFS + 1ul)) +#define MCHP_I2C_SMB_SCMD_RCNT(ba) \ + REG8_OFS(ba, (MCHP_I2C_SMB_SLV_CMD_OFS + 2ul)) + +/* PEC register */ +#define MCHP_I2C_SMB_PEC(ba) REG8_OFS(ba, MCHP_I2C_SMB_PEC_CRC_OFS) + +/* Repeated Start Hold Time register */ +#define MCHP_I2C_SMB_RSHT(ba) REG8_OFS(ba, MCHP_I2C_SMB_RSHT_OFS) + +/* Completion register */ +#define MCHP_I2C_SMB_CMPL(ba) REG32_OFS(ba, MCHP_I2C_SMB_CMPL_OFS) +/* access only bits[7:0] R/W timeout enables */ +#define MCHP_I2C_SMB_CMPL_B0(ba) REG8_OFS(ba, MCHP_I2C_SMB_CMPL_OFS) + +/* Idle Scaling register */ +#define MCHP_I2C_SMB_IDLSC(ba) REG32_OFS(ba, MCHP_I2C_SMB_IDLSC_OFS) + +/* Configuration register */ +#define MCHP_I2C_SMB_CFG(ba) REG32_OFS(ba, MCHP_I2C_SMB_CFG_OFS) +/* access each byte */ +#define MCHP_I2C_SMB_CFG_B0(ba) \ + REG8_OFS(ba, (MCHP_I2C_SMB_CFG_OFS + 0x00ul)) +#define MCHP_I2C_SMB_CFG_B1(ba) \ + REG8_OFS(ba, (MCHP_I2C_SMB_CFG_OFS + 0x01ul)) +#define MCHP_I2C_SMB_CFG_B2(ba) \ + REG8_OFS(ba, (MCHP_I2C_SMB_CFG_OFS + 0x02ul)) +#define MCHP_I2C_SMB_CFG_B3(ba) \ + REG8_OFS(ba, (MCHP_I2C_SMB_CFG_OFS + 0x03ul)) + +/* Bus Clock register */ +#define MCHP_I2C_SMB_BUS_CLK(ba) REG32_OFS(ba, MCHP_I2C_SMB_BUS_CLK_OFS) +#define MCHP_I2C_SMB_BUS_CLK_LO_PERIOD(ba) \ + REG8_OFS(ba, (MCHP_I2C_SMB_BUS_CLK_OFS + 0x00ul)) +#define MCHP_I2C_SMB_BUS_CLK_HI_PERIOD(ba) \ + REG8_OFS(ba, (MCHP_I2C_SMB_BUS_CLK_OFS + 0x01ul)) + +/* Bit-Bang Control register */ +#define MCHP_I2C_SMB_BB_CTRL(ba) REG8_OFS(ba, MCHP_I2C_SMB_BB_OFS) + +/* MCHP Reserved 0x3C register */ +#define MCHP_I2C_SMB_RSVD_3C(ba) REG8_OFS(ba, MCHP_I2C_SMB_RSVD_3C) + +/* Data Timing register */ +#define MCHP_I2C_SMB_DATA_TM(ba) REG32_OFS(ba, MCHP_I2C_SMB_DATA_TM_OFS) + +/* Timeout Scaling register */ +#define MCHP_I2C_SMB_TMTSC(ba) REG32_OFS(ba, MCHP_I2C_SMB_TMTSC_OFS) + +/* Network layer Slave Transmit Buffer register */ +#define MCHP_I2C_SMB_SLV_TXB(ba) REG8_OFS(ba, MCHP_I2C_SMB_SLV_TX_BUF_OFS) + +/* Network layer Slave Receive Buffer register */ +#define MCHP_I2C_SMB_SLV_RXB(ba) REG8_OFS(ba, MCHP_I2C_SMB_SLV_RX_BUF_OFS) + +/* Network layer Master Transmit Buffer register */ +#define MCHP_I2C_SMB_MTR_TXB(ba) REG8_OFS(ba, MCHP_I2C_SMB_MTR_TX_BUF_OFS) + +/* Network layer Master Receive Buffer register */ +#define MCHP_I2C_SMB_MTR_RXB(ba) REG8_OFS(ba, MCHP_I2C_SMB_MTR_RX_BUF_OFS) + +/* Wake Status register */ +#define MCHP_I2C_SMB_WAKE_STS(ba) REG8_OFS(ba, MCHP_I2C_SMB_WAKE_STS_OFS) + +/* Wake Enable register */ +#define MCHP_I2C_SMB_WAKE_ENABLE(ba) REG8_OFS(ba, MCHP_SMB_WAKE_EN_OFS) + +#endif /* #ifndef _COMPONENT_I2C_SMB_H */ +/* end i2c_smb.h */ +/** @} + */ diff --git a/mec/mec172x/component/kbc.h b/mec/mec172x/component/kbc.h new file mode 100644 index 0000000..272b4cf --- /dev/null +++ b/mec/mec172x/component/kbc.h @@ -0,0 +1,105 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file kbc.h + * MEC172x EM8042 Keyboard Controller Registers + */ +/** @defgroup MEC172x Peripherals KBC + */ + +#ifndef _COMPONENT_KBC_H +#define _COMPONENT_KBC_H + +#include +#include + +#include +#include + +/* ---- EM8042 Keyboard Controller (KBC) ---- */ +#define MCHP_KBC_BASE_ADDR 0x400F0400ul + +/* KBC interrupts */ +#define MCHP_KBC_GIRQ 15u +#define MCHP_KBC_GIRQ_NVIC 7u +#define MCHP_KBC_OBE_NVIC 58u +#define MCHP_KBC_IBF_NVIC 59u + +#define MCHP_KBC_OBE_GIRQ_POS 18u +#define MCHP_KBC_IBF_GIRQ_POS 19u + +#define MCHP_KBC_OBE_GIRQ BIT(MCHP_KBC_OBE_GIRQ_POS) +#define MCHP_KBC_IBF_GIRQ BIT(MCHP_KBC_IBF_GIRQ_POS) + +/* EC_KBC_STS and KBC_STS_RD bit definitions */ +#define MCHP_KBC_STS_OBF_POS 0u +#define MCHP_KBC_STS_OBF BIT(MCHP_KBC_STS_OBF_POS) +#define MCHP_KBC_STS_IBF_POS 1u +#define MCHP_KBC_STS_IBF BIT(MCHP_KBC_STS_IBF_POS) +#define MCHP_KBC_STS_UD0_POS 2u +#define MCHP_KBC_STS_UD0 BIT(MCHP_KBC_STS_UD0_POS) +#define MCHP_KBC_STS_CD_POS 3u +#define MCHP_KBC_STS_CD BIT(MCHP_KBC_STS_CD_POS) +#define MCHP_KBC_STS_UD1_POS 4u +#define MCHP_KBC_STS_UD1 BIT(MCHP_KBC_STS_UD1_POS) +#define MCHP_KBC_STS_AUXOBF_POS 5u +#define MCHP_KBC_STS_AUXOBF BIT(MCHP_KBC_STS_AUXOBF_POS) +#define MCHP_KBC_STS_UD2_POS 6u +#define MCHP_KBC_STS_UD2_MASK0 0x03ul +#define MCHP_KBC_STS_UD2_MASK 0xC0ul +#define MCHP_KBC_STS_UD2_0_POS 6u +#define MCHP_KBC_STS_UD2_0 BIT(6) +#define MCHP_KBC_STS_UD2_1 BIT(7) + +/* KBC_CTRL bit definitions */ +#define MCHP_KBC_CTRL_UD3_POS 0u +#define MCHP_KBC_CTRL_UD3 BIT(MCHP_KBC_CTRL_UD3_POS) +#define MCHP_KBC_CTRL_SAEN_POS 1u +#define MCHP_KBC_CTRL_SAEN BIT(MCHP_KBC_CTRL_SAEN_POS) +#define MCHP_KBC_CTRL_PCOBFEN_POS 2u +#define MCHP_KBC_CTRL_PCOBFEN BIT(MCHP_KBC_CTRL_PCOBFEN_POS) +#define MCHP_KBC_CTRL_UD4_POS 3u +#define MCHP_KBC_CTRL_UD4_MASK0 0x03ul +#define MCHP_KBC_CTRL_UD4_MASK 0x18ul +#define MCHP_KBC_CTRL_OBFEN_POS 5u +#define MCHP_KBC_CTRL_OBFEN BIT(MCHP_KBC_CTRL_OBFEN_POS) +#define MCHP_KBC_CTRL_UD5_POS 6u +#define MCHP_KBC_CTRL_UD5 BIT(MCHP_KBC_CTRL_UD5_POS) +#define MCHP_KBC_CTRL_AUXH_POS 7u +#define MCHP_KBC_CTRL_AUXH BIT(MCHP_KBC_CTRL_AUXH_POS) + +/* PCOBF register bit definitions */ +#define MCHP_KBC_PCOBF_EN_POS 0u +#define MCHP_KBC_PCOBF_EN BIT(MCHP_KBC_PCOBF_EN_POS) + +/* KBC_PORT92_EN register bit definitions */ +#define MCHP_KBC_PORT92_EN_POS 0u +#define MCHP_KBC_PORT92_EN BIT(MCHP_KBC_PORT92_EN_POS) + +#endif /* #ifndef _COMPONENT_KBC_H */ +/* end kbc.h */ +/** @} + */ diff --git a/mec/mec172x/component/keyscan.h b/mec/mec172x/component/keyscan.h new file mode 100644 index 0000000..ece3258 --- /dev/null +++ b/mec/mec172x/component/keyscan.h @@ -0,0 +1,83 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file keyscan.h + * MEC172x Keyboard matrix scan controller registers + */ +/** @defgroup MEC172x Peripherals KSCAN + */ + +#ifndef _COMPONENT_KSCAN_H +#define _COMPONENT_KSCAN_H + +#include +#include + +#include +#include + +#define MCHP_KSCAN_BASE_ADDR 0x40009C00ul + +/* KSCAN interrupts */ +#define MCHP_KSCAN_GIRQ 21u +#define MCHP_KSCAN_GIRQ_NVIC 13u +/* Direct mode connection to NVIC */ +#define MCHP_KSCAN_NVIC 135u +/* backwards compatibility misspelling */ +#define MCHP_KSAN_NVIC (MCHP_KSCAN_NVIC) + +#define MCHP_KSCAN_GIRQ_POS 25u +#define MCHP_KSCAN_GIRQ_VAL BIT(25) + +/* KSO_SEL */ +#define MCHP_KSCAN_KSO_SEL_REG_MASK 0xFFul +#define MCHP_KSCAN_KSO_LINES_POS 0u +#define MCHP_KSCAN_KSO_LINES_MASK0 0x1Ful +#define MCHP_KSCAN_KSO_LINES_MASK 0x1Ful +#define MCHP_KSCAN_KSO_ALL_POS 5u +#define MCHP_KSCAN_KSO_ALL BIT(5) +#define MCHP_KSCAN_KSO_EN_POS 6u +#define MCHP_KSCAN_KSO_EN BIT(6) +#define MCHP_KSCAN_KSO_INV_POS 7u +#define MCHP_KSCAN_KSO_INV BIT(7) + +/* KSI_IN */ +#define MCHP_KSCAN_KSI_IN_REG_MASK 0xFFul + +/* KSI_STS */ +#define MCHP_KSCAN_KSI_STS_REG_MASK 0xFFul + +/* KSI_IEN */ +#define MCHP_KSCAN_KSI_IEN_REG_MASK 0xFFul + +/* EXT_CTRL */ +#define MCHP_KSCAN_EXT_CTRL_REG_MASK 0x01ul +#define MCHP_KSCAN_EXT_CTRL_PREDRV_EN 0x01ul + +#endif /* #ifndef _COMPONENT_KSCAN_H */ +/* end kscan.h */ +/** @} + */ diff --git a/mec/mec172x/component/led.h b/mec/mec172x/component/led.h new file mode 100644 index 0000000..f011458 --- /dev/null +++ b/mec/mec172x/component/led.h @@ -0,0 +1,139 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file led.h + * MEC172x Breathing-Blinking LED definitions + */ +/** @defgroup MEC172x Peripherals LED + */ + +#ifndef _COMPONENT_LED_H +#define _COMPONENT_LED_H + +#include +#include + +#include +#include + +#define MCHP_LED_BASE_ADDR 0x4000B800ul +#define MCHP_LED_SPACING 0x100ul + +#define MCHP_LED0_ADDR 0x4000B800ul +#define MCHP_LED1_ADDR 0x4000B900ul +#define MCHP_LED2_ADDR 0x4000BA00ul +#define MCHP_LED3_ADDR 0x4000BB00ul + +#define MCHP_LED_ADDR(n) \ + (MCHP_LED_BASE_ADDR + ((uint32_t)(n) * MCHP_LED_SPACING)) + +/* LED register offsets */ +#define MCHP_LED_CFG_OFS 0x00ul +#define MCHP_LED_LIMITS_OFS 0x04ul +#define MCHP_LED_DELAY_OFS 0x08ul +#define MCHP_LED_UPD_STEP_OFS 0x0Cul +#define MCHP_LED_UPD_INTRVL_OFS 0x10ul +#define MCHP_LED_OUTPUT_DLY_OFS 0x14ul + +/* LED Configuration Register */ +#define MCHP_LED_CFG_CNTL_MASK 0x0003u +#define MCHP_LED_CFG_CNTL_LO 0x0000u +#define MCHP_LED_CFG_CNTL_BREATH 0x0001u +#define MCHP_LED_CFG_CNTL_BLINK 0x0002u +#define MCHP_LED_CFG_CNTL_HI 0x0003u +#define MCHP_LED_CFG_CLK_SRC_MCLK 0x0002u +#define MCHP_LED_CFG_CLK_SRC_32K 0x0000u +#define MCHP_LED_CFG_SYNC 0x0008u +#define MCHP_LED_CFG_PWM_COUNT_WIDTH_MASK 0x0030u +#define MCHP_LED_CFG_COUNT_WIDTH_8 0x0000u +#define MCHP_LED_CFG_COUNT_WIDTH_7 0x0010u +#define MCHP_LED_CFG_COUNT_WIDTH_6 0x0020u +#define MCHP_LED_CFG_EN_UPDATE 0x0040u +#define MCHP_LED_CFG_RESET 0x0080u +#define MCHP_LED_CFG_WDT_PRELOAD_MASK 0xFF00u +#define MCHP_LED_CFG_WDT_PRELOAD_POR 0x1400u +#define MCHP_LED_CFG_SYMMETRY_EN 0x10000u + +/* LED Limit Register */ +#define MCHP_LED_LIM_MIN_POS 0u +#define MCHP_LED_LIM_MIN_MASK 0xFFu +#define MCHP_LED_LIM_MAX_POS 8u +#define MCHP_LED_LIM_MAX_MASK 0xFF00ul + +/* LED Delay Register */ +#define MCHP_LED_DLY_LO_MASK 0x0000FFFul +#define MCHP_LED_DLY_HI_MASK 0x0FFF000ul +#define MCHP_LED_DLY_HI_POS 12u + +/* LED Step Size Register */ +#define MCHP_LED_STEP_FIELD_WIDTH 4u +#define MCHP_LED_STEP_MASK0 0x0Ful +#define MCHP_LED_STEP0_POS 0u +#define MCHP_LED_STEP0_MASK 0x0000000Ful +#define MCHP_LED_STEP1_POS 4u +#define MCHP_LED_STEP1_MASK 0x000000F0ul +#define MCHP_LED_STEP2_POS 8u +#define MCHP_LED_STEP2_MASK 0x00000F00ul +#define MCHP_LED_STEP3_POS 12u +#define MCHP_LED_STEP3_MASK 0x0000F000ul +#define MCHP_LED_STEP4_POS 16u +#define MCHP_LED_STEP4_MASK 0x000F0000ul +#define MCHP_LED_STEP5_POS 20u +#define MCHP_LED_STEP5_MASK 0x00F00000ul +#define MCHP_LED_STEP6_POS 24u +#define MCHP_LED_STEP6_MASK 0x0F000000ul +#define MCHP_LED_STEP7_POS 28u +#define MCHP_LED_STEP7_MASK 0xF0000000ul + +/* LED Update Register */ +#define MCHP_LED_UPDT_FIELD_WIDTH 4u +#define MCHP_LED_UPDT_MASK0 0x0Ful; +#define MCHP_LED_UPDT0_POS 0u +#define MCHP_LED_UPDT0_MASK 0x0000000Ful +#define MCHP_LED_UPDT1_POS 4u +#define MCHP_LED_UPDT1_MASK 0x000000F0ul +#define MCHP_LED_UPDT2_POS 8u +#define MCHP_LED_UPDT2_MASK 0x00000F00ul +#define MCHP_LED_UPDT3_POS 12u +#define MCHP_LED_UPDT3_MASK 0x0000F000ul +#define MCHP_LED_UPDT4_POS 16u +#define MCHP_LED_UPDT4_MASK 0x000F0000ul +#define MCHP_LED_UPDT5_POS 20u +#define MCHP_LED_UPDT5_MASK 0x00F00000ul +#define MCHP_LED_UPDT6_POS 24u +#define MCHP_LED_UPDT6_MASK 0x0F000000ul +#define MCHP_LED_UPDT7_POS 28u +#define MCHP_LED_UPDT7_MASK 0xF0000000ul + +#define MCHP_BLINK_0P5_HZ_DUTY_CYCLE 0x010ul +#define MCHP_BLINK_0P5_HZ_PRESCALE 0x0FFul +#define MCHP_BLINK_1_HZ_DUTY_CYCLE 0x020ul +#define MCHP_BLINK_1_HZ_PRESCALE 0x07Ful + +#endif /* #ifndef _COMPONENT_LED_H */ +/* end led.h */ +/** @} + */ diff --git a/mec/mec172x/component/mailbox.h b/mec/mec172x/component/mailbox.h new file mode 100644 index 0000000..711d75c --- /dev/null +++ b/mec/mec172x/component/mailbox.h @@ -0,0 +1,83 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file mailbox.h + * MEC172x Mailbox Registers + */ +/** @defgroup MEC172x Peripherals MBOX + */ + +#ifndef _COMPONENT_MAILBOX_H +#define _COMPONENT_MAILBOX_H + +#include +#include + +#include +#include + +#define MCHP_MBOX_BASE_ADDR 0x400F0000ul + +/* Mailbox interrupts */ +#define MCHP_MBOX_GIRQ 15u +#define MCHP_MBOX_GIRQ_NVIC 7u +#define MCHP_MBOX_NVIC 60u + +#define MCHP_KBC_MBOX_GIRQ_POS 20u +#define MCHP_KBC_MBOX_GIRQ BIT(MCHP_KBC_MBOX_GIRQ_POS) + +/* SMI Source register */ +#define MCHP_MBOX_SMI_SRC_EC_WR_POS 0u +#define MCHP_MBOX_SMI_SRC_EC_WR BIT(MCHP_MBOX_SMI_SRC_WR_POS) +#define MCHP_MBOX_SMI_SRC_SWI_POS 1u +#define MCHP_MBOX_SMI_SRC_SWI_MASK0 0x7Ful +#define MCHP_MBOX_SMI_SRC_SWI_MASK 0xFEul +#define MCHP_MBOX_SMI_SRC_SWI0 BIT(1) +#define MCHP_MBOX_SMI_SRC_SWI1 BIT(2) +#define MCHP_MBOX_SMI_SRC_SWI2 BIT(3) +#define MCHP_MBOX_SMI_SRC_SWI3 BIT(4) +#define MCHP_MBOX_SMI_SRC_SWI4 BIT(5) +#define MCHP_MBOX_SMI_SRC_SWI5 BIT(6) +#define MCHP_MBOX_SMI_SRC_SWI6 BIT(7) + +/* SMI Mask register */ +#define MCHP_MBOX_SMI_MASK_WR_EN_POS 0u +#define MCHP_MBOX_SMI_MASK_WR_EN BIT(MCHP_MBOX_SMI_MASK_WR_EN_POS) +#define MCHP_MBOX_SMI_SWI_EN_POS 1u +#define MCHP_MBOX_SMI_SWI_EN_MASK0 0x7Ful +#define MCHP_MBOX_SMI_SWI_EN_MASK 0xFEul +#define MCHP_MBOX_SMI_SRC_EN_SWI0 BIT(1) +#define MCHP_MBOX_SMI_SRC_EN_SWI1 BIT(2) +#define MCHP_MBOX_SMI_SRC_EN_SWI2 BIT(3) +#define MCHP_MBOX_SMI_SRC_EN_SWI3 BIT(4) +#define MCHP_MBOX_SMI_SRC_EN_SWI4 BIT(5) +#define MCHP_MBOX_SMI_SRC_EN_SWI5 BIT(6) +#define MCHP_MBOX_SMI_SRC_EN_SWI6 BIT(7) + +#endif /* #ifndef _COMPONENT_MAILBOX_H */ +/* end mailbox.h */ +/** @} + */ diff --git a/mec/mec172x/component/p80bd.h b/mec/mec172x/component/p80bd.h new file mode 100644 index 0000000..f49380d --- /dev/null +++ b/mec/mec172x/component/p80bd.h @@ -0,0 +1,118 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file p80bd.h + * MEC172x Port 80h BIOS Debug and Alias port capture Registers + */ +/** @defgroup MEC172x Peripherals Port 80h BIOS Debug Port capture + */ + +#ifndef _COMPONENT_P80BD_H +#define _COMPONENT_P80BD_H + +#include +#include + +#include +#include + +#define MCHP_P80BD_0_BASE_ADDR 0x400F8000ul + +#define MCHP_P80BD_0_GIRQ 15u +#define MCHP_P80BD_0_GIRQ_POS 22u +#define MCHP_P80BD_0_GIRQ_VAL BIT(22) +#define MCHP_P80BD_0_GIRQ_NVIC 7u +#define MCHP_P80BD_0_NVIC 62u + +/* HDATA - Write-Only 32-bit */ +#define MCHP_P80BD_HDATA_OFS 0x00ul +#define MCHP_P80BD_HDATA_MASK 0xFFFFFFFFul + +/* + * EC-only Data/Attributes 16-bit + * b[7:0] = data byte from capture FIFO + * b[15:8] = data attributes + */ +#define MCHP_P80BD_ECDA_OFS 0x100ul +#define MCHP_P80BD_ECDA_MASK 0x7FFFul +#define MCHP_P80BD_ECDA_DPOS 0 +#define MCHP_P80BD_ECDA_APOS 8 +#define MCHP_P80BD_ECDA_DMSK 0xFFul +#define MCHP_P80BD_ECDA_AMSK 0x7F00ul +#define MCHP_P80BD_ECDA_LANE_POS 8 +#define MCHP_P80BD_ECDA_LANE_MSK 0x0300ul +#define MCHP_P80BD_ECDA_LANE_0 0x0000ul +#define MCHP_P80BD_ECDA_LANE_1 0x0100ul +#define MCHP_P80BD_ECDA_LANE_2 0x0200ul +#define MCHP_P80BD_ECDA_LANE_3 0x0300ul +#define MCHP_P80BD_ECDA_LEN_POS 10 +#define MCHP_P80BD_ECDA_LEN_MSK 0x0C00ul +#define MCHP_P80BD_ECDA_LEN_1 0x0000ul +#define MCHP_P80BD_ECDA_LEN_2 0x0400ul +#define MCHP_P80BD_ECDA_LEN_4 0x0800ul +#define MCHP_P80BD_ECDA_LEN_INVAL 0x0C00ul +#define MCHP_P80BD_ECDA_NE BIT(12) +#define MCHP_P80BD_ECDA_OVR BIT(13) +#define MCHP_P80BD_ECDA_THR BIT(14) + +/* Configuration */ +#define MCHP_P80BD_CFG_OFS 0x104ul +#define MCHP_P80BD_CFG_MASK 0x80000703ul +#define MCHP_P80BD_CFG_FLUSH_FIFO BIT(0) /* WO */ +#define MCHP_P80BD_CFG_SNAP_CLR BIT(1) /* WO */ +#define MCHP_P80BD_CFG_FIFO_THR_POS 8 +#define MCHP_P80BD_CFG_FIFO_THR_MSK 0x700ul +#define MCHP_P80BD_CFG_FIFO_THR_1 0x000ul +#define MCHP_P80BD_CFG_FIFO_THR_4 0x100ul +#define MCHP_P80BD_CFG_FIFO_THR_8 0x200ul +#define MCHP_P80BD_CFG_FIFO_THR_16 0x300ul +#define MCHP_P80BD_CFG_FIFO_THR_20 0x400ul +#define MCHP_P80BD_CFG_FIFO_THR_24 0x500ul +#define MCHP_P80BD_CFG_FIFO_THR_28 0x600ul +#define MCHP_P80BD_CFG_FIFO_THR_30 0x700ul +#define MCHP_P80BD_CFG_SRST BIT(31) /* WO */ + +/* Status and Interrupt Enable 16-bit */ +#define MCHP_P80BD_SI_OFS 0x108u +#define MCHP_P80BD_SI_MASK 0x107u +#define MCHP_P80BD_SI_STS_MASK 0x007u +#define MCHP_P80BD_SI_IEN_MASK 0x100u +#define MCHP_P80BD_SI_NE_STS BIT(0) +#define MCHP_P80BD_SI_OVR_STS BIT(1) +#define MCHP_P80BD_SI_THR_STS BIT(2) +#define MCHP_P80BD_SI_THR_IEN BIT(8) + +/* Snapshot 32-bit (RO) */ +#define MCHP_P80BD_SS_OFS 0x10Cu +#define MCHP_P80BD_SS_MASK 0xFFFFFFFFul + +/* Capture 32-bit (RO). Current 4-byte Port 80 capture value */ +#define MCHP_P80BD_CAP_OFS 0x110u + +#endif /* #ifndef _COMPONENT_P80BD_H */ +/* end p80bd.h */ +/** @} + */ diff --git a/mec/mec172x/component/pcr.h b/mec/mec172x/component/pcr.h new file mode 100644 index 0000000..a8c279c --- /dev/null +++ b/mec/mec172x/component/pcr.h @@ -0,0 +1,566 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file pcr.h + * MEC172x Power Control Reset definitions + */ +/** @defgroup MEC172x Peripherals PCR + */ + +#include +#include + +#include +#include + +#ifndef _COMPONENT_PCR_H +#define _COMPONENT_PCR_H + +#define MCHP_PCR_BASE_ADDR 0x40080100ul + +#define MCHP_PCR_SYS_SLP_CTRL_OFS 0x00ul +#define MCHP_PCR_SYS_CLK_CTRL_OFS 0x04ul +#define MCHP_PCR_SLOW_CLK_CTRL_OFS 0x08ul +#define MCHP_PCR_OSC_ID_OFS 0x0Cul +#define MCHP_PCR_PRS_OFS 0x10ul +#define MCHP_PCR_PR_CTRL_OFS 0x14ul +#define MCHP_PCR_SYS_RESET_OFS 0x18ul +#define MCHP_PCR_PKE_CLK_CTRL_OFS 0x1Cul +#define MCHP_PCR_SLP_EN0_OFS 0x30ul +#define MCHP_PCR_SLP_EN1_OFS 0x34ul +#define MCHP_PCR_SLP_EN2_OFS 0x38ul +#define MCHP_PCR_SLP_EN3_OFS 0x3Cul +#define MCHP_PCR_SLP_EN4_OFS 0x40ul +#define MCHP_PCR_CLK_REQ0_OFS 0x50ul +#define MCHP_PCR_CLK_REQ1_OFS 0x54ul +#define MCHP_PCR_CLK_REQ2_OFS 0x58ul +#define MCHP_PCR_CLK_REQ3_OFS 0x5Cul +#define MCHP_PCR_CLK_REQ4_OFS 0x60ul +#define MCHP_PCR_PERIPH_RST0_OFS 0x70ul +#define MCHP_PCR_PERIPH_RST1_OFS 0x74ul +#define MCHP_PCR_PERIPH_RST2_OFS 0x78ul +#define MCHP_PCR_PERIPH_RST3_OFS 0x7Cul +#define MCHP_PCR_PERIPH_RST4_OFS 0x80ul +#define MCHP_PCR_PERIPH_RST_LCK_OFS 0x84ul +#define MCHP_PCR_VBAT_SRST_OFS 0x88ul +#define MCHP_PCR_CLK32K_SRC_VTR_OFS 0x8Cul +#define MCHP_PCR_CNT32K_PER_OFS 0xC0ul +#define MCHP_PCR_CNT32K_PULSE_HI_OFS 0xC4ul +#define MCHP_PCR_CNT32K_PER_MIN_OFS 0xC8ul +#define MCHP_PCR_CNT32K_PER_MAX_OFS 0xCCul +#define MCHP_PCR_CNT32K_DV_OFS 0xD0ul +#define MCHP_PCR_CNT32K_DV_MAX_OFS 0xD4ul +#define MCHP_PCR_CNT32K_VALID_OFS 0xD8ul +#define MCHP_PCR_CNT32K_VALID_MIN_OFS 0xDCul +#define MCHP_PCR_CNT32K_CTRL_OFS 0xE0ul +#define MCHP_PCR_CLK32K_MON_ISTS_OFS 0xE4ul +#define MCHP_PCR_CLK32K_MON_IEN_OFS 0xE8ul + +#define MCHP_PCR_SYS_SLP_CTRL_ADDR (MCHP_PCR_BASE_ADDR) +#define MCHP_PCR_SYS_CLK_CTRL_ADDR (MCHP_PCR_BASE_ADDR + 0x04ul) +#define MCHP_PCR_SLOW_CLK_CTRL_ADDR (MCHP_PCR_BASE_ADDR + 0x08ul) +#define MCHP_PCR_OSC_ID_ADDR (MCHP_PCR_BASE_ADDR + 0x0Cul) +#define MCHP_PCR_PRS_ADDR (MCHP_PCR_BASE_ADDR + 0x10ul) +#define MCHP_PCR_PR_CTRL_ADDR (MCHP_PCR_BASE_ADDR + 0x14ul) +#define MCHP_PCR_SYS_RESET_ADDR (MCHP_PCR_BASE_ADDR + 0x18ul) +#define MCHP_PCR_PKE_CLK_CTRL_ADDR (MCHP_PCR_BASE_ADDR + 0x1Cul) +#define MCHP_PCR_SLP_EN0_ADDR (MCHP_PCR_BASE_ADDR + 0x30ul) +#define MCHP_PCR_SLP_EN1_ADDR (MCHP_PCR_BASE_ADDR + 0x34ul) +#define MCHP_PCR_SLP_EN2_ADDR (MCHP_PCR_BASE_ADDR + 0x38ul) +#define MCHP_PCR_SLP_EN3_ADDR (MCHP_PCR_BASE_ADDR + 0x3Cul) +#define MCHP_PCR_SLP_EN4_ADDR (MCHP_PCR_BASE_ADDR + 0x40ul) +#define MCHP_PCR_CLK_REQ0_ADDR (MCHP_PCR_BASE_ADDR + 0x50ul) +#define MCHP_PCR_CLK_REQ1_ADDR (MCHP_PCR_BASE_ADDR + 0x54ul) +#define MCHP_PCR_CLK_REQ2_ADDR (MCHP_PCR_BASE_ADDR + 0x58ul) +#define MCHP_PCR_CLK_REQ3_ADDR (MCHP_PCR_BASE_ADDR + 0x5Cul) +#define MCHP_PCR_CLK_REQ4_ADDR (MCHP_PCR_BASE_ADDR + 0x60ul) +#define MCHP_PCR_PERIPH_RST0_ADDR (MCHP_PCR_BASE_ADDR + 0x70ul) +#define MCHP_PCR_PERIPH_RST1_ADDR (MCHP_PCR_BASE_ADDR + 0x74ul) +#define MCHP_PCR_PERIPH_RST2_ADDR (MCHP_PCR_BASE_ADDR + 0x78ul) +#define MCHP_PCR_PERIPH_RST3_ADDR (MCHP_PCR_BASE_ADDR + 0x7Cul) +#define MCHP_PCR_PERIPH_RST4_ADDR (MCHP_PCR_BASE_ADDR + 0x80ul) +#define MCHP_PCR_PERIPH_RESET_LOCK_ADDR (MCHP_PCR_BASE_ADDR + 0x84ul) +#define MCHP_PCR_VBAT_SRST_ADDR (MCHP_PCR_BASE_ADDR + 0x88ul) +#define MCHP_PCR_CLK32K_SRC_VTR_ADDR (MCHP_PCR_BASE_ADDR + 0x8Cul) +#define MCHP_PCR_CNT32K_PER_ADDR (MCHP_PCR_BASE_ADDR + 0xC0ul) +#define MCHP_PCR_CNT32K_PULSE_HI_ADDR (MCHP_PCR_BASE_ADDR + 0xC4ul) +#define MCHP_PCR_CNT32K_PER_MIN_ADDR (MCHP_PCR_BASE_ADDR + 0xC8ul) +#define MCHP_PCR_CNT32K_PER_MAX_ADDR (MCHP_PCR_BASE_ADDR + 0xCCul) +#define MCHP_PCR_CNT32K_DV_ADDR (MCHP_PCR_BASE_ADDR + 0xD0ul) +#define MCHP_PCR_CNT32K_DV_MAX_ADDR (MCHP_PCR_BASE_ADDR + 0xD4ul) +#define MCHP_PCR_CNT32K_VALID_ADDR (MCHP_PCR_BASE_ADDR + 0xD8ul) +#define MCHP_PCR_CNT32K_VALID_MIN_ADDR (MCHP_PCR_BASE_ADDR + 0xDCul) +#define MCHP_PCR_CNT32K_CTRL_ADDR (MCHP_PCR_BASE_ADDR + 0xE0ul) +#define MCHP_PCR_CLK32K_MON_ISTS_ADDR (MCHP_PCR_BASE_ADDR + 0xE4ul) +#define MCHP_PCR_CLK32K_MON_IEN_ADDR (MCHP_PCR_BASE_ADDR + 0xE8ul) + +#define MCHP_PCR_SLP_EN_ADDR(n) \ + (MCHP_PCR_BASE_ADDR + 0x30ul + ((uint32_t)(n) * 4U)) +#define MCHP_PCR_CLK_REQ_ADDR(n) \ + (MCHP_PCR_BASE_ADDR + 0x50ul + ((uint32_t)(n) * 4U)) +#define MCHP_PCR_PERIPH_RESET_ADDR(n) \ + (MCHP_PCR_BASE_ADDR + 0x70ul + ((uint32_t)(n) * 4U)) + +#define MCHP_PCR_SLEEP_EN (1u) +#define MCHP_PCR_SLEEP_DIS (0u) + +/* + * MEC172x PCR implements multiple SLP_EN, CLR_REQ, and RST_EN registers. + * CLK_REQ bits are read-only. The peripheral sets its CLK_REQ if it requires + * clocks. CLK_REQ bits must all be zero for the PCR block to put the MEC17xx + * into light or heavy sleep. + * SLP_EN bit = 1 instructs HW to gate off clock tree to peripheral only if + * peripherals PCR CLK_REQ bit is 0. + * RST_EN bit = 1 will reset the peripheral at any time. The RST_EN registers + * must be unlocked by writing the unlock code to PCR Peripheral Reset Lock + * register. + * SLP_EN usage is: + * Initialization set all PCR SLP_EN bits = 0 except for crypto blocks as + * these IP do not implement internal clock gating. + * When firmware wants to enter light or heavy sleep. + * Configure wake up source(s) + * Write MCHP_PCR_SYS_SLP_CTR register to value based on light/heavy with + * SLEEP_ALL bit = 1. + * Execute Cortex-M4 WFI sequence. DSB(), ISB(), WFI(), NOP() + * Cortex-M4 will assert sleep signal to PCR block. + * PCR HW will spin until all CLK_REQ==0 + * PCR will then turn off clocks based on light/heavy sleep. + * + * RST_EN usage is: + * Save and disable maskable interrupts + * Write unlock code to PCR Peripheral Reset Lock + * Write bit patterns to one or more of PCR RST_EN[0, 4] registers + * Selected peripherals will be reset. + * Write lock code to PCR Peripheral Reset Lock. + * Restore interrupts. + */ +#define MCHP_MAX_PCR_SCR_REGS 5ul + +/* VTR Powered PCR registers */ +#define MCHP_PCR_SLP(bitpos) BIT(bitpos) + +/* PCR System Sleep Control */ +#define MCHP_PCR_SYS_SLP_CTRL_MASK 0x0109ul +#define MCHP_PCR_SYS_SLP_CTRL_SLP_HEAVY BIT(0) +#define MCHP_PCR_SYS_SLP_CTRL_SLP_ALL BIT(3) +/* + * bit[8] can be used to prevent entry to heavy sleep unless the + * PLL is locked. + * bit[8]==0 (POR default) system will allow entry to light or heavy + * sleep if and only if PLL is locked. + * bit[8]==1 system will allow entry to heavy sleep before PLL is locked. + */ +#define MCHP_PCR_SYS_SLP_CTRL_ALLOW_SLP_NO_PLL_LOCK BIT(8) + +/* Assert all peripheral sleep enables once CPU asserts its sleep signal */ +#define MCHP_PCR_SYS_SLP_LIGHT 0x08ul +#define MCHP_PCR_SYS_SLP_HEAVY 0x09ul + +/* + * PCR Process Clock Control + * Divides 96MHz clock to ARM Cortex-M4 core including + * SysTick and NVIC. + */ +#define MCHP_PCR_PROC_CLK_CTRL_MASK 0xFFul +#define MCHP_PCR_PROC_CLK_CTRL_96MHZ 0x01ul +#define MCHP_PCR_PROC_CLK_CTRL_48MHZ 0x02ul +#define MCHP_PCR_PROC_CLK_CTRL_24MHZ 0x04ul +#define MCHP_PCR_PROC_CLK_CTRL_12MHZ 0x08ul +#define MCHP_PCR_PROC_CLK_CTRL_6MHZ 0x10ul +#define MCHP_PCR_PROC_CLK_CTRL_2MHZ 0x30ul +#define MCHP_PCR_PROC_CLK_CTRL_DFLT MCHP_PCR_PROC_CLK_CTRL_24MHZ + +/* PCR Slow Clock Control. Clock divicder for 100KHz clock domain */ +#define MCHP_PCR_SLOW_CLK_CTRL_MASK 0x3FFul +#define MCHP_PCR_SLOW_CLK_CTRL_100KHZ 0x1E0ul + +/* PCR Oscillator ID register (Read-Only) */ +#define MCHP_PCR_OSC_ID_MASK 0x1FFul +#define MCHP_PCR_OSC_ID_PLL_LOCK BIT(8) + +/* PCR Power Reset Status Register */ +#define MCHP_PCR_PRS_MASK 0x0DFCul +#define MCHP_PCR_PRS_VCC_PWRGD_STATE_RO BIT(2) +#define MCHP_PCR_PRS_HOST_RESET_STATE_RO BIT(3) +#define MCHP_PCR_PRS_VTR_RST_RWC BIT(4) +#define MCHP_PCR_PRS_VBAT_RST_RWC BIT(5) +#define MCHP_PCR_PRS_RST_SYS_RWC BIT(6) +#define MCHP_PCR_PRS_JTAG_RST_RO BIT(7) +#define MCHP_PCR_PRS_WDT_EVENT_RWC BIT(8) +#define MCHP_PCR_PRS_32K_ACTIVE_RO BIT(10) +#define MCHP_PCR_PRS_LPC_ESPI_CLK_ACTIVE_RO BIT(11) + +/* PCR Power Reset Control Register */ +#define MCHP_PCR_PR_CTRL_MASK 0x101ul +#define MCHP_PCR_PR_CTRL_PWR_INV BIT(0) +#define MCHP_PCR_PR_CTRL_USE_ESPI_PLTRST 0ul +#define MCHP_PCR_PR_CTRL_USE_PCI_RST BIT(8) + +/* PCR System Reset Register */ +#define MCHP_PCR_SYS_RESET_MASK 0x100ul +#define MCHP_PCR_SYS_RESET_NOW BIT(8) + +/* Turbo Clock Register */ +#define MCHP_PCR_TURBO_CLK_MASK 0x04ul +#define MCHP_PCR_TURBO_CLK_96M BIT(2) + +/* + * Sleep Enable Reg 0 (Offset +30h) + * Clock Required Reg 0 (Offset +50h) + * Reset Enable Reg 0 (Offset +70h) + */ +#define MCHP_PCR0_JTAG_STAP_POS 0u +#define MCHP_PCR0_OTP_POS 1u +#define MCHP_PCR0_ISPI_EMC_POS 2u + +/* + * Sleep Enable Reg 1 (Offset +34h) + * Clock Required Reg 1 (Offset +54h) + * Reset Enable Reg 1 (Offset +74h) + */ +#define MCHP_PCR1_ECIA_POS 0u +#define MCHP_PCR1_PECI_POS 1u +#define MCHP_PCR1_TACH0_POS 2u +#define MCHP_PCR1_PWM0_POS 4u +#define MCHP_PCR1_PMC_POS 5u +#define MCHP_PCR1_DMA_POS 6u +#define MCHP_PCR1_TFDP_POS 7u +#define MCHP_PCR1_CPU_POS 8u +#define MCHP_PCR1_WDT_POS 9u +#define MCHP_PCR1_SMB0_POS 10u +#define MCHP_PCR1_TACH1_POS 11u +#define MCHP_PCR1_TACH2_POS 12u +#define MCHP_PCR1_TACH3_POS 13u +#define MCHP_PCR1_PWM1_POS 20u +#define MCHP_PCR1_PWM2_POS 21u +#define MCHP_PCR1_PWM3_POS 22u +#define MCHP_PCR1_PWM4_POS 23u +#define MCHP_PCR1_PWM5_POS 24u +#define MCHP_PCR1_PWM6_POS 25u +#define MCHP_PCR1_PWM7_POS 26u +#define MCHP_PCR1_PWM8_POS 27u +#define MCHP_PCR1_ECS_POS 29u +#define MCHP_PCR1_B16TMR0_POS 30u +#define MCHP_PCR1_B16TMR1_POS 31u + +/* + * Sleep Enable Reg 2 (Offset +38h) + * Clock Required Reg 2 (Offset +58h) + * Reset Enable Reg 2 (Offset +78h) + */ +#define MCHP_PCR2_EMI0_POS 0u +#define MCHP_PCR2_UART0_POS 1u +#define MCHP_PCR2_UART1_POS 2u +#define MCHP_PCR2_GCFG_POS 12u +#define MCHP_PCR2_ACPI_EC0_POS 13u +#define MCHP_PCR2_ACPI_EC1_POS 14u +#define MCHP_PCR2_ACPI_PM1_POS 15u +#define MCHP_PCR2_KBC_POS 16u +#define MCHP_PCR2_MBOX_POS 17u +#define MCHP_PCR2_RTC_POS 18u +#define MCHP_PCR2_ESPI_POS 19u +#define MCHP_PCR2_SCR32_POS 20u +#define MCHP_PCR2_ACPI_EC2_POS 21u +#define MCHP_PCR2_ACPI_EC3_POS 22u +#define MCHP_PCR2_ACPI_EC4_POS 23u +#define MCHP_PCR2_P80BD_POS 25u +#define MCHP_PCR2_ESPI_SAF_POS 27u +#define MCHP_PCR2_GLUE_POS 29u + +/* + * Sleep Enable Reg 3 (Offset +3Ch) + * Clock Required Reg 3 (Offset +5Ch) + * Reset Enable Reg 3 (Offset +7Ch) + */ +#define MCHP_PCR3_ADC_POS 3u +#define MCHP_PCR3_PS2_0_POS 5u +#define MCHP_PCR3_GPSPI0_POS 9u +#define MCHP_PCR3_HTMR0_POS 10u +#define MCHP_PCR3_KEYSCAN_POS 11u +#define MCHP_PCR3_RPMFAN0_POS 12u +#define MCHP_PCR3_SMB1_POS 13u +#define MCHP_PCR3_SMB2_POS 14u +#define MCHP_PCR3_SMB3_POS 15u +#define MCHP_PCR3_LED0_POS 16u +#define MCHP_PCR3_LED1_POS 17u +#define MCHP_PCR3_LED2_POS 18u +#define MCHP_PCR3_BCL0_POS 19u +#define MCHP_PCR3_SMB4_POS 20u +#define MCHP_PCR3_B16TMR2_POS 21u +#define MCHP_PCR3_B16TMR3_POS 22u +#define MCHP_PCR3_B32TMR0_POS 23u +#define MCHP_PCR3_B32TMR1_POS 24u +#define MCHP_PCR3_LED3_POS 25u +#define MCHP_PCR3_CRYPTO_POS 26u +#define MCHP_PCR3_HTMR1_POS 29u +#define MCHP_PCR3_CCT_POS 30u +#define MCHP_PCR3_PWM9_POS 31u + +#define MCHP_PCR3_CRYPTO_MASK BIT(MCHP_PCR3_CRYPTO_POS) + +/* + * Sleep Enable Reg 4 (Offset +40h) + * Clock Required Reg 4 (Offset +60h) + * Reset Enable Reg 4 (Offset +80h) + */ +#define MCHP_PCR4_PWM10_POS 0u +#define MCHP_PCR4_PWM11_POS 1u +#define MCHP_CTMR0_POS 2u +#define MCHP_CTMR1_POS 3u +#define MCHP_CTMR2_POS 4u +#define MCHP_CTMR3_POS 5u +#define MCHP_PCR4_RTMR_POS 6u +#define MCHP_PCR4_RPMFAN1_POS 7u +#define MCHP_PCR4_QMSPI_POS 8u +#define MCHP_PCR4_RCID0_POS 10u +#define MCHP_PCR4_RCID1_POS 11u +#define MCHP_PCR4_RCID2_POS 12u +#define MCHP_PCR4_PHOT_POS 13u +#define MCHP_PCR4_EEPROM_POS 14u +#define MCHP_PCR4_SPIP_POS 16u +#define MCHP_PCR4_GPSPI1_POS 22u + +/* Reset Enable Lock (Offset +84h) */ +#define MCHP_PCR_RSTEN_UNLOCK 0xA6382D4Cul +#define MCHP_PCR_RSTEN_LOCK 0xA6382D4Dul + +/* VBAT Soft Reset (Offset +88h) */ +#define MCHP_PCR_VBSR_MASK BIT(0) +#define MCHP_PCR_VBSR_EN BIT(0) /* self clearing */ + +/* VTR Source 32 KHz Clock (Offset +8Ch) */ +#define MCHP_PCR_VTR_32K_SRC_MASK 0x03U +#define MCHP_PCR_VTR_32K_SRC_SILOSC 0x00U +#define MCHP_PCR_VTR_32K_SRC_XTAL 0x01U +#define MCHP_PCR_VTR_32K_SRC_PIN 0x02U +#define MCHP_PCR_VTR_32K_SRC_NONE 0x03U + +/* + * Clock monitor 32KHz period counter (Offset +C0h, RO) + * Clock monitor 32KHz high counter (Offset +C4h, RO) + * Clock monitor 32KHz period counter minimum (Offset +C8h, RW) + * Clock monitor 32KHz period counter maximum (Offset +CCh, RW) + * Clock monitor 32KHz Duty Cycle variation counter (Offset +D0h, RO) + * Clock monitor 32KHz Duty Cycle variation counter maximum (Offset +D4h, RW) + */ +#define MCHP_PCR_CLK32M_CNT_MASK 0xFFFFU + +/* + * Clock monitor 32KHz Valid Count (Offset +0xD8, RO) + * Clock monitor 32KHz Valid Count minimum (Offset +0xDC, RW) + */ +#define MCHP_PCR_CLK32M_VALID_CNT_MASK 0xFFU + +/* Clock monitor control register (Offset +0xE0, RW) */ +#define MCHP_PCR_CLK32M_CTRL_MASK 0x01000017U +#define MCHP_PCR_CLK32M_CTRL_PER_EN BIT(0) +#define MCHP_PCR_CLK32M_CTRL_DC_EN BIT(1) +#define MCHP_PCR_CLK32M_CTRL_VAL_EN BIT(2) +#define MCHP_PCR_CLK32M_CTRL_SRC_SO BIT(4) +#define MCHP_PCR_CLK32M_CTRL_CLR_CNT BIT(24) + +/* Clock monitor interrupt status (Offset +0xE4, R/W1C) */ +#define MCHP_PCR_CLK32M_ISTS_MASK 0x7FU +#define MCHP_PCR_CLK32M_ISTS_PULSE_RDY BIT(0) +#define MCHP_PCR_CLK32M_ISTS_PASS_PER BIT(1) +#define MCHP_PCR_CLK32M_ISTS_PASS_DC BIT(2) +#define MCHP_PCR_CLK32M_ISTS_FAIL BIT(3) +#define MCHP_PCR_CLK32M_ISTS_STALL BIT(4) +#define MCHP_PCR_CLK32M_ISTS_VALID BIT(5) +#define MCHP_PCR_CLK32M_ISTS_UNWELL BIT(6) + +/* Clock monitor interrupt enable (Offset +0xE8, RW) */ +#define MCHP_PCR_CLK32M_IEN_MASK 0x7FU +#define MCHP_PCR_CLK32M_IEN_PULSE_RDY BIT(0) +#define MCHP_PCR_CLK32M_IEN_PASS_PER BIT(1) +#define MCHP_PCR_CLK32M_IEN_PASS_DC BIT(2) +#define MCHP_PCR_CLK32M_IEN_FAIL BIT(3) +#define MCHP_PCR_CLK32M_IEN_STALL BIT(4) +#define MCHP_PCR_CLK32M_IEN_VALID BIT(5) +#define MCHP_PCR_CLK32M_IEN_UNWELL BIT(6) + +/* PCR 32KHz clock monitor uses 48 MHz for all counters */ +#define MCHP_PCR_CLK32M_CLOCK 48000000U + +/* PCR register access */ +#define MCHP_PCR_SLP_CTRL() REG32(MCHP_PCR_SYS_SLP_CTRL_ADDR) +#define MCHP_PCR_PROC_CLK_DIV() REG32(MCHP_PCR_SYS_CLK_CTRL_ADDR) +#define MCHP_PCR_SLOW_CLK_CTRL() REG32(MCHP_PCR_SLOW_CLK_CTRL_ADDR) +#define MCHP_PCR_OSC_ID() REG32(MCHP_PCR_OSC_ID_ADDR) +#define MCHP_PCR_PRS() REG32(MCHP_PCR_PRS_ADDR) +#define MCHP_PCR_PR_CTRL() REG32(MCHP_PCR_PR_CTRL_ADDR) +#define MCHP_PCR_SYS_RESET() REG32(MCHP_PCR_SYS_RESET_ADDR) +#define MCHP_PCR_PERIPH_RST_LOCK() REG32(MCHP_PCR_PERIPH_RESET_LOCK_ADDR) +#define MCHP_PCR_SLP_EN(n) REG32(MCHP_PCR_SLP_EN_ADDR(n)) +#define MCHP_PCR_CLK_REQ_RO(n) REG32(MCHP_PCR_CLK_REQ_ADDR(n)) +#define MCHP_PCR_PERIPH_RST(n) REG32(MCHP_PCR_PERIPH_RESET_ADDR(n)) + +#define MCHP_PCR_DEV_SLP_EN_CLR(n, b) \ + REG32(MCHP_PCR_SLP_EN_ADDR(n)) &= ~BIT((b)) + +#define MCHP_PCR_DEV_SLP_EN_SET(n, b) \ + REG32(MCHP_PCR_SLP_EN_ADDR(n)) |= BIT((b)) + +/* + * Encode peripheral SLP_EN/CLK_REQ/RST_EN bit number and register index. + * b[4:0] = bit number + * b[10:8] = zero based register number + */ +#define MCHP_PCR_ERB(rnum, bnum) ((((rnum) & 0x07u) << 8) | ((bnum) & 0x1fu)) +#define MCHP_PCR_ERB_RNUM(erb) (((uint32_t)(erb) >> 8) & 0x07u) +#define MCHP_PCR_ERB_BITPOS(erb) ((uint32_t)(erb) & 0x1fu) + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum pcr_id { + PCR_STAP = MCHP_PCR_ERB(0, 0), + PCR_OTP = MCHP_PCR_ERB(0, 1), + PCR_ECIA = MCHP_PCR_ERB(1, 0), + PCR_PECI = MCHP_PCR_ERB(1, 1), + PCR_TACH0 = MCHP_PCR_ERB(1, 2), + PCR_PWM0 = MCHP_PCR_ERB(1, 4), + PCR_PMC = MCHP_PCR_ERB(1, 5), + PCR_DMA = MCHP_PCR_ERB(1, 6), + PCR_TFDP = MCHP_PCR_ERB(1, 7), + PCR_CPU = MCHP_PCR_ERB(1, 8), + PCR_WDT = MCHP_PCR_ERB(1, 9), + PCR_SMB0 = MCHP_PCR_ERB(1, 10), + PCR_TACH1 = MCHP_PCR_ERB(1, 11), + PCR_TACH2 = MCHP_PCR_ERB(1, 12), + PCR_TACH3 = MCHP_PCR_ERB(1, 13), + PCR_PWM1 = MCHP_PCR_ERB(1, 20), + PCR_PWM2 = MCHP_PCR_ERB(1, 21), + PCR_PWM3 = MCHP_PCR_ERB(1, 22), + PCR_PWM4 = MCHP_PCR_ERB(1, 23), + PCR_PWM5 = MCHP_PCR_ERB(1, 24), + PCR_PWM6 = MCHP_PCR_ERB(1, 25), + PCR_PWM7 = MCHP_PCR_ERB(1, 26), + PCR_PWM8 = MCHP_PCR_ERB(1, 27), + PCR_ECS = MCHP_PCR_ERB(1, 29), + PCR_B16TMR0 = MCHP_PCR_ERB(1, 30), + PCR_B16TMR1 = MCHP_PCR_ERB(1, 31), + PCR_EMI0 = MCHP_PCR_ERB(2, 0), + PCR_UART0 = MCHP_PCR_ERB(2, 1), + PCR_UART1 = MCHP_PCR_ERB(2, 2), + PCR_GCFG = MCHP_PCR_ERB(2, 12), + PCR_ACPI_EC0 = MCHP_PCR_ERB(2, 13), + PCR_ACPI_EC1 = MCHP_PCR_ERB(2, 14), + PCR_ACPI_PM1 = MCHP_PCR_ERB(2, 15), + PCR_KBC = MCHP_PCR_ERB(2, 16), + PCR_MBOX = MCHP_PCR_ERB(2, 17), + PCR_RTC = MCHP_PCR_ERB(2, 18), + PCR_ESPI = MCHP_PCR_ERB(2, 19), + PCR_SCR32 = MCHP_PCR_ERB(2, 20), + PCR_ACPI_EC2 = MCHP_PCR_ERB(2, 21), + PCR_ACPI_EC3 = MCHP_PCR_ERB(2, 22), + PCR_ACPI_EC4 = MCHP_PCR_ERB(2, 23), + PCR_P80DP = MCHP_PCR_ERB(2, 25), + PCR_ESPI_SAF = MCHP_PCR_ERB(2, 27), + PCR_GLUE = MCHP_PCR_ERB(2, 29), + PCR_ADC = MCHP_PCR_ERB(3, 3), + PCR_PS2_0 = MCHP_PCR_ERB(3, 5), + PCR_GPSPI_0 = MCHP_PCR_ERB(3, 9), + PCR_HTMR0 = MCHP_PCR_ERB(3, 10), + PCR_KEYSCAN = MCHP_PCR_ERB(3, 11), + PCR_RPMFAN_0 = MCHP_PCR_ERB(3, 12), + PCR_SMB1 = MCHP_PCR_ERB(3, 13), + PCR_SMB2 = MCHP_PCR_ERB(3, 14), + PCR_SMB3 = MCHP_PCR_ERB(3, 15), + PCR_LED0 = MCHP_PCR_ERB(3, 16), + PCR_LED1 = MCHP_PCR_ERB(3, 17), + PCR_LED2 = MCHP_PCR_ERB(3, 18), + PCR_BCL_0 = MCHP_PCR_ERB(3, 19), + PCR_SMB4 = MCHP_PCR_ERB(3, 20), + PCR_B16TMR2 = MCHP_PCR_ERB(3, 21), + PCR_B16MTR3 = MCHP_PCR_ERB(3, 22), + PCR_B32TMR0 = MCHP_PCR_ERB(3, 23), + PCR_B32TMR1 = MCHP_PCR_ERB(3, 24), + PCR_LED3 = MCHP_PCR_ERB(3, 25), + PCR_CRYPTO = MCHP_PCR_ERB(3, 26), + PCR_HTMR1 = MCHP_PCR_ERB(3, 29), + PCR_CCT = MCHP_PCR_ERB(3, 30), + PCR_PWM9 = MCHP_PCR_ERB(3, 31), + PCR_PWM10 = MCHP_PCR_ERB(4, 0), + PCR_PWM11 = MCHP_PCR_ERB(4, 1), + PCR_CTMR_0 = MCHP_PCR_ERB(4, 2), + PCR_CTMR_1 = MCHP_PCR_ERB(4, 3), + PCR_CTMR_2 = MCHP_PCR_ERB(4, 4), + PCR_CTMR_3 = MCHP_PCR_ERB(4, 5), + PCR_RTMR = MCHP_PCR_ERB(4, 6), + PCR_RPMFAN_1 = MCHP_PCR_ERB(4, 7), + PCR_QMSPI = MCHP_PCR_ERB(4, 8), + PCR_RCID_0 = MCHP_PCR_ERB(4, 10), + PCR_RCID_1 = MCHP_PCR_ERB(4, 11), + PCR_RCID_2 = MCHP_PCR_ERB(4, 12), + PCR_PHOT = MCHP_PCR_ERB(4, 13), + PCR_EEPROM = MCHP_PCR_ERB(4, 14), + PCR_SPIP = MCHP_PCR_ERB(4, 16), + PCR_GPSPI_1 = MCHP_PCR_ERB(4, 22), + PCR_MAX_ID, +} PCR_ID; + +static __attribute__ ((always_inline)) inline void +mec_pcr_periph_slp_ctrl(PCR_ID pcr_id, uint8_t enable) +{ + uint32_t bitpos = MCHP_PCR_ERB_BITPOS(pcr_id); + uint32_t ofs = MCHP_PCR_ERB_RNUM(pcr_id); + uintptr_t raddr = (uintptr_t)(MCHP_PCR_SLP_EN0_ADDR); + + raddr += (ofs * 4u); + if (enable) { + REG32(raddr) |= BIT(bitpos); + } else { + REG32(raddr) &= ~BIT(bitpos); + } +} + +#define mchp_pcr_periph_slp_ctrl(id, en) mec_pcr_periph_slp_ctrl((id), (en)) + +static __attribute__ ((always_inline)) inline void +mec_pcr_periph_reset(PCR_ID pcr_id) +{ + uint32_t bitpos = MCHP_PCR_ERB_BITPOS(pcr_id); + uint32_t ofs = MCHP_PCR_ERB_RNUM(pcr_id); + uintptr_t raddr = (uintptr_t)(MCHP_PCR_SLP_EN0_ADDR); + + raddr += (ofs * 4u); + REG32(MCHP_PCR_PERIPH_RESET_LOCK_ADDR) = MCHP_PCR_RSTEN_UNLOCK; + REG32(raddr) = BIT(bitpos); + REG32(MCHP_PCR_PERIPH_RESET_LOCK_ADDR) = MCHP_PCR_RSTEN_LOCK; +} + +#define mchp_pcr_periph_reset(id) mec_pcr_periph_reset((id)) + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _COMPONENT_PCR_H */ +/* end pcr.h */ +/** @} + */ diff --git a/mec/mec172x/component/peci.h b/mec/mec172x/component/peci.h new file mode 100644 index 0000000..9083e17 --- /dev/null +++ b/mec/mec172x/component/peci.h @@ -0,0 +1,164 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file peci.h + * MEC172x Platform Environment Control Interface registers + */ +/** @defgroup MEC172x Peripherals PECI + */ + +#ifndef _COMPONENT_PECI_H +#define _COMPONENT_PECI_H + +#include +#include + +#include +#include + +#define MCHP_PECI_BASE_ADDR 0x40006400ul + +/* PECI interrupts. */ +#define MCHP_PECI_GIRQ 17u + +/* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ +#define MCHP_PECI_GIRQ_POS 0 + +#define MCHP_PECI_GIRQ_VAL BIT(MCHP_PECI_GIRQ_POS) + +/* PECI GIRQ aggregated NVIC input */ +#define MCHP_PECI_NVIC_AGGR 9u + +/* PECI direct NVIC inputs */ +#define MCHP_PECI_NVIC_DIRECT 70u + +/* Write Data register */ +#define MCHP_PECI_WR_DATA_REG_OFS 0U +#define MCHP_PECI_WR_DATA_MASK 0xffU + +/* Read Data register */ +#define MCHP_PECI_RD_DATA_REG_OFS 4U +#define MCHP_PECI_RD_DATA_MASK 0xffU + +/* Control register */ +#define MCHP_PECI_CTRL_REG_OFS 8U +#define MCHP_PECI_CTRL_MASK 0xE9U +#define MCHP_PECI_CTRL_PD_POS 0 +#define MCHP_PECI_CTRL_PD BIT(MCHP_PECI_CTRL_PD_POS) +#define MCHP_PECI_CTRL_RST_POS 3 +#define MCHP_PECI_CTRL_RST BIT(MCHP_PECI_CTRL_RST_POS) +#define MCHP_PECI_CTRL_FRST_POS 5 +#define MCHP_PECI_CTRL_FRST BIT(MCHP_PECI_CTRL_FRST_POS) +#define MCHP_PECI_CTRL_TXEN_POS 6 +#define MCHP_PECI_CTRL_TXEN BIT(MCHP_PECI_CTRL_TXEN_POS) +#define MCHP_PECI_CTRL_MIEN_POS 7 +#define MCHP_PECI_CTRL_MIEN BIT(MCHP_PECI_CTRL_MIEN_POS) + +/* Status 1 register. RW1C and read-only bits. */ +#define MCHP_PECI_STS1_REG_OFS 0x0Cu +#define MCHP_PECI_STS1_MASK 0xBFu +#define MCHP_PECI_STS1_BOF_POS 0 +#define MCHP_PECI_STS1_BOF BIT(MCHP_PECI_STS1_BOF_POS) +#define MCHP_PECI_STS1_EOF_POS 1 +#define MCHP_PECI_STS1_EOF BIT(MCHP_PECI_STS1_EOF_POS) +/* Error is read-only */ +#define MCHP_PECI_STS1_ERR_POS 2 +#define MCHP_PECI_STS1_ERR BIT(MCHP_PECI_STS1_ERR_POS) +/* Ready is read-only */ +#define MCHP_PECI_STS1_RDY_POS 3 +#define MCHP_PECI_STS1_RDY BIT(MCHP_PECI_STS1_RDY_POS) +#define MCHP_PECI_STS1_RDYLO_POS 4 +#define MCHP_PECI_STS1_RDYLO BIT(MCHP_PECI_STS1_RDYLO_POS) +#define MCHP_PECI_STS1_RDYHI_POS 5 +#define MCHP_PECI_STS1_RDYHI BIT(MCHP_PECI_STS1_RDYHI_POS) +/* MINT is read-only */ +#define MCHP_PECI_STS1_MINT_POS 7 +#define MCHP_PECI_STS1_MINT BIT(MCHP_PECI_STS1_MINT_POS) + +/* Status 2 register. Read-only bits. */ +#define MCHP_PECI_STS2_REG_OFS 0x10u +#define MCHP_PECI_STS2_MASK 0x8Fu +#define MCHP_PECI_STS2_WFF_POS 0 +#define MCHP_PECI_STS2_WFF BIT(MCHP_PECI_STS2_WFF_POS) +#define MCHP_PECI_STS2_WFE_POS 1 +#define MCHP_PECI_STS2_WFE BIT(MCHP_PECI_STS2_WFE_POS) +#define MCHP_PECI_STS2_RFF_POS 2 +#define MCHP_PECI_STS2_RFF BIT(MCHP_PECI_STS2_RFF_POS) +#define MCHP_PECI_STS2_RFE_POS 3 +#define MCHP_PECI_STS2_RFE BIT(MCHP_PECI_STS2_RFE_POS) +#define MCHP_PECI_STS2_IDLE_POS 7 +#define MCHP_PECI_STS2_IDLE BIT(MCHP_PECI_STS2_IDLE_POS) + +/* Error register. R/W1C bits. */ +#define MCHP_PECI_ERR_REG_OFS 0x14u +#define MCHP_PECI_ERR_MASK 0xF3u +#define MCHP_PECI_ERR_FERR_POS 0 +#define MCHP_PECI_ERR_FERR BIT(MCHP_PECI_ERR_FERR_POS) +#define MCHP_PECI_ERR_BERR_POS 1 +#define MCHP_PECI_ERR_BERR BIT(MCHP_PECI_ERR_BERR_POS) +#define MCHP_PECI_ERR_WROV_POS 4 +#define MCHP_PECI_ERR_WROV BIT(MCHP_PECI_ERR_WROV_POS) +#define MCHP_PECI_ERR_WRUN_POS 5 +#define MCHP_PECI_ERR_WRUN BIT(MCHP_PECI_ERR_WRUN_POS) +#define MCHP_PECI_ERR_RDOV_POS 6 +#define MCHP_PECI_ERR_RDOV BIT(MCHP_PECI_ERR_RDOV_POS) +#define MCHP_PECI_ERR_CLK_POS 7 +#define MCHP_PECI_ERR_CLK BIT(MCHP_PECI_ERR_CLK_POS) + +/* Interrupt Enable 1 register. */ +#define MCHP_PECI_IEN1_REG_OFS 0x18u +#define MCHP_PECI_IEN1_MASK 0x37u +#define MCHP_PECI_IEN1_BIEN_POS 0 +#define MCHP_PECI_IEN1_BIEN BIT(MCHP_PECI_IEN1_BIEN_POS) +#define MCHP_PECI_IEN1_EIEN_POS 1 +#define MCHP_PECI_IEN1_EIEN BIT(MCHP_PECI_IEN1_EIEN_POS) +#define MCHP_PECI_IEN1_EREN_POS 2 +#define MCHP_PECI_IEN1_EREN BIT(MCHP_PECI_IEN1_EREN_POS) +#define MCHP_PECI_IEN1_RLEN_POS 4 +#define MCHP_PECI_IEN1_RLEN BIT(MCHP_PECI_IEN1_RLEN_POS) +#define MCHP_PECI_IEN1_RHEN_POS 5 +#define MCHP_PECI_IEN1_RHEN BIT(MCHP_PECI_IEN1_RHEN_POS) + +/* Interrupt Enable 2 register. */ +#define MCHP_PECI_IEN2_REG_OFS 0x1Cu +#define MCHP_PECI_IEN2_MASK 0x06u +#define MCHP_PECI_IEN2_ENWFE_POS 1 +#define MCHP_PECI_IEN2_ENWFE BIT(MCHP_PECI_IEN2_ENWFE_POS) +#define MCHP_PECI_IEN2_ENRFF_POS 2 +#define MCHP_PECI_IEN2_ENRFF BIT(MCHP_PECI_IEN2_ENRFF_POS) + +/* Optimal Bit Time LSB register. */ +#define MCHP_PECI_OPT_BT_LSB_REG_OFS 0x20u +#define MCHP_PECI_OPT_BT_LSB_MASK 0xFFu + +/* Optimal Bit Time MSB register. */ +#define MCHP_PECI_OPT_BT_MSB_REG_OFS 0x24u +#define MCHP_PECI_OPT_BT_MSB_MASK 0xFFu + +#endif /* #ifndef _COMPONENT_PECI_H */ +/* end peci.h */ +/** @} + */ diff --git a/mec/mec172x/component/port92.h b/mec/mec172x/component/port92.h new file mode 100644 index 0000000..a10409f --- /dev/null +++ b/mec/mec172x/component/port92.h @@ -0,0 +1,81 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file port92.h + * MEC172x Fast Port92h Registers + */ +/** @defgroup MEC172x Peripherals Fast Port92 + */ + +#ifndef _COMPONENT_PORT92_H +#define _COMPONENT_PORT92_H + +#include +#include + +#include +#include + +#define MCHP_PORT92_BASE_ADDR 0x400F2000ul + +/* HOST_P92 */ +#define MCHP_PORT92_HOST_MASK 0x03ul +#define MCHP_PORT92_HOST_ALT_CPU_RST_POS 0u +#define MCHP_PORT92_HOST_ALT_CPU_RST BIT(0) +#define MCHP_PORT92_HOST_ALT_GA20_POS 1u +#define MCHP_PORT92_HOST_ALT_GA20 BIT(1) + +/* GATEA20_CTRL */ +#define MCHP_PORT92_GA20_CTRL_MASK 0x01ul +#define MCHP_PORT92_GA20_CTRL_VAL_POS 0u +#define MCHP_PORT92_GA20_CTRL_VAL_MASK BIT(0) +#define MCHP_PORT92_GA20_CTRL_VAL_HI BIT(0) +#define MCHP_PORT92_GA20_CTRL_VAL_LO 0ul + +/* + * SETGA20L - writes of any data to this register causes + * GATEA20 latch to be set. + */ +#define MCHP_PORT92_SETGA20L_MASK 0x01ul +#define MCHP_PORT92_SETGA20L_SET_POS 0u +#define MCHP_PORT92_SETGA20L_SET BIT(0) + +/* + * RSTGA20L - writes of any data to this register causes + * the GATEA20 latch to be reset + */ +#define MCHP_PORT92_RSTGA20L_MASK 0x01ul +#define MCHP_PORT92_RSTGA20L_SET_POS 0u +#define MCHP_PORT92_RSTGA20L_RST BIT(0) + +/* ACTV */ +#define MCHP_PORT92_ACTV_MASK 0x01ul +#define MCHP_PORT92_ACTV_ENABLE 0x01ul + +#endif /* #ifndef _COMPONENT_PORT92_H */ +/* end port92.h */ +/** @} + */ diff --git a/mec/mec172x/component/prochot.h b/mec/mec172x/component/prochot.h new file mode 100644 index 0000000..719bd27 --- /dev/null +++ b/mec/mec172x/component/prochot.h @@ -0,0 +1,98 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file prochot.h + * MEC172x Processor temperature control registers + */ +/** @defgroup MEC172x Peripherals PROCHOT + */ + +#ifndef _COMPONENT_PROCHOT_H +#define _COMPONENT_PROCHOT_H + +#include +#include + +#include +#include + +#define MCHP_PROCHOT_BASE_ADDR 0x40003400ul + +/* PROCHOT interrupt signal */ +#define MCHP_PROCHOT_GIRQ 17u +/* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ +#define MCHP_PROCHOT_GIRQ_POS 17 +#define MCHP_PROCHOT_GIRQ_VAL BIT(MCHP_PROCHOT_GIRQ_POS) + +/* PROCHOT GIRQ aggregated NVIC input */ +#define MCHP_PROCHOT_NVIC_AGGR 9u +/* PROCHOT direct NVIC inputs */ +#define MCHP_PROCHOT_NVIC_DIRECT 87u + +/* Cumulative Count register */ +#define MCHP_PROCHOT_CCNT_REG_OFS 0 +#define MCHP_PROCHOT_CCNT_REG_MASK 0x00fffffful + +/* Duty cycle count register */ +#define MCHP_PROCHOT_DCCNT_REG_OFS 4 +#define MCHP_PROCHOT_DCCNT_REG_MASK 0x00fffffful + +/* Duty cycle period register */ +#define MCHP_PROCHOT_DCPER_REG_OFS 8 +#define MCHP_PROCHOT_DCPER_REG_MASK 0x00fffffful + +/* Control and Status register */ +#define MCHP_PROCHOT_CTRLS_REG_OFS 0x0C +#define MCHP_PROCHOT_CTRLS_REG_MASK 0x00000C3Ful +#define MCHP_PROCHOT_CTRLS_EN_POS 0 +#define MCHP_PROCHOT_CTRLS_EN BIT(MCHP_PROCHOT_CTRLS_EN_POS) +#define MCHP_PROCHOT_CTRLS_PIN_POS 1 +#define MCHP_PROCHOT_CTRLS_PIN_HI BIT(MCHP_PROCHOT_CTRLS_PIN_POS) +#define MCHP_PROCHOT_CTRLS_ASSERT_EN_POS 2 +#define MCHP_PROCHOT_CTRLS_ASSERT_EN \ + BIT(MCHP_PROCHOT_CTRLS_ASSERT_EN_POS) +#define MCHP_PROCHOT_CTRLS_PERIOD_EN_POS 3 +#define MCHP_PROCHOT_CTRLS_PERIOD_EN \ + BIT(MCHP_PROCHOT_CTRLS_PERIOD_EN_POS) +#define MCHP_PROCHOT_CTRLS_RESET_EN_POS 4 +#define MCHP_PROCHOT_CTRLS_RESET_EN \ + BIT(MCHP_PROCHOT_CTRLS_RESET_EN_POS) +#define MCHP_PROCHOT_CTRLS_FILT_EN_POS 5 +#define MCHP_PROCHOT_CTRLS_FILT_EN \ + BIT(MCHP_PROCHOT_CTRLS_FILT_EN_POS) + +/* Assertion counter register */ +#define MCHP_PROCHOT_ASSERT_CNT_REG_OFS 0x10 +#define MCHP_PROCHOT_ASSERT_CNT_REG_MASK 0x0000fffful + +/* Assertion counter limit register */ +#define MCHP_PROCHOT_ASSERT_LIM_REG_OFS 0x14 +#define MCHP_PROCHOT_ASSERT_LIM_REG_MASK 0x0000fffful + +#endif /* #ifndef _COMPONENT_PROCHOT_H */ +/* end prochot.h */ +/** @} + */ diff --git a/mec/mec172x/component/ps2_ctrl.h b/mec/mec172x/component/ps2_ctrl.h new file mode 100644 index 0000000..9cc5385 --- /dev/null +++ b/mec/mec172x/component/ps2_ctrl.h @@ -0,0 +1,141 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file ps2_ctrl.h + * MEC172x PS/2 Controller Registers + */ +/** @defgroup MEC172x Peripherals PS/2 + */ + +#ifndef _COMPONENT_PS2_CTRL_H +#define _COMPONENT_PS2_CTRL_H + +#include +#include + +#include +#include + +#define MCHP_PS2_0_BASE_ADDR 0x40009000ul + +/* PS2 interrupts */ +#define MCHP_PS2_0_GIRQ 18u +#define MCHP_PS2_0_GIRQ_NVIC 10u +#define MCHP_PS2_0_NVIC_DIRECT 100u + +#define MCHP_PS2_0_GIRQ_POS 10u +#define MCHP_PS2_0_GIRQ_VAL BIT(10) + +/* PS2 wake on port activity interrupts */ +#define MCHP_PS2_0_WK_GIRQ 21u +#define MCHP_PS2_0_0A_WK_GIRQ_VAL BIT(18) +#define MCHP_PS2_0_0B_WK_GIRQ_VAL BIT(19) + +/* + * PS2 TRX Buffer register + * Writes -> Transmit buffer + * Read <- Receive buffer + */ +#define MCHP_PS2_TRX_BUFF_REG_MASK 0xFFUL + +/* + * PS2 Control register + */ +#define MCHP_PS2_CTRL_REG_MASK 0x3FUL + +/* Select Transmit or Receive */ +#define MCHP_PS2_CTRL_TR_POS 0 +#define MCHP_PS2_CTRL_TR_RX 0U +#define MCHP_PS2_CTRL_TR_TX BIT(MCHP_PS2_CTRL_TR_POS) + +/* Enable PS2 state machine */ +#define MCHP_PS2_CTRL_EN_POS 1 +#define MCHP_PS2_CTRL_EN BIT(MCHP_PS2_CTRL_EN_POS) + +/* Protocol parity selection */ +#define MCHP_PS2_CTRL_PAR_POS 2 +#define MCHP_PS2_CTRL_PAR_MASK0 0x03U +#define MCHP_PS2_CTRL_PAR_MASK 0x0CU +#define MCHP_PS2_CTRL_PAR_ODD 0U +#define MCHP_PS2_CTRL_PAR_EVEN 0x04U +#define MCHP_PS2_CTRL_PAR_IGNORE 0x08U +#define MCHP_PS2_CTRL_PAR_RSVD 0x0CU + +/* Protocol stop bit selection */ +#define MCHP_PS2_CTRL_STOP_POS 4 +#define MCHP_PS2_CTRL_STOP_MASK0 0x03U +#define MCHP_PS2_CTRL_STOP_MASK 0x30U +#define MCHP_PS2_CTRL_STOP_ACT_HI 0U +#define MCHP_PS2_CTRL_STOP_ACT_LO 0x10U +#define MCHP_PS2_CTRL_STOP_IGNORE 0x20U +#define MCHP_PS2_CTRL_STOP_RSVD 0x30U + +/* PS2 Status register */ +#define MCHP_PS2_STATUS_REG_MASK 0xFFUL +#define MCHP_PS2_STATUS_RW1C_MASK 0xAEUL +#define MCHP_PS2_STATUS_RO_MASK 0x51UL +/* RX Data Ready(Read-Only) */ +#define MCHP_PS2_STATUS_RXD_RDY_POS 0 +#define MCHP_PS2_STATUS_RXD_RDY BIT(MCHP_PS2_STATUS_RXD_RDY_POS) +/* RX Timeout(R/W1C) */ +#define MCHP_PS2_STATUS_RX_TMOUT_POS 1 +#define MCHP_PS2_STATUS_RX_TMOUT BIT(MCHP_PS2_STATUS_RX_TMOUT_POS) +/* Parity Error(R/W1C) */ +#define MCHP_PS2_STATUS_PE_POS 2 +#define MCHP_PS2_STATUS_PE BIT(MCHP_PS2_STATUS_PE_POS) +/* Framing Error(R/W1C) */ +#define MCHP_PS2_STATUS_FE_POS 3 +#define MCHP_PS2_STATUS_FE BIT(MCHP_PS2_STATUS_FE_POS) +/* Transmitter is Idle(Read-Only) */ +#define MCHP_PS2_STATUS_TX_IDLE_POS 4 +#define MCHP_PS2_STATUS_TX_IDLE BIT(MCHP_PS2_STATUS_TX_IDLE_POS) +/* Transmitter timeout(R/W1C) */ +#define MCHP_PS2_STATUS_TX_TMOUT_POS 5 +#define MCHP_PS2_STATUS_TX_TMOUT BIT(MCHP_PS2_STATUS_TX_TMOUT_POS) +/* RX is Busy(Read-Only) */ +#define MCHP_PS2_STATUS_RX_BUSY_POS 6 +#define MCHP_PS2_STATUS_RX_BUSY BIT(MCHP_PS2_STATUS_RX_BUSY_POS) +/* Transmitter start timeout(R/W1C) */ +#define MCHP_PS2_STATUS_TX_ST_TMOUT_POS 7 +#define MCHP_PS2_STATUS_TX_ST_TMOUT BIT(MCHP_PS2_STATUS_TX_ST_TMOUT_POS) + +/* PS2 Protocol bit positions */ +#define MCHP_PS2_PROT_START_BIT_POS 1 +#define MCHP_PS2_PROT_DATA_BIT0_POS 2 +#define MCHP_PS2_PROT_DATA_BIT1_POS 3 +#define MCHP_PS2_PROT_DATA_BIT2_POS 4 +#define MCHP_PS2_PROT_DATA_BIT3_POS 5 +#define MCHP_PS2_PROT_DATA_BIT4_POS 6 +#define MCHP_PS2_PROT_DATA_BIT5_POS 7 +#define MCHP_PS2_PROT_DATA_BIT6_POS 8 +#define MCHP_PS2_PROT_DATA_BIT7_POS 9 +#define MCHP_PS2_PROT_PARITY_POS 10 +#define MCHP_PS2_PROT_STOP_BIT_POS 11 + +#endif /* #ifndef _COMPONENT_PS2_CTRL_H */ +/* end ps2_ctrl.h */ +/** @} + */ diff --git a/mec/mec172x/component/pwm.h b/mec/mec172x/component/pwm.h new file mode 100644 index 0000000..3be7316 --- /dev/null +++ b/mec/mec172x/component/pwm.h @@ -0,0 +1,121 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file pwm.h + * MEC172x Pulse width modulator controller registers + */ +/** @defgroup MEC172x Peripherals PWM + */ + +#ifndef _COMPONENT_PWM_H +#define _COMPONENT_PWM_H + +#include +#include + +#include +#include + +#define MCHP_PWM_BASE_ADDR 0x40005800ul + +#define MCHP_PWM_INST_SPACING 0x10ul +#define MCHP_PWM_INST_SPACING_P2 4u + +#define MCHP_PWM_ADDR(n) (MCHP_PWM_BASE_ADDR + \ + ((uint32_t)(n) * MCHP_PWM_INST_SPACING)) + +/* !!!! PWM does not generate interrupts. !!!! */ + +/* PWM Count On register */ +#define MCHP_PWM_COUNT_ON_REG_OFS 0U +#define MCHP_PWM_COUNT_ON_MASK 0xffffU + +/* PWM Count Off register */ +#define MCHP_PWM_COUNT_OFF_REG_OFS 4U +#define MCHP_PWM_COUNT_OFF_MASK 0xffffU + +/* PWM Configuration Register */ +#define MCHP_PWM_CONFIG_REG_OFS 8U +#define MCHP_PWM_CONFIG_MASK 0x7FU +/* + * Enable and start PWM. Clearing this bit resets internal counters. + * COUNT_ON and COUNT_OFF registers are not affected by enable bit. + */ +#define MCHP_PWM_CFG_ENABLE_POS 0 +#define MCHP_PWM_CFG_ENABLE BIT(MCHP_PWM_CFG_ENABLE_POS) +/* Clock select */ +#define MCHP_PWM_CFG_CLK_SEL_POS 1 +#define MCHP_PWM_CFG_CLK_SEL_48M 0U +#define MCHP_PWM_CFG_CLK_SEL_100K BIT(MCHP_PWM_CFG_CLK_SEL_POS) +/* + * ON state polarity. + * Default ON state is High. + */ +#define MCHP_PWM_CFG_ON_POL_POS 2 +#define MCHP_PWM_CFG_ON_POL_HI 0U +#define MCHP_PWM_CFG_ON_POL_LO BIT(MCHP_PWM_CFG_ON_POL_POS) +/* + * Clock pre-divider + * Clock divider value = pre-divider + 1 + */ +#define MCHP_PWM_CFG_CLK_PRE_DIV_POS 3 +#define MCHP_PWM_CFG_CLK_PRE_DIV_MASK0 0x0FU +#define MCHP_PWM_CFG_CLK_PRE_DIV_MASK \ + SHLU32(0x0Fu, MCHP_PWM_CFG_CLK_PRE_DIV_POS) + +#define MCHP_PWM_CFG_CLK_PRE_DIV(n) \ + SHLU32((n) & MCHP_PWM_CFG_CLK_PRE_DIV_MASK0, \ + MCHP_PWM_CFG_CLK_PRE_DIV_POS) + +/* PWM input frequencies selected in configuration register. */ +#define MCHP_PWM_INPUT_FREQ_HI 48000000U +#define MCHP_PWM_INPUT_FREQ_LO 100000U + +/* + * Register access + * 0 <= n < MCHP_PWM_INSTANCES + */ +#define MCHP_PWM_COUNT_ON(n) \ + REG16(MCHP_PWM_ADDR(n) + MCHP_PWM_COUNT_ON_REG_OFS) + +#define MCHP_PWM_COUNT_OFF(n) \ + REG16(MCHP_PWM_ADDR(n) + MCHP_PWM_COUNT_OFF_REG_OFS) + +#define MCHP_PWM_CONFIG(n) \ + REG8(MCHP_PWM_ADDR(n) + MCHP_PWM_CONFIG_REG_OFS) + +/* + * PWM Frequency = + * (1 / (pre_div + 1)) * PWM_INPUT_FREQ / ((COUNT_ON+1) + (COUNT_OFF+1)) + * + * PWM Duty Cycle = + * (COUNT_ON+1) / ((COUNT_ON+1) + (COUNT_OFF + 1)) + */ + +#endif /* #ifndef _COMPONENT_PWM_H */ +/* end pwm.h */ +/** @} + */ diff --git a/mec/mec172x/component/qmspi.h b/mec/mec172x/component/qmspi.h new file mode 100644 index 0000000..57b278f --- /dev/null +++ b/mec/mec172x/component/qmspi.h @@ -0,0 +1,501 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file qmspi.h + * MEC172x Quad SPI Controller with Local DMA Registers + */ +/** @defgroup MEC172x Peripherals QMSPI + */ + +#ifndef _COMPONENT_QMSPI_H_ +#define _COMPONENT_QMSPI_H_ + +#include +#include + +#include +#include + +#define QMPSPI_HW_VER 4u + +#define MCHP_QMSPI_BASE_ADDR 0x40070000ul + +#define MCHP_QMSPI_MAX_DESCR 16ul + +#define MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ 96000000ul +#define MCHP_QMSPI_MAX_FREQ_KHZ \ + ((MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ) / 1000ul) +#define MCHP_QMSPI_MIN_FREQ_KHZ (MCHP_QMSPI_MAX_FREQ_KHZ / 256ul) + +#define MCHP_QMSPI_GIRQ_NUM 18u +#define MCHP_QMSPI_GIRQ_POS 1u +#define MCHP_QMSPI_GIRQ_VAL BIT(MCHP_QMSPI_GIRQ_POS) +#define MCHP_QMSPI_GIRQ_OFS (((MCHP_QMSPI0_GIRQ_NUM) -8) * 20u) + +#define MCHP_QMSPI_GIRQ_NVIC_AGGR 10u +#define MCHP_QMSPI_GIRQ_NVIC_DIRECT 91u + +#define MCHP_QMSPI_GIRQ_EN BIT(MCHP_QMSPI_GIRQ_POS) +#define MCHP_QMSPI_GIRQ_STS BIT(MCHP_QMSPI_GIRQ_POS) + +/* Mode 0: Clock idle = Low. Data change falling edge, sample rising edge */ +#define MCHP_QMSPI_SPI_MODE0 0ul +/* Mode 1: Clock idle = Low. Data change rising edge, sample falling edge */ +#define MCHP_QMSPI_SPI_MODE1 0x06ul +/* Mode 2: Clock idle = High. Data change rising edge, sample falling edge */ +#define MCHP_QMSPI_SPI_MODE2 0x06ul +/* Mode 3: Clock idle = High. Data change falling edge, sample rising edge */ +#define MCHP_QMSPI_SPI_MODE3 0x07ul + +/* Device ID used in DMA channel Control.DeviceID field */ +#define MCHP_QMSPI_TX_DMA_REQ_ID 10ul +#define MCHP_QMSPI_RX_DMA_REQ_ID 11ul + +/* QMSPI transmit and receive FIFO lengths */ +#define MCHP_QMSPI_TX_FIFO_LEN 8ul +#define MCHP_QMSPI_RX_FIFO_LEN 8ul + +/* QMSPI Local DMA channels */ +#define MCHP_QMSPI_LDMA_RX_CHANNELS 3U +#define MCHP_QMSPI_LDMA_TX_CHANNELS 3U + +#define MCHP_QMSPI_M_ACT_SRST_OFS 0ul +#define MCHP_QMSPI_M_SPI_MODE_OFS 1ul +#define MCHP_QMSPI_M_CLK_DIV_OFS 2ul +#define MCHP_QMSPI_CTRL_OFS 4ul +#define MCHP_QMSPI_EXE_OFS 8ul +#define MCHP_QMSPI_IF_CTRL_OFS 0x0Cul +#define MCHP_QMSPI_STS_OFS 0x10ul +#define MCHP_QMSPI_BUF_CNT_STS_OFS 0x14ul +#define MCHP_QMSPI_IEN_OFS 0x18ul +#define MCHP_QMSPI_BUF_CNT_TRIG_OFS 0x1Cul +#define MCHP_QMSPI_TX_FIFO_OFS 0x20ul +#define MCHP_QMSPI_RX_FIFO_OFS 0x24ul +#define MCHP_QMSPI_CSTM_OFS 0x28ul +/* 0 <= n < MCHP_QMSPI_MAX_DESCR */ +#define MCHP_QMSPI_DESC0_OFS 0x30ul +#define MCHP_QMSPI_DESCR_OFS(n) (0x30ul + ((uint32_t)(n) * 4U)) +#define MCHP_QMSPI_ALIAS_CTRL_OFS 0xB0ul +#define MCHP_QMSPI_MODE_ALT1_OFS 0xC0ul +#define MCHP_QMSPI_TAPS_OFS 0xD0ul +#define MCHP_QMSPI_TAPS_ADJ_OFS 0xD4ul +#define MCHP_QMSPI_TAPS_CTRL_OFS 0xD8ul +#define MCHP_QMSPI_LDMA_RX_EN_OFS 0x100ul +#define MCHP_QMSPI_LDMA_TX_EN_OFS 0x104ul +#define MCHP_QMSPI_LDMA_RX_0_CTRL_OFS 0x110ul +#define MCHP_QMSPI_LDMA_RX_0_START_OFS 0x114ul +#define MCHP_QMSPI_LDMA_RX_0_LEN_OFS 0x118ul +#define MCHP_QMSPI_LDMA_RX_1_CTRL_OFS 0x120ul +#define MCHP_QMSPI_LDMA_RX_1_START_OFS 0x124ul +#define MCHP_QMSPI_LDMA_RX_1_LEN_OFS 0x128ul +#define MCHP_QMSPI_LDMA_RX_2_CTRL_OFS 0x130ul +#define MCHP_QMSPI_LDMA_RX_2_START_OFS 0x134ul +#define MCHP_QMSPI_LDMA_RX_2_LEN_OFS 0x138ul +#define MCHP_QMSPI_LDMA_TX_0_CTRL_OFS 0x140ul +#define MCHP_QMSPI_LDMA_TX_0_START_OFS 0x144ul +#define MCHP_QMSPI_LDMA_TX_0_LEN_OFS 0x148ul +#define MCHP_QMSPI_LDMA_TX_1_CTRL_OFS 0x150ul +#define MCHP_QMSPI_LDMA_TX_1_START_OFS 0x154ul +#define MCHP_QMSPI_LDMA_TX_1_LEN_OFS 0x158ul +#define MCHP_QMSPI_LDMA_TX_2_CTRL_OFS 0x160ul +#define MCHP_QMSPI_LDMA_TX_2_START_OFS 0x164ul +#define MCHP_QMSPI_LDMA_TX_2_LEN_OFS 0x168ul + +#define MCHP_QMSPI_MODE_ADDR (MCHP_QMSPI_BASE_ADDR + 0x00) +#define MCHP_QMSPI_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x04) +#define MCHP_QMSPI_EXE_ADDR (MCHP_QMSPI_BASE_ADDR + 0x08) +#define MCHP_QMSPI_IFC_ADDR (MCHP_QMSPI_BASE_ADDR + 0x0C) +#define MCHP_QMSPI_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x10) +#define MCHP_QMSPI_BUFCNT_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x14) +#define MCHP_QMSPI_TX_BCNT_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x14) +#define MCHP_QMSPI_RX_BCNT_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x16) +#define MCHP_QMSPI_IEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x18) +#define MCHP_QMSPI_TXB_ADDR (MCHP_QMSPI_BASE_ADDR + 0x20) +#define MCHP_QMSPI_RXB_ADDR (MCHP_QMSPI_BASE_ADDR + 0x24) +#define MCHP_QMSPI_CSTM_ADDR (MCHP_QMSPI_BASE_ADDR + 0x28) +#define MCHP_QMSPI_DESCR_ADDR(n) \ + (MCHP_QMSPI_BASE_ADDR + (0x30 + (((uint32_t)(n) & 0x0Ful) << 2))) + +#define MCHP_QMSPI_ALIAS_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0xB0ul) +#define MCHP_QMSPI_MODE_ALT1_ADDR (MCHP_QMSPI_BASE_ADDR + 0xC0ul) +#define MCHP_QMSPI_TAPS_ADDR (MCHP_QMSPI_BASE_ADDR + 0xD0ul) +#define MCHP_QMSPI_TAPS_ADJ_ADDR (MCHP_QMSPI_BASE_ADDR + 0xD4ul) +#define MCHP_QMSPI_TAPS_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0xD8ul) +#define MCHP_QMSPI_LDMA_RX_EN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x100ul) +#define MCHP_QMSPI_LDMA_TX_EN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x104ul) +#define MCHP_QMSPI_LDMA_RX_0_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x110ul) +#define MCHP_QMSPI_LDMA_RX_0_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x114ul) +#define MCHP_QMSPI_LDMA_RX_0_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x118ul) +#define MCHP_QMSPI_LDMA_RX_1_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x120ul) +#define MCHP_QMSPI_LDMA_RX_1_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x124ul) +#define MCHP_QMSPI_LDMA_RX_1_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x128ul) +#define MCHP_QMSPI_LDMA_RX_2_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x130ul) +#define MCHP_QMSPI_LDMA_RX_2_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x134ul) +#define MCHP_QMSPI_LDMA_RX_2_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x138ul) +#define MCHP_QMSPI_LDMA_TX_0_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x140ul) +#define MCHP_QMSPI_LDMA_TX_0_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x144ul) +#define MCHP_QMSPI_LDMA_TX_0_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x148ul) +#define MCHP_QMSPI_LDMA_TX_1_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x150ul) +#define MCHP_QMSPI_LDMA_TX_1_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x154ul) +#define MCHP_QMSPI_LDMA_TX_1_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x158ul) +#define MCHP_QMSPI_LDMA_TX_2_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x160ul) +#define MCHP_QMSPI_LDMA_TX_2_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x164ul) +#define MCHP_QMSPI_LDMA_TX_2_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x168ul) + +/* Mode Register */ +#define MCHP_QMSPI_M_MASK 0x00ff371Fu +#define MCHP_QMSPI_M_ACTIVATE BIT(0) +#define MCHP_QMSPI_M_SRST BIT(1) +#define MCHP_QMSPI_M_SAF_DMA_MODE_EN BIT(2) +#define MCHP_QMSPI_M_LDMA_RX_EN BIT(3) +#define MCHP_QMSPI_M_LDMA_TX_EN BIT(4) +#define MCHP_QMSPI_M_CPOL_POS 8u +#define MCHP_QMSPI_M_CPOL_CLK_IDLE_LO 0 +#define MCHP_QMSPI_M_CPOL_CLK_IDLE_HI BIT(8) + +#define MCHP_QMSPI_M_CPHA_MOSI_POS 9u +/* MOSI data changes on first clock edge of clock pulse */ +#define MCHP_QMSPI_M_CPHA_MOSI_CE1 (0ul << 9) +/* MOSI data changes on second clock edge of clock pulse */ +#define MCHP_QMSPI_M_CPHA_MOSI_CE2 BIT(9) + +#define MCHP_QMSPI_M_CPHA_MIS0_POS 10u +/* MISO data capture on first clock edge of clock pulse */ +#define MCHP_QMSPI_M_CPHA_MISO_CE1 0ul +/* MISO data capture on second clock edge of clock pulse */ +#define MCHP_QMSPI_M_CPHA_MISO_CE2 BIT(10) + +#define MCHP_QMSPI_M_SIG_POS 8u +#define MCHP_QMSPI_M_SIG_MASK0 0x07ul +#define MCHP_QMSPI_M_SIG_MASK 0x0700ul +#define MCHP_QMSPI_M_SIG_MODE0_VAL 0x00ul +#define MCHP_QMSPI_M_SIG_MODE1_VAL 0x06ul +#define MCHP_QMSPI_M_SIG_MODE2_VAL 0x01ul +#define MCHP_QMSPI_M_SIG_MODE3_VAL 0x07ul +#define MCHP_QMSPI_M_SIG_MODE0 0x00ul +#define MCHP_QMSPI_M_SIG_MODE1 SHLU32(0x06ul, MCHP_QMSPI_M_SIG_POS) +#define MCHP_QMSPI_M_SIG_MODE2 SHLU32(0x01ul, MCHP_QMSPI_M_SIG_POS) +#define MCHP_QMSPI_M_SIG_MODE3 SHLU32(0x07ul, MCHP_QMSPI_M_SIG_POS) +#define MCHP_QMSPI_M_CS_POS 12u +#define MCHP_QMSPI_M_CS_MASK0 0x03ul +#define MCHP_QMSPI_M_CS_MASK SHLU32(0x03ul, 12) +#define MCHP_QMSPI_M_CS0 SHLU32(0x00ul, 12) +#define MCHP_QMSPI_M_CS1 SHLU32(0x01ul, 12) +/* Two chip selects only 0 and 1 */ +#define MCHP_QMSPI_M_CS(n) \ + (((uint32_t)(n) & MCHP_QMSPI_M_CS_MASK0) << MCHP_QMSPI_M_CS_POS) +#define MCHP_QMSPI_M_FDIV_POS 16u +#define MCHP_QMSPI_M_FDIV_MASK0 0xFFul +#define MCHP_QMSPI_M_FDIV_MASK 0x00FF0000ul + +/* Control/Descriptors */ +#define MCHP_QMSPI_C_IFM_MASK 0x03ul +#define MCHP_QMSPI_C_IFM_1X 0x00ul +#define MCHP_QMSPI_C_IFM_2X 0x01ul +#define MCHP_QMSPI_C_IFM_4X 0x02ul +#define MCHP_QMSPI_C_TX_POS 2u +#define MCHP_QMSPI_C_TX_MASK SHLU32(0x03ul, MCHP_QMSPI_C_TX_POS) +#define MCHP_QMSPI_C_TX_DIS 0x00ul +#define MCHP_QMSPI_C_TX_DATA SHLU32(0x01ul, MCHP_QMSPI_C_TX_POS) +#define MCHP_QMSPI_C_TX_ZEROS SHLU32(0x02ul, MCHP_QMSPI_C_TX_POS) +#define MCHP_QMSPI_C_TX_ONES SHLU32(0x03ul, MCHP_QMSPI_C_TX_POS) +#define MCHP_QMSPI_C_TX_DMA_POS 4u +#define MCHP_QMSPI_C_TX_DMA_MASK SHLU32(0x03ul, MCHP_QMSPI_C_TX_DMA_POS) +#define MCHP_QMSPI_C_TX_DMA_DIS 0x00ul +#define MCHP_QMSPI_C_TX_DMA_1B SHLU32(0x01ul, MCHP_QMSPI_C_TX_DMA_POS) +#define MCHP_QMSPI_C_TX_DMA_2B SHLU32(0x02ul, MCHP_QMSPI_C_TX_DMA_POS) +#define MCHP_QMSPI_C_TX_DMA_4B SHLU32(0x03ul, MCHP_QMSPI_C_TX_DMA_POS) +#define MCHP_QMSPI_C_RX_POS 6u +#define MCHP_QMSPI_C_RX_DIS 0ul +#define MCHP_QMSPI_C_RX_EN BIT(MCHP_QMSPI_C_RX_POS) +#define MCHP_QMSPI_C_RX_DMA_POS 7u +#define MCHP_QMSPI_C_RX_DMA_MASK SHLU32(0x03ul, MCHP_QMSPI_C_RX_DMA_POS) +#define MCHP_QMSPI_C_RX_DMA_DIS 0x00ul +#define MCHP_QMSPI_C_RX_DMA_1B SHLU32(0x01ul, MCHP_QMSPI_C_RX_DMA_POS) +#define MCHP_QMSPI_C_RX_DMA_2B SHLU32(0x02ul, MCHP_QMSPI_C_RX_DMA_POS) +#define MCHP_QMSPI_C_RX_DMA_4B SHLU32(0x03ul, MCHP_QMSPI_C_RX_DMA_POS) +#define MCHP_QMSPI_C_CLOSE_POS 9u +#define MCHP_QMSPI_C_NO_CLOSE 0ul +#define MCHP_QMSPI_C_CLOSE BIT(MCHP_QMSPI_C_CLOSE_POS) +#define MCHP_QMSPI_C_XFR_UNITS_POS 10u +#define MCHP_QMSPI_C_XFR_UNITS_MASK SHLU32(0x03ul, MCHP_QMSPI_C_XFR_UNITS_POS) +#define MCHP_QMSPI_C_XFR_UNITS_BITS 0x00ul +#define MCHP_QMSPI_C_XFR_UNITS_1 SHLU32(0x01ul, MCHP_QMSPI_C_XFR_UNITS_POS) +#define MCHP_QMSPI_C_XFR_UNITS_4 SHLU32(0x02ul, MCHP_QMSPI_C_XFR_UNITS_POS) +#define MCHP_QMSPI_C_XFR_UNITS_16 SHLU32(0x03ul, MCHP_QMSPI_C_XFR_UNITS_POS) +#define MCHP_QMSPI_C_NEXT_DESCR_POS 12u +#define MCHP_QMSPI_C_NEXT_DESCR_MASK0 0x0Ful +#define MCHP_QMSPI_C_NEXT_DESCR_MASK 0xF000ul +#define MCHP_QMSPI_C_DESCR0 0ul +#define MCHP_QMSPI_C_DESCR1 0x1000ul +#define MCHP_QMSPI_C_DESCR2 0x2000ul +#define MCHP_QMSPI_C_DESCR3 0x3000ul +#define MCHP_QMSPI_C_DESCR4 0x4000ul +/* Control register start descriptor field */ +#define MCHP_QMSPI_C_DESCR(n) \ + SHLU32(((n) & 0xFu), MCHP_QMSPI_C_NEXT_DESCR_POS) +/* Descriptor registers next descriptor field */ +#define MCHP_QMSPI_C_NEXT_DESCR(n) \ + SHLU32(((n) & 0xFu), MCHP_QMSPI_C_NEXT_DESCR_POS) +/* Control register descriptor mode enable */ +#define MCHP_QMSPI_C_DESCR_EN_POS 16u +#define MCHP_QMSPI_C_DESCR_EN BIT(MCHP_QMSPI_C_DESCR_EN_POS) +/* Descriptor registers last descriptor flag */ +#define MCHP_QMSPI_C_DESCR_LAST BIT(MCHP_QMSPI_C_DESCR_EN_POS) +#define MCHP_QMSPI_C_MAX_UNITS 0x7FFFul +#define MCHP_QMSPI_C_MAX_UNITS_MASK 0x7FFFul +#define MCHP_QMSPI_C_XFR_NUNITS_POS 17u +#define MCHP_QMSPI_C_XFR_NUNITS_MASK0 0x7FFFul +#define MCHP_QMSPI_C_XFR_NUNITS_MASK 0xFFFE0000ul +#define MCHP_QMSPI_C_XFR_NUNITS(n) SHLU32((n), MCHP_QMSPI_C_XFR_NUNITS_POS) +#define MCHP_QMSPI_C_XFR_NUNITS_GET(descr) ((uint32_t)(descr) >> 17) + +/* Exe */ +#define MCHP_QMSPI_EXE_START 0x01ul +#define MCHP_QMSPI_EXE_STOP 0x02ul +#define MCHP_QMSPI_EXE_CLR_FIFOS 0x04ul + +/* Interface Control */ +#define MCHP_QMSPI_IFC_DFLT 0x00ul +#define MCHP_QMSPI_IFC_WP_OUT_HI BIT(0) +#define MCHP_QMSPI_IFC_WP_OUT_EN BIT(1) +#define MCHP_QMSPI_IFC_HOLD_OUT_HI BIT(2) +#define MCHP_QMSPI_IFC_HOLD_OUT_EN BIT(3) +#define MCHP_QMSPI_IFC_PD_ON_NS BIT(4) +#define MCHP_QMSPI_IFC_PU_ON_NS BIT(5) +#define MCHP_QMSPI_IFC_PD_ON_ND BIT(6) +#define MCHP_QMSPI_IFC_PU_ON_ND BIT(7) + +/* Status Register */ +#define MCHP_QMSPI_STS_REG_MASK 0x0F01FF1Ful +#define MCHP_QMSPI_STS_RO_MASK 0x0F013300ul +#define MCHP_QMSPI_STS_RW1C_MASK 0x0000CC1Ful +#define MCHP_QMSPI_STS_DONE BIT(0) +#define MCHP_QMSPI_STS_DMA_DONE BIT(1) +#define MCHP_QMSPI_STS_TXB_ERR BIT(2) +#define MCHP_QMSPI_STS_RXB_ERR BIT(3) +#define MCHP_QMSPI_STS_PROG_ERR BIT(4) +#define MCHP_QMSPI_STS_TXBF_RO BIT(8) +#define MCHP_QMSPI_STS_TXBE_RO BIT(9) +#define MCHP_QMSPI_STS_TXBR BIT(10) +#define MCHP_QMSPI_STS_TXBS BIT(11) +#define MCHP_QMSPI_STS_RXBF_RO BIT(12) +#define MCHP_QMSPI_STS_RXBE_RO BIT(13) +#define MCHP_QMSPI_STS_RXBR BIT(14) +#define MCHP_QMSPI_STS_RXBS BIT(15) +#define MCHP_QMSPI_STS_ACTIVE_RO BIT(16) +#define MCHP_QMSPI_STS_CD_POS 24u +#define MCHP_QMSPI_STS_CD_MASK0 0x0Ful +#define MCHP_QMSPI_STS_CD_MASK 0x0F000000ul + +/* Buffer Count Status (RO) */ +#define MCHP_QMSPI_TX_BUF_CNT_STS_POS 0u +#define MCHP_QMSPI_TX_BUF_CNT_STS_MASK 0xffffu +#define MCHP_QMSPI_RX_BUF_CNT_STS_POS 16u +#define MCHP_QMSPI_RX_BUF_CNT_STS_MASK 0xffff0000ul + +/* Interrupt Enable Register */ +#define MCHP_QMSPI_IEN_XFR_DONE BIT(0) +#define MCHP_QMSPI_IEN_DMA_DONE BIT(1) +#define MCHP_QMSPI_IEN_TXB_ERR BIT(2) +#define MCHP_QMSPI_IEN_RXB_ERR BIT(3) +#define MCHP_QMSPI_IEN_PROG_ERR BIT(4) +#define MCHP_QMSPI_IEN_TXB_FULL BIT(8) +#define MCHP_QMSPI_IEN_TXB_EMPTY BIT(9) +#define MCHP_QMSPI_IEN_TXB_REQ BIT(10) +#define MCHP_QMSPI_IEN_RXB_FULL BIT(12) +#define MCHP_QMSPI_IEN_RXB_EMPTY BIT(13) +#define MCHP_QMSPI_IEN_RXB_REQ BIT(14) + +/* Buffer Count Trigger (RW) */ +#define MCHP_QMSPI_TX_BUF_CNT_TRIG_POS 0u +#define MCHP_QMSPI_RX_BUF_CNT_TRIG_POS 16u + +/* Chip Select Timing (RW) */ +#define MCHP_QMSPI_CSTM_MASK 0xFF0F0F0Ful +#define MCHP_QMSPI_CSTM_DFLT 0x06060406ul +#define MCHP_QMSPI_DLY_CS_ON_CK_STR_POS 0u +#define MCHP_QMSPI_DLY_CS_ON_CK_STR_MASK 0x0Ful +#define MCHP_QMSPI_DLY_CK_STP_CS_OFF_POS 8u +#define MCHP_QMSPI_DLY_CK_STP_CS_OFF_MASK 0x0F00ul +#define MCHP_QMSPI_DLY_LST_DAT_HLD_POS 16u +#define MCHP_QMSPI_DLY_LST_DAT_HLD_MASK 0x0F0000ul +#define MCHP_QMSPI_DLY_CS_OFF_CS_ON_POS 24u +#define MCHP_QMSPI_DLY_CS_OFF_CS_ON_MASK 0x0F000000ul + +/* Alias Control (WO) */ +#define MCHP_QMSPI_ACTRL_MASK 0xffffff7ful +#define MCHP_QMSPI_ACTRL_ESTART BIT(0) +#define MCHP_QMSPI_ACTRL_CDE BIT(1) +#define MCHP_QMSPI_ACTRL_TXBW BIT(2) +#define MCHP_QMSPI_ACTRL_DLEN BIT(3) +#define MCHP_QMSPI_ACTRL_CS_POS 4 +#define MCHP_QMSPI_ACTRL_CS0 0ul +#define MCHP_QMSPI_ACTRL_CS1 0x10ul +#define MCHP_QMSPI_ACTRL_LDIA BIT(6) +#define MCHP_QMSPI_ACTRL_DBP_POS 8 +#define MCHP_QMSPI_ACTRL_DBP_0 0ul +#define MCHP_QMSPI_ACTRL_DBP_1 0x100ul +#define MCHP_QMSPI_ACTRL_DBP_N(n) SHLU32(((n) & 0xFu), 8) +#define MCHP_QMSPI_ACTRL_BSEL_POS 12 +#define MCHP_QMSPI_ACTRL_BSEL_MSK 0xf000ul +#define MCHP_QMSPI_ACTRL_DBLEN_POS 16 +#define MCHP_QMSPI_ACTRL_DBLEN_MSK 0xff0000ul +#define MCHP_QMSPI_ACTRL_TXB_DATA_POS 24 +#define MCHP_QMSPI_ACTRL_TXB_DATA_MSK 0xff000000ul + +/* Mode Alternate 1 (RW) */ +#define MCHP_QMSPI_MA1_MASK 0xffff0001ul +#define MCHP_QMSPI_MA1_CS1_CDIV_EN BIT(0) +#define MCHP_QMSPI_MA1_CS1_CDIV_POS 16 +#define MCHP_QMSPI_MA1_CS1_CDIV_MSK 0xffff0000ul + +/* TAPS select and TAPS Adjust registers */ +#define MCHP_QMSPI_TAPS_MASK 0xfffful +#define MCHP_QMSPI_TAPS_SCK_MASK 0xfful +#define MCHP_QMSPI_TAPS_CTL_MASK 0xff00ul + +/* TAPS Control register */ +#define MCHP_QMSPI_TCTRL_MASK 0x70107ul +#define MCHP_QMSPI_TCTRL_AUTO_MODE_MASK 0x03ul +#define MCHP_QMSPI_TCTRL_AM_OFF 0x00ul +#define MCHP_QMSPI_TCTRL_AM_ON 0x01ul +#define MCHP_QMSPI_TCTRL_AM_PERIODIC 0x02ul +#define MCHP_QMSPI_TCTRL_UPDATE_EN BIT(2) +#define MCHP_QMSPI_TCTRL_UPDATE_NOW BIT(8) +#define MCHP_QMSPI_TCTRL_MULT_POS 16 +#define MCHP_QMSPI_TCTRL_MULT_MSK 0x70000ul + +/* Local DMA RX Descriptor Enable bit map */ +/* Local DMA TX Descriptor Enable bit map */ +#define MCHP_QMSPI_LDMA_DESCR_EN_MASK 0xfffful +#define MCHP_QMSPI_LDMA_DESCR_EN(n) BIT((n) & 0xFu) + +/* Each Local DMA channel implements 4 32-bit registers. + * Channels are identical for RX and TX + * offset 0x00: Control + * offset 0x04: memory start address + * offset 0x08: transfer byte length + * offset 0x0c: reserved read-only 0 + */ + +/* LDMA Channel Control register */ +#define MCHP_QMSPI_LDC_MASK 0x7Ful +/* enable channel */ +#define MCHP_QMSPI_LDC_EN BIT(0) +/* re-enable channel upon done */ +#define MCHP_QMSPI_LDC_RS_EN BIT(1) +/* on restart put memory start address back to its original value */ +#define MCHP_QMSPI_LDC_RSA_EN BIT(2) +/* use channel length not length in descriptor */ +#define MCHP_QMSPI_LDC_UCHL_EN BIT(3) +/* LDMA unit(access) size: 1, 2, or 4 bytes */ +#define MCHP_QMSPI_LDC_ASZ_POS 4 +#define MCHP_QMSPI_LDC_ASZ_MSK 0x30ul +#define MCHP_QMSPI_LDC_ASZ_1 0x00ul +#define MCHP_QMSPI_LDC_ASZ_2 0x10ul +#define MCHP_QMSPI_LDC_ASZ_4 0x20ul +/* LDMA increment memory start address by access size */ +#define MCHP_QMSPI_LDC_INCR_EN BIT(6) + +/* LDMA Channel (memory) Start address register */ +#define MCHP_QMSPI_LDMS_MASK 0xfffffffful + +/* LDMA Channel Length register */ +#define MCHP_QMSPI_LDLEN_MASK 0xfffffffful + +/* ----------------------- Register Access ------------------------------ */ +#define MCHP_QMSPI_MODE() REG32(MCHP_QMSPI_MODE_ADDR) +#define MCHP_QMSPI_MODE_ACTRST() REG8(MCHP_QMSPI_MODE_ADDR) +#define MCHP_QMSPI_MODE_SIG() REG8(MCHP_QMSPI_MODE_ADDR + 1ul) +#define MCHP_QMSPI_MODE_FDIV() REG16(MCHP_QMSPI_MODE_ADDR + 2ul) + +/* Control register */ +#define MCHP_QMSPI_CTRL() REG32(MCHP_QMSPI_CTRL_ADDR) + +/* Execute register */ +#define MCHP_QMSPI_EXE() REG8(MCHP_QMSPI_EXE_ADDR) + +/* Interface Control register */ +#define MCHP_QMSPI_IFC() REG8(MCHP_QMSPI_IFC_ADDR) + +/* Status register */ +#define MCHP_QMSPI_STS() REG32(MCHP_QMSPI_STS_ADDR) + +/* Buffer Count Status register (read-only) */ +#define MCHP_QMSPI_BCNT_STS() REG32(MCHP_QMSPI_BUFCNT_STS_ADDR) +/* b[15:0] = TX buffer count */ +#define MCHP_QMSPI_BCNT_TX_STS() REG16(MCHP_QMSPI_BUFCNT_STS_ADDR) +/* b[31:15] = RX buffer count */ +#define MCHP_QMSPI_BCNT_RX_STS() REG16(MCHP_QMSPI_BUFCNT_STS_ADDR + 2ul) + +/* Interrupt Enable register */ +#define MCHP_QMSPI_IEN() REG32(MCHP_QMSPI_IEN_ADDR) + +/* TX FIFO write-only */ +#define MCHP_QMSPI_TXB_32() REG32(MCHP_QMSPI_TXB_ADDR) +#define MCHP_QMSPI_TXB_16() REG16(MCHP_QMSPI_TXB_ADDR) +#define MCHP_QMSPI_TXB_8() REG8(MCHP_QMSPI_TXB_ADDR) + +/* RX FIFO read-only */ +#define MCHP_QMSPI_RXB_32() REG32(MCHP_QMSPI_RXB_ADDR) +#define MCHP_QMSPI_RXB_16() REG16(MCHP_QMSPI_RXB_ADDR) +#define MCHP_QMSPI_RXB_8() REG8(MCHP_QMSPI_RXB_ADDR) + +/* Descriptor registers 0 <= id < MCHP_QMSPI_MAX_DESCR */ +#define MCHP_QMSPI_DESCR(id) REG32(MCHP_QMSPI_DESCR_ADDR(id)) + +#define MCHP_QMSPI_DESCR_NUNITS(id, nu) MCHP_QMSPI_DESCR(id) = \ + ((MCHP_QMSPI_DESCR(id) & ~(MCHP_QMSPI_C_XFR_NUNITS_MASK)) + \ + (((uint32_t)nu & MCHP_QMSPI_C_XFR_NUNITS_MASK0) \ + << MCHP_QMSPI_C_XFR_NUNITS_POS)) + +#define MCHP_QMSPI_ALIAS_CTRL() REG32(MCHP_QMSPI_ALIAS_CTRL_ADDR) +#define MCHP_QMSPI_MODE_ALT1() REG32(MCHP_QMSPI_MODE_ALT1_ADDR) +#define MCHP_QMSPI_TAPS() REG32(MCHP_QMSPI_TAPS_ADDR) +#define MCHP_QMSPI_TAPS_ADJ() REG32(MCHP_QMSPI_TAPS_ADJ_ADDR) +#define MCHP_QMSPI_TAPS_CTRL() REG32(MCHP_QMSPI_TAPS_CTRL_ADDR) +#define MCHP_QMSPI_LDMA_RX_EN() REG32(MCHP_QMSPI_LDMA_RX_EN_ADDR) +#define MCHP_QMSPI_LDMA_TX_EN() REG32(MCHP_QMSPI_LDMA_TX_EN_ADDR) + +#define MCHP_QMSPI_LDMA_RX_CTRL(n) \ + REG32(MCHP_QMSPI_LDMA_RX_0_CTRL_ADDR + ((n) * 0x10u)) +#define MCHP_QMSPI_LDMA_RX_START(n) \ + REG32(MCHP_QMSPI_LDMA_RX_0_START_ADDR + ((n) * 0x10u)) +#define MCHP_QMSPI_LDMA_RX_LEN(n) \ + REG32(MCHP_QMSPI_LDMA_RX_0_LEN_ADDR + ((n) * 0x10u)) + +#define MCHP_QMSPI_LDMA_TX_CTRL(n) \ + REG32(MCHP_QMSPI_LDMA_TX_0_CTRL_ADDR + ((n) * 0x10u)) +#define MCHP_QMSPI_LDMA_TX_START(n) \ + REG32(MCHP_QMSPI_LDMA_TX_0_START_ADDR + ((n) * 0x10u)) +#define MCHP_QMSPI_LDMA_TX_LEN(n) \ + REG32(MCHP_QMSPI_LDMA_TX_0_LEN_ADDR + ((n) * 0x10u)) + +#endif /* #ifndef _COMPONENT_QMSPI_H */ +/* end qmspi.h */ +/** @} + */ diff --git a/mec/mec172x/component/rcid.h b/mec/mec172x/component/rcid.h new file mode 100644 index 0000000..35b395e --- /dev/null +++ b/mec/mec172x/component/rcid.h @@ -0,0 +1,77 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file rcid.h + * MEC172x RC ID controller registers + */ +/** @defgroup MEC172x Peripherals RCID + */ + +#ifndef _COMPONENT_RCID_H +#define _COMPONENT_RCID_H + +#include +#include + +#include +#include + +#define MCHP_RCID_0_BASE_ADDR 0x40001400ul +#define MCHP_RCID_INST_SPACING 0x80ul + +#define MCHP_RCID_ADDR(n) (MCHP_RCID_0_BASE_ADDR + \ + ((uint32_t)(n) * MCHP_RCID_INST_SPACING)) + +#define MCHP_RCID_GIRQ(n) 17u +#define MCHP_RCID_NVIC_GIRQ(n) 9u +#define MCHP_RCID_POS(n) (10u + (uint32_t)(n)) +#define MCHP_RCID_NVIC(n) (80u + (uint32_t)(n)) +#define MCHP_RCID_GIRQ_VAL(n) BIT(n) + +/* RCID Control register at 0x00 */ +#define MCHP_RCID_CTRL_OFS 0x00u +#define MCHP_RCID_CTRL_MASK 0x03C7u +#define MCHP_RCID_CTRL_RO_MASK 0x0007u +#define MCHP_RCID_CTRL_RW_MASK 0x03C0u +#define MCHP_RCID_CTRL_DONE_RO BIT(0) +#define MCHP_RCID_CTRL_TC_RO BIT(1) +#define MCHP_RCID_CTRL_CY_ER_RO BIT(2) +#define MCHP_RCID_CTRL_START BIT(6) +#define MCHP_RCID_CTRL_EN BIT(7) +#define MCHP_RCID_CTRL_CKS_MSK 0x300u +#define MCHP_RCID_CTRL_CK_48M 0x000u +#define MCHP_RCID_CTRL_CK_24M 0x100u +#define MCHP_RCID_CTRL_CK_12M 0x200u +#define MCHP_RCID_CTRL_CK_6M 0x300u + +/* RCID Data register at 0x04 */ +#define MCHP_RCID_DATA_OFS 0x04u +#define MCHP_RCID_DATA_MASK 0xFFFFu + +#endif /* #ifndef _COMPONENT_RCID_H */ +/* end rcid.h */ +/** @} + */ diff --git a/mec/mec172x/component/rpmfan.h b/mec/mec172x/component/rpmfan.h new file mode 100644 index 0000000..9ba87f0 --- /dev/null +++ b/mec/mec172x/component/rpmfan.h @@ -0,0 +1,229 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file rpmfan.h + * MEC172x RPM to PWM Fan controller + */ +/** @defgroup MEC172x Peripherals RPMFAN + */ + +#ifndef _COMPONENT_RPMFAN_H +#define _COMPONENT_RPMFAN_H + +#include +#include + +#include +#include + +#define MCHP_RPMFAN_BASE_ADDR 0x4000A000ul +#define MCHP_RPMFAN_INST_SPACING 0x80ul +#define MCHP_RPMFAN_ADDR(n) \ + (MCHP_RPMFAN_BASE_ADDR + ((n) * MCHP_RPMFAN_INST_SPACING)) + +/* RPMFAN has two interrupt signals: Fail and Stall */ +#define MCHP_RPMFAN_0_GIRQ 17u +#define MCHP_RPMFAN_1_GIRQ 17u +#define MCHP_RPMFAN_0_GIRQ_NVIC 9u +#define MCHP_RPMFAN_1_GIRQ_NVIC 9u + +#define MCHP_RPMFAN_0_FAIL_GIRQ_POS 20u +#define MCHP_RPMFAN_0_STALL_GIRQ_POS 21u +#define MCHP_RPMFAN_1_FAIL_GIRQ_POS 22u +#define MCHP_RPMFAN_1_STALL_GIRQ_POS 23u + +#define MCHP_RPMFAN_0_FAIL_GIRQ BIT(20) +#define MCHP_RPMFAN_0_STALL_GIRQ BIT(21) +#define MCHP_RPMFAN_1_FAIL_GIRQ BIT(22) +#define MCHP_RPMFAN_1_STALL_GIRQ BIT(23) + +#define MCHP_RPMFAN_0_FAIL_NVIC 74u +#define MCHP_RPMFAN_0_STALL_NVIC 75u +#define MCHP_RPMFAN_1_FAIL_NVIC 76u +#define MCHP_RPMFAN_1_STALL_NVIC 77u + +/* Fan Setting register 16-bit */ +#define MCHP_RPMFAN_FS_OFS 0x00u +#define MCHP_RPMFAN_FS_MSK 0xFFC0u +#define MCHP_RPMFAN_FSO_POS 6 + +/* Fan Configuration register 16-bit */ +#define MCHP_RPMFAN_FC_OFS 0x02u +#define MCHP_RPMFAN_FC_MSK 0xFEFFu +#define MCHP_RPMFAN_FC_DFLT 0x1C3Du +#define MCHP_RPMFAN_FC_UPD_POS 0 +#define MCHP_RPMFAN_FC_UPD_MSK 0x07u +#define MCHP_RPMFAN_FC_UPD_100MS 0u +#define MCHP_RPMFAN_FC_UPD_200MS 0x01u +#define MCHP_RPMFAN_FC_UPD_300MS 0x02u +#define MCHP_RPMFAN_FC_UPD_400MS 0x03u +#define MCHP_RPMFAN_FC_UPD_500MS 0x04u +#define MCHP_RPMFAN_FC_UPD_800MS 0x05u +#define MCHP_RPMFAN_FC_UPD_1200MS 0x06u +#define MCHP_RPMFAN_FC_UPD_1600MS 0x07u +/* number of edges per rotation on TACH input */ +#define MCHP_RPMFAN_FC_NE_POS 3 +#define MCHP_RPMFAN_FC_NE_MSK 0x18u +#define MCHP_RPMFAN_FC_NE_MSK 0x18u +#define MCHP_RPMFAN_FC_NE_3 0u +#define MCHP_RPMFAN_FC_NE_4 0x08u +#define MCHP_RPMFAN_FC_NE_7 0x10u +#define MCHP_RPMFAN_FC_NE_9 0x18u +/* weight the TACH values */ +#define MCHP_RPMFAN_RNG_POS 5 +#define MCHP_RPMFAN_RNG_MSK 0x60u +#define MCHP_RPMFAN_RNG_500_1X 0u +#define MCHP_RPMFAN_RNG_1000_2X 0x20u +#define MCHP_RPMFAN_RNG_2000_4X 0x40u +#define MCHP_RPMFAN_RNG_4000_8X 0x60u +/* enable selected HW algorithm */ +#define MCHP_RPMFAN_ALGO_EN BIT(7) +/* PWM driver polarity */ +#define MCHP_RPMFAN_PWM_INV BIT(9) +/* HW algorithm error window adjust */ +#define MCHP_RPMFAN_ERR_RNG_POS 10 +#define MCHP_RPMFAN_ERR_RNG_MSK 0xC00u +#define MCHP_RPMFAN_ERR_RNG_0 0x00u +#define MCHP_RPMFAN_ERR_RNG_50 0x400u +#define MCHP_RPMFAN_ERR_RNG_100 0x800u +#define MCHP_RPMFAN_ERR_RNG_200 0xC00u +/* HW algorithm derivative options */ +#define MCHP_RPMFAN_DER_OPT_POS 12 +#define MCHP_RPMFAN_DER_OPT_MSK 0x3000u +#define MCHP_RPMFAN_DER_OPT_NONE 0x00u +#define MCHP_RPMFAN_DER_OPT_BASIC 0x1000u +#define MCHP_RPMFAN_DER_OPT_STEP 0x2000u +#define MCHP_RPMFAN_DER_OPT_BOTH 0x3000u +/* disable glitch filter on TACH input pin */ +#define MCHP_RPMFAN_DIS_GLITCH BIT(14) +/* enable ramp rate control in manual mode operation */ +#define MCHP_RPMFAN_EN_RRC BIT(15) + +/* PWM Divider register 8-bit */ +#define MCHP_RPMFAN_PWM_DIV_OFS 0x04u +#define MCHP_RPMFAN_PWM_DIV_MSK 0xffu +#define MCHP_RPMFAN_PWM_DIV_DFLT 0x01u + +/* Gain register 8-bit */ +#define MCHP_RPMFAN_GAIN_OFS 0x05u +#define MCHP_RPMFAN_GAIN_MSK 0x3Fu +#define MCHP_RPMFAN_GAIN_DFLT 0x2Au +#define MCHP_RPMFAN_GAINP_POS 0 +#define MCHP_RPMFAN_GAINP_MSK 0x03u +#define MCHP_RPMFAN_GAINP_1X 0x00u +#define MCHP_RPMFAN_GAINP_2X 0x01u +#define MCHP_RPMFAN_GAINP_4X 0x02u +#define MCHP_RPMFAN_GAINP_8X 0x03u +#define MCHP_RPMFAN_GAINI_POS 2 +#define MCHP_RPMFAN_GAINI_MSK 0x0Cu +#define MCHP_RPMFAN_GAINI_1X 0x00u +#define MCHP_RPMFAN_GAINI_2X 0x04u +#define MCHP_RPMFAN_GAINI_4X 0x08u +#define MCHP_RPMFAN_GAINI_8X 0x0Cu +#define MCHP_RPMFAN_GAIND_POS 4 +#define MCHP_RPMFAN_GAIND_MSK 0x30u +#define MCHP_RPMFAN_GAIND_1X 0x00u +#define MCHP_RPMFAN_GAIND_2X 0x10u +#define MCHP_RPMFAN_GAIND_4X 0x20u +#define MCHP_RPMFAN_GAIND_8X 0x30u + +/* Fan spin up register 8-bit */ +#define MCHP_RPMFAN_SU_OFS 0x06u +#define MCHP_RPMFAN_SU_MSK 0xffu +#define MCHP_RPMFAN_SU_DFLT 0x19u +#define MCHP_RPMFAN_SU_TIME_POS 0 +#define MCHP_RPMFAN_SU_TIME_MSK 0x03u +#define MCHP_RPMFAN_SU_TIME_250MS 0x00u +#define MCHP_RPMFAN_SU_TIME_500MS 0x01u +#define MCHP_RPMFAN_SU_TIME_1S 0x02u +#define MCHP_RPMFAN_SU_TIME_2S 0x03u +#define MCHP_RPMFAN_SU_LVL_POS 2 +#define MCHP_RPMFAN_SU_LVL_MSK 0x1Cu +#define MCHP_RPMFAN_SU_LVL_30P 0x00u +#define MCHP_RPMFAN_SU_LVL_35P 0x04u +#define MCHP_RPMFAN_SU_LVL_40P 0x08u +#define MCHP_RPMFAN_SU_LVL_45P 0x0Cu +#define MCHP_RPMFAN_SU_LVL_50P 0x10u +#define MCHP_RPMFAN_SU_LVL_55P 0x14u +#define MCHP_RPMFAN_SU_LVL_60P 0x18u +#define MCHP_RPMFAN_SU_LVL_66P 0x1Cu +#define MCHP_RPMFAN_SU_NOKICK BIT(5) +#define MCHP_RPMFAN_SU_DFC_POS 6 +#define MCHP_RPMFAN_SU_DFC_MSK 0xC0u +#define MCHP_RPMFAN_SU_DFC_DIS 0x00u +#define MCHP_RPMFAN_SU_DFC_16 0x40u +#define MCHP_RPMFAN_SU_DFC_32 0x80u +#define MCHP_RPMFAN_SU_DFC_64 0xC0u + +/* Fan step register 8-bit */ +#define MCHP_RPMFAN_FSTEP_OFS 0x07u +#define MCHP_RPMFAN_FSTEP_MSK 0xffu +#define MCHP_RPMFAN_FSTEP_DFLT 0x10u + +/* Fan minimum driver register 8-bit */ +#define MCHP_RPMFAN_MDRV_OFS 0x08u +#define MCHP_RPMFAN_MDRV_MSK 0xffu +#define MCHP_RPMFAN_MDRV_DFLT 0x66u + +/* Valid Tach Count register 8-bit */ +#define MCHP_RPMFAN_VTC_OFS 0x09u +#define MCHP_RPMFAN_VTC_MSK 0xffu +#define MCHP_RPMFAN_VTC_DFLT 0xF5u + +/* Fan drive fail band register 16-bit */ +#define MCHP_RPMFAN_FDFB_OFS 0x0Au +#define MCHP_RPMFAN_FDFB_MSK 0xFFF8u +#define MCHP_RPMFAN_FDFB_SHIFT 3 + +/* Tach target register 16-bit */ +#define MCHP_RPMFAN_TT_OFS 0x0Cu +#define MCHP_RPMFAN_TT_MSK 0xfff8u +#define MCHP_RPMFAN_TT_SHIFT 3 + +/* Tach reading register 16-bit */ +#define MCHP_RPMFAN_TR_OFS 0x0Eu +#define MCHP_RPMFAN_TR_MSK 0xfff8u +#define MCHP_RPMFAN_TR_SHIFT 3 + +/* PWM driver base frequency register 8-bit */ +#define MCHP_RPMFAN_PBF_OFS 0x10u +#define MCHP_RPMFAN_PBF_MSK 0x03u +#define MCHP_RPMFAN_PBF_26K 0x00u +#define MCHP_RPMFAN_PBF_23K 0x01u +#define MCHP_RPMFAN_PBF_4K 0x02u +#define MCHP_RPMFAN_PBF_2K 0x03u + +/* Fan status register 8-bit */ +#define MCHP_RPMFAN_FSTS_OFS 0x11u +#define MCHP_RPMFAN_FSTS_MSK 0x23u +#define MCHP_RPMFAN_FSTS_STALL BIT(0) +#define MCHP_RPMFAN_FSTS_SU_FAIL BIT(1) +#define MCHP_RPMFAN_FSTS_DRV_FAIL BIT(5) + +#endif /* #ifndef _COMPONENT_RPMFAN_H */ +/* end rpmfan.h */ +/** @} + */ diff --git a/mec/mec172x/component/rtc.h b/mec/mec172x/component/rtc.h new file mode 100644 index 0000000..8bddce6 --- /dev/null +++ b/mec/mec172x/component/rtc.h @@ -0,0 +1,147 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file rtc.h + * MEC172x Real Time Clock definitions + */ +/** @defgroup MEC172x Peripherals RTC + */ + +#ifndef _COMPONENT_RTC_H +#define _COMPONENT_RTC_H + +#include +#include + +#include +#include + +/* interrupt routing */ +#define MCHP_RTC_GIRQ 21u +#define MCHP_RTC_GIRQ_IDX 13u +#define MCHP_RTC_NVIC_AGGR 13u +#define MCHP_RTC_NVIC 119u +#define MCHP_RTC_ALARM_NVIC 120u +#define MCHP_RTC_GIRQ_POS 8u +#define MCHP_RTC_ALARM_GIRQ_POS 9u +#define MCHP_RTC_GIRQ_VAL BIT(MCHP_RTC_GIRQ_POS) +#define MCHP_RTC_ALARM_GIRQ_VAL BIT(MCHP_RTC_ALARM_GIRQ_POS) + +/* Hours register */ +#define MCHP_RTC_HOURS_REG_OFS 0x04u +#define MCHP_RTC_HOURS_MASK 0x7Fu +#define MCHP_RTC_HOURS_AM_PM_MASK 0x80u +#define MCHP_RTC_HOURS_PM 0x80u + +/* RegA */ +#define MCHP_RTC_REGA_REG_OFS 0x0Aul +#define MCHP_RTC_REGA_MASK 0xFFu +#define MCHP_RTC_REGA_RATE_SEL_POS 0 +#define MCHP_RTC_REGA_RATE_SEL_MASK0 0x0Fu +#define MCHP_RTC_REGA_RATE_SEL_MASK 0x0Fu +#define MCHP_RTC_REGA_RATE_NONE 0x00u +#define MCHP_RTC_REGA_RATE_3906250_NS 0x01u +#define MCHP_RTC_REGA_RATE_7812500_NS 0x02u +#define MCHP_RTC_REGA_RATE_122070_NS 0x03u +#define MCHP_RTC_REGA_RATE_244141_NS 0x04u +#define MCHP_RTC_REGA_RATE_488281_NS 0x05u +#define MCHP_RTC_REGA_RATE_976563_NS 0x06u +#define MCHP_RTC_REGA_RATE_1953125_NS 0x07u +#define MCHP_RTC_REGA_RATE_3906250_NS_ALT 0x08u +#define MCHP_RTC_REGA_RATE_7812500_NS_ALT 0x09u +#define MCHP_RTC_REGA_RATE_15625_US 0x0Au +#define MCHP_RTC_REGA_RATE_31250_US 0x0Bu +#define MCHP_RTC_REGA_RATE_62500_US 0x0Cu +#define MCHP_RTC_REGA_RATE_125000_US 0x0Du +#define MCHP_RTC_REGA_RATE_250000_US 0x0Du +#define MCHP_RTC_REGA_RATE_500000_US 0x0Du +#define MCHP_RTC_REGA_DIVC_SEL_POS 4 +#define MCHP_RTC_REGA_DIVC_SEL_MASK0 0x07u +#define MCHP_RTC_REGA_DIVC_SEL_MASK 0x70u +#define MCHP_RTC_REGA_DIVC_SEL_NORM 0x20u +#define MCHP_RTC_REGA_DIVC_SEL_HALT 0x30u +/* bit[7] is read-only status */ +#define MCHP_RTC_REGA_UPDATE_IN_PROGESS_POS 7 +#define MCHP_RTC_REGA_UPDATE_IN_PROGESS 0x80 + +/* RegB */ +#define MCHP_RTC_REGB_REG_OFS 0x0Bul +#define MCHP_RTC_REGB_MASK 0xF7u +#define MCHP_RTC_REGB_DS_EN 0x01u +#define MCHP_RTC_REGB_FMT_12H 0x00u +#define MCHP_RTC_REGB_FMT_24H 0x02u +#define MCHP_RTC_REGB_DATA_BCD 0x00u +#define MCHP_RTC_REGB_DATA_BIN 0x04u +#define MCHP_RTC_REGB_UPDATE_DONE_IEN 0x10u +#define MCHP_RTC_REGB_ALARM_IEN 0x20u +#define MCHP_RTC_REGB_PERIODIC_IEN 0x40u +#define MCHP_RTC_REGB_UPDATE_INHIBIT 0x80u + +/* RegC contains read-to-clear status */ +#define MCHP_RTC_REGC_REG_OFS 0x0Cul +#define MCHP_RTC_REGC_MASK 0xF0u +#define MCHP_RTC_REGC_UPDATE_DONE_STS 0x10u +#define MCHP_RTC_REGC_ALARM_STS 0x20u +#define MCHP_RTC_REGC_PERIODIC_STS 0x40u +#define MCHP_RTC_REGC_INT_REQ_STS 0x80u + +/* RegD */ +#define MCHP_RTC_REGD_REG_OFS 0x0Dul +#define MCHP_RTC_REGD_MASK 0x3Fu +#define MCHP_RTC_REGD_DATE_ALARM_MASK 0x3Fu + +/* Control */ +#define MCHP_RTC_CTRL_REG_OFS 0x10ul +#define MCHP_RTC_CTRL_MASK 0x0Fu +#define MCHP_RTC_CTRL_BLK_EN 0x01u +#define MCHP_RTC_CTRL_SRST 0x02u +#define MCHP_RTC_CTRL_RSVD2 0x04u +#define MCHP_RTC_CTRL_ALARM_EN 0x08u + +/* Daylight savings forward (DLSF) and backward (DLSB) registers */ +#define MCHP_RTC_DLSF_REG_OFS 0x18ul +#define MCHP_RTC_DLSB_REG_OFS 0x1Cul +#define MCHP_RTC_DLS_MASK 0xFF0707FFul +#define MCHP_RTC_DLS_MON_POS 0 +#define MCHP_RTC_DLS_MON_MASK 0xFFul +#define MCHP_RTC_DLS_DOFW_POS 8 +#define MCHP_RTC_DLS_DOFW_MASK (0x700ul << 8) +#define MCHP_RTC_DLS_WEEK_POS 16 +#define MCHP_RTC_DLS_WEEK_MASK 0x70000ul +#define MCHP_RTC_DLS_WEEK_1 SHLU32(1u, 16) +#define MCHP_RTC_DLS_WEEK_2 SHLU32(2u, 16) +#define MCHP_RTC_DLS_WEEK_3 SHLU32(3u, 16) +#define MCHP_RTC_DLS_WEEK_4 SHLU32(4u, 16) +#define MCHP_RTC_DLS_WEEK_LAST SHLU32(5u, 16) +#define MCHP_RTC_DLS_HOUR_POS 24 +#define MCHP_RTC_DLS_HOUR_MASK SHLU32(0x3Fu, 24) +#define MCHP_RTC_DLS_AM_PM_POS 31 +#define MCHP_RTC_DLS_PM BIT(31) + +#endif /* #ifndef _RTC_H */ +/* end rtc.h */ +/** @} + */ diff --git a/mec/mec172x/component/spi_periph.h b/mec/mec172x/component/spi_periph.h new file mode 100644 index 0000000..e47dfe7 --- /dev/null +++ b/mec/mec172x/component/spi_periph.h @@ -0,0 +1,310 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file spi_slave.h + * MEC172x SPI Peripheral controller registers + */ +/** @defgroup MEC172x Peripherals SPI Slave + */ + +#ifndef _COMPONENT_SPI_PERIPH_H +#define _COMPONENT_SPI_PERIPH_H + +#include +#include + +#include +#include + +#define MCHP_SPIP_BASE_ADDR 0x40007000ul + +/* SPIP interrupts */ +#define MCHP_SPIP_GIRQ 18u + +/* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ +#define MCHP_SPIP_GIRQ_POS 0u + +#define MCHP_SPIP_GIRQ_VAL BIT(MCHP_SPIP_GIRQ_POS) + +/* SPIP GIRQ aggregated NVIC input */ +#define MCHP_SPIP_NVIC_AGGR 10u + +/* SPIP direct NVIC inputs */ +#define MCHP_SPIP_NVIC_DIRECT 90u + +/* SPIP Configuration register */ +#define MCHP_SPIP_CFG_REG_OFS 0u +#define MCHP_SPIP_CFG_REG_MASK 0x00ff0301ul +#define MCHP_SPIP_CFG_SQ_SEL_POS 0 +#define MCHP_SPIP_CFG_SINGLE 0ul +#define MCHP_SPIP_CFG_QUAD BIT(0) +#define MCHP_SPIP_CFG_TAR_POS 8 +#define MCHP_SPIP_CFG_TAR_MASK0 0x03u +#define MCHP_SPIP_CFG_TAR_MASK 0x0300u +#define MCHP_SPIP_CFG_TAR_1 0x00u +#define MCHP_SPIP_CFG_TAR_2 0x0100ul +#define MCHP_SPIP_CFG_TAR_4 0x0200ul +#define MCHP_SPIP_CFG_TAR_8 0x0300ul +#define MCHP_SPIP_CFG_WTM_POS 16 +#define MCHP_SPIP_CFG_WTM_MASK0 0xffu +#define MCHP_SPIP_CFG_WTM_MASK 0xff0000ul + +/* SPIP Status register */ +#define MCHP_SPIP_STS_REG_OFS 4u +#define MCHP_SPIP_STS_REG_MASK 0x1FFFEF7Bul +#define MCHP_SPIP_SPI_STS_MWD BIT(0) +#define MCHP_SPIP_SPI_STS_MRD BIT(1) +#define MCHP_SPIP_SPI_STS_MWB BIT(3) +#define MCHP_SPIP_SPI_STS_MRB BIT(4) +#define MCHP_SPIP_SPI_STS_SRTB BIT(5) +#define MCHP_SPIP_SPI_STS_PHI_REQ BIT(6) +#define MCHP_SPIP_SPI_STS_RXFE BIT(8) +#define MCHP_SPIP_SPI_STS_RXFF BIT(9) +#define MCHP_SPIP_SPI_STS_TXFE BIT(10) +#define MCHP_SPIP_SPI_STS_TXFF BIT(11) +#define MCHP_SPIP_SPI_STS_SCCE BIT(13) +#define MCHP_SPIP_SPI_STS_OBF BIT(15) +#define MCHP_SPIP_SPI_STS_SPIMR BIT(16) +#define MCHP_SPIP_SPI_STS_RXF_RSTD BIT(17) +#define MCHP_SPIP_SPI_STS_TXF_RSTD BIT(18) +#define MCHP_SPIP_SPI_STS_LIM0 BIT(19) +#define MCHP_SPIP_SPI_STS_LIM1 BIT(20) +#define MCHP_SPIP_SPI_STS_ABERR BIT(21) +#define MCHP_SPIP_SPI_STS_UNDEF_CMD BIT(22) +#define MCHP_SPIP_SPI_STS_DVB BIT(23) +#define MCHP_SPIP_SPI_STS_RXF_SZ BIT(24) +#define MCHP_SPIP_SPI_STS_TXF_UNF BIT(25) +#define MCHP_SPIP_SPI_STS_TXF_OVF BIT(26) +#define MCHP_SPIP_SPI_STS_RXF_UNF BIT(27) +#define MCHP_SPIP_SPI_STS_RXF_OVF BIT(28) + +/* SPIP EC Status register */ +#define MCHP_SPIP_EC_STS_REG_OFS 8u +#define MCHP_SPIP_EC_STS_REG_MASK 0x1FFFEF7Bul +#define MCHP_SPIP_EC_STS_MWD BIT(0) +#define MCHP_SPIP_EC_STS_MRD BIT(1) +#define MCHP_SPIP_EC_STS_MWB BIT(3) +#define MCHP_SPIP_EC_STS_MRB BIT(4) +#define MCHP_SPIP_EC_STS_SRTB BIT(5) +#define MCHP_SPIP_EC_STS_PHI_REQ BIT(6) +#define MCHP_SPIP_EC_STS_RXFE BIT(8) +#define MCHP_SPIP_EC_STS_RXFF BIT(9) +#define MCHP_SPIP_EC_STS_TXFE BIT(10) +#define MCHP_SPIP_EC_STS_TXFF BIT(11) +#define MCHP_SPIP_EC_STS_SCCE BIT(13) +#define MCHP_SPIP_EC_STS_IBF BIT(14) +#define MCHP_SPIP_EC_STS_OBF BIT(15) +#define MCHP_SPIP_EC_STS_SPIMR BIT(16) +#define MCHP_SPIP_EC_STS_RXF_RSTD BIT(17) +#define MCHP_SPIP_EC_STS_TXF_RSTD BIT(18) +#define MCHP_SPIP_EC_STS_LIM0 BIT(19) +#define MCHP_SPIP_EC_STS_LIM1 BIT(20) +#define MCHP_SPIP_EC_STS_ABERR BIT(21) +#define MCHP_SPIP_EC_STS_UNDEF_CMD BIT(22) +#define MCHP_SPIP_EC_STS_DVB BIT(23) +#define MCHP_SPIP_EC_STS_RXF_SZ BIT(24) +#define MCHP_SPIP_EC_STS_TXF_UNF BIT(25) +#define MCHP_SPIP_EC_STS_TXF_OVF BIT(26) +#define MCHP_SPIP_EC_STS_RXF_UNF BIT(27) +#define MCHP_SPIP_EC_STS_RXF_OVF BIT(28) + +/* SPIP SPI Interrupt Enable register */ +#define MCHP_SPIP_SPI_IEN_REG_OFS 0x0Cu +#define MCHP_SPIP_SPI_IEN_REG_MASK 0x1FFFAF7Bul +#define MCHP_SPIP_SPI_IEN_MWD BIT(0) +#define MCHP_SPIP_SPI_IEN_MRD BIT(1) +#define MCHP_SPIP_SPI_IEN_MWB BIT(3) +#define MCHP_SPIP_SPI_IEN_MRB BIT(4) +#define MCHP_SPIP_SPI_IEN_SRTB BIT(5) +#define MCHP_SPIP_SPI_IEN_PHI_REQ BIT(6) +#define MCHP_SPIP_SPI_IEN_RXFE BIT(8) +#define MCHP_SPIP_SPI_IEN_RXFF BIT(9) +#define MCHP_SPIP_SPI_IEN_TXFE BIT(10) +#define MCHP_SPIP_SPI_IEN_TXFF BIT(11) +#define MCHP_SPIP_SPI_IEN_SCCE BIT(13) +#define MCHP_SPIP_SPI_IEN_OBF BIT(15) +#define MCHP_SPIP_SPI_IEN_SPIMR BIT(16) +#define MCHP_SPIP_SPI_IEN_RXF_RSTD BIT(17) +#define MCHP_SPIP_SPI_IEN_TXF_RSTD BIT(18) +#define MCHP_SPIP_SPI_IEN_LIM0 BIT(19) +#define MCHP_SPIP_SPI_IEN_LIM1 BIT(20) +#define MCHP_SPIP_SPI_IEN_ABERR BIT(21) +#define MCHP_SPIP_SPI_IEN_UNDEF_CMD BIT(22) +#define MCHP_SPIP_SPI_IEN_DVB BIT(23) +#define MCHP_SPIP_SPI_IEN_RXF_SZ BIT(24) +#define MCHP_SPIP_SPI_IEN_TXF_UNF BIT(25) +#define MCHP_SPIP_SPI_IEN_TXF_OVF BIT(26) +#define MCHP_SPIP_SPI_IEN_RXF_UNF BIT(27) +#define MCHP_SPIP_SPI_IEN_RXF_OVF BIT(28) + +/* SPIP EC Interrupt Enable register */ +#define MCHP_SPIP_EC_IEN_REG_OFS 0x10u +#define MCHP_SPIP_EC_IEN_REG_MASK 0x1FFFEF7Bul +#define MCHP_SPIP_EC_IEN_MWD BIT(0) +#define MCHP_SPIP_EC_IEN_MRD BIT(1) +#define MCHP_SPIP_EC_IEN_MWB BIT(3) +#define MCHP_SPIP_EC_IEN_MRB BIT(4) +#define MCHP_SPIP_EC_IEN_SRTB BIT(5) +#define MCHP_SPIP_EC_IEN_PHI_REQ BIT(6) +#define MCHP_SPIP_EC_IEN_RXFE BIT(8) +#define MCHP_SPIP_EC_IEN_RXFF BIT(9) +#define MCHP_SPIP_EC_IEN_TXFE BIT(10) +#define MCHP_SPIP_EC_IEN_TXFF BIT(11) +#define MCHP_SPIP_EC_IEN_SCCE BIT(13) +#define MCHP_SPIP_EC_IEN_IBF BIT(14) +#define MCHP_SPIP_EC_IEN_OBF BIT(15) +#define MCHP_SPIP_EC_IEN_SPIMR BIT(16) +#define MCHP_SPIP_EC_IEN_RXF_RSTD BIT(17) +#define MCHP_SPIP_EC_IEN_TXF_RSTD BIT(18) +#define MCHP_SPIP_EC_IEN_LIM0 BIT(19) +#define MCHP_SPIP_EC_IEN_LIM1 BIT(20) +#define MCHP_SPIP_EC_IEN_ABERR BIT(21) +#define MCHP_SPIP_EC_IEN_UNDEF_CMD BIT(22) +#define MCHP_SPIP_EC_IEN_DVB BIT(23) +#define MCHP_SPIP_EC_IEN_RXF_SZ BIT(24) +#define MCHP_SPIP_EC_IEN_TXF_UNF BIT(25) +#define MCHP_SPIP_EC_IEN_TXF_OVF BIT(26) +#define MCHP_SPIP_EC_IEN_RXF_UNF BIT(27) +#define MCHP_SPIP_EC_IEN_RXF_OVF BIT(28) + +/* SPIP Memory Config register */ +#define MCHP_SPIP_MCFG_REG_OFS 0x14u +#define MCHP_SPIP_MCFG_REG_MASK 0x03ul +#define MCHP_SPIP_MCFG_BAR0_EN_POS 0 +#define MCHP_SPIP_MCFG_BAR0_EN BIT(0) +#define MCHP_SPIP_MCFG_BAR1_EN_POS 1 +#define MCHP_SPIP_MCFG_BAR1_EN BIT(1) + +/* SPIP Memory Base Address 0 register */ +#define MCHP_SPIP_MBA0_REG_OFS 0x18u +#define MCHP_SPIP_MBA0_REG_MASK 0xFFFFFFFCul + +/* SPIP Memory Write Limit 0 register */ +#define MCHP_SPIP_MWLIM0_REG_OFS 0x1Cu +#define MCHP_SPIP_MWLIM0_REG_MASK 0xFFFFFFFCul + +/* SPIP Memory Read Limit 0 register */ +#define MCHP_SPIP_MRLIM0_REG_OFS 0x20u +#define MCHP_SPIP_MRLIM0_REG_MASK 0xFFFFFFFCul + +/* SPIP Memory Base Address 1 register */ +#define MCHP_SPIP_MBA1_REG_OFS 0x24u +#define MCHP_SPIP_MBA1_REG_MASK 0xFFFFFFFCul + +/* SPIP Memory Write Limit 1 register */ +#define MCHP_SPIP_MWLIM1_REG_OFS 0x28u +#define MCHP_SPIP_MWLIM1_REG_MASK 0xFFFFFFFCul + +/* SPIP Memory Read Limit 1 register */ +#define MCHP_SPIP_MRLIM1_REG_OFS 0x2Cu +#define MCHP_SPIP_MRLIM1_REG_MASK 0xFFFFFFFCul + +/* SPIP RX FIFO Host BAR register */ +#define MCHP_SPIP_RXFHB_REG_OFS 0x30u +#define MCHP_SPIP_RXFHB_REG_MASK 0xFFFFul + +/* SPIP RX FIFO Host BAR register */ +#define MCHP_SPIP_RXFBC_REG_OFS 0x34u +#define MCHP_SPIP_RXFBC_REG_MASK 0x7FFFul + +/* SPIP TX FIFO Host BAR register */ +#define MCHP_SPIP_TXFHB_REG_OFS 0x38u +#define MCHP_SPIP_TXFHB_REG_MASK 0xFFFFul + +/* SPIP TX FIFO Host BAR register */ +#define MCHP_SPIP_TXFBC_REG_OFS 0x3Cu +#define MCHP_SPIP_TXFBC_REG_MASK 0x7FFFul + +/* SPIP System Configuration register */ +#define MCHP_SPIP_SYSCFG_REG_OFS 0x40u +#define MCHP_SPIP_SYSCFG_REG_MASK 0x000F04FFul +#define MCHP_SPIP_SYSCFG_SRST BIT(0) +#define MCHP_SPIP_SYSCFG_LOCK_WM BIT(1) +#define MCHP_SPIP_SYSCFG_LOCK_TAR BIT(2) +#define MCHP_SPIP_SYSCFG_LOCK_WC BIT(3) +#define MCHP_SPIP_SYSCFG_LOCK_SPI_STS BIT(4) +#define MCHP_SPIP_SYSCFG_LOCK_SPI_IEN BIT(5) +#define MCHP_SPIP_SYSCFG_LOCK_MBA0 BIT(6) +#define MCHP_SPIP_SYSCFG_LOCK_MBA1 BIT(7) +#define MCHP_SPIP_SYSCFG_LOCK_TST BIT(10) +#define MCHP_SPIP_SYSCFG_LOCK_ALL 0x04FEul +#define MCHP_SPIP_SYSCFG_ACT BIT(16) +#define MCHP_SPIP_SYSCFG_MASK_EC BIT(17) +#define MCHP_SPIP_SYSCFG_SIMPLE_MODE BIT(18) +#define MCHP_SPIP_SYSCFG_ECDA BIT(19) + +/* SPIP SPI Master to EC Mailbox register */ +#define MCHP_SPIP_MB_S2EC_REG_OFS 0x44u +#define MCHP_SPIP_MB_S2EC_REG_MASK 0xFFFFFFFFul +#define MCHP_SPIP_MB_S2EC_CLR 0xFFFFFFFFul + +/* SPIP EC to SPI Master Mailbox register */ +#define MCHP_SPIP_MB_EC2S_REG_OFS 0x48u +#define MCHP_SPIP_MB_EC2S_REG_MASK 0xFFFFFFFFul +#define MCHP_SPIP_MB_EC2S_CLR 0xFFFFFFFFul + +/* SPI commands supported by SPIP */ +#define SPIP_CMD_IN_BAND_RST 0xFFu +#define SPIP_CMD_UNDEF_W32 0x01u +#define SPIP_CMD_UNDEF_W8 0x02u +#define SPIP_CMD_UNDEF_R32 0x05u +#define SPIP_CMD_UNDEF_R8 0x06u +#define SPIP_CMD_SREG_W8 0x09u +#define SPIP_CMD_SREG_W16 0x0Au +#define SPIP_CMD_SREG_W32 0x0Bu +#define SPIP_CMD_SREG_R8 0x0Du +#define SPIP_CMD_SREG_R16 0x0Eu +#define SPIP_CMD_SREG_R32 0x0Fu +#define SPIP_CMD_RST_RX_FIFO 0x12u +#define SPIP_CMD_RST_TX_FIFO 0x14u +#define SPIP_CMD_RST_RXTX_FIFO 0x16u +#define SPIP_CMD_MEM_W8 0x21u +#define SPIP_CMD_MEM_W16 0x22u +#define SPIP_CMD_MEM_W32 0x23u +#define SPIP_CMD_MEM_R8 0x25u +#define SPIP_CMD_MEM_R16 0x26u +#define SPIP_CMD_MEM_R32 0x27u +#define SPIP_CMD_RS_FIFO8 0x28u +#define SPIP_CMD_RS_FIFO16 0x29u +#define SPIP_CMD_RS_FIFO32 0x2Bu +#define SPIP_CMD_POLL_LO 0x2Cu +#define SPIP_CMD_POLL_HI 0x2Du +#define SPIP_CMD_POLL_ALL 0x2Fu +#define SPIP_CMD_EXT_REG_W8 0x41u +#define SPIP_CMD_EXT_REG_R8 0x45u +#define SPIP_CMD_RS_FIFO8_FSR 0x68u +#define SPIP_CMD_RS_FIFO16_FSR 0x69u +#define SPIP_CMD_RS_FIFO32_FSR 0x6Bu +#define SPIP_CMD_EXT_END 0x6Cu +#define SPIP_CMD_MBLK_W 0x80u +#define SPIP_CMD_MBLK_R 0xA0u +#define SPIP_CMD_RD_BLK_FIFO 0xC0u +#define SPIP_CMD_RD_BLK_FIFO_FSR 0xE0u + +#endif /* #ifndef _COMPONENT_SPI_PERIPH_H */ +/* end spi_periph.h */ +/** @} + */ diff --git a/mec/mec172x/component/tach.h b/mec/mec172x/component/tach.h new file mode 100644 index 0000000..70b5fab --- /dev/null +++ b/mec/mec172x/component/tach.h @@ -0,0 +1,149 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file tach.h + * MEC172x Tachometer registers + */ +/** @defgroup MEC172x Peripherals TACH + */ + +#ifndef _COMPONENT_TACH_H +#define _COMPONENT_TACH_H + +#include +#include + +#include +#include + +#define MCHP_TACH_BASE_ADDR 0x40006000ul + +#define MCHP_TACH_INST_SPACING 0x10ul +#define MCHP_TACH_INST_SPACING_P2 4u + +#define MCHP_TACH_ADDR(n) (MCHP_TACH_BASE_ADDR + \ + ((uint32_t)(n) * MCHP_TACH_INST_SPACING)) + +/* TACH interrupts */ +#define MCHP_TACH0_GIRQ 17u +#define MCHP_TACH1_GIRQ 17u +#define MCHP_TACH2_GIRQ 17u +#define MCHP_TACH3_GIRQ 17u + +/* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ +#define MCHP_TACH0_GIRQ_POS 1u +#define MCHP_TACH1_GIRQ_POS 2u +#define MCHP_TACH2_GIRQ_POS 3u +#define MCHP_TACH3_GIRQ_POS 4u + +#define MCHP_TACH0_GIRQ_VAL BIT(MCHP_TACH0_GIRQ_POS) +#define MCHP_TACH1_GIRQ_VAL BIT(MCHP_TACH1_GIRQ_POS) +#define MCHP_TACH2_GIRQ_VAL BIT(MCHP_TACH2_GIRQ_POS) +#define MCHP_TACH3_GIRQ_VAL BIT(MCHP_TACH3_GIRQ_POS) + +/* TACH GIRQ aggregated NVIC input */ +#define MCHP_TACH0_NVIC_AGGR 9u +#define MCHP_TACH1_NVIC_AGGR 9u +#define MCHP_TACH2_NVIC_AGGR 9u +#define MCHP_TACH3_NVIC_AGGR 9u + +/* TACH direct NVIC inputs */ +#define MCHP_TACH0_NVIC_DIRECT 71u +#define MCHP_TACH1_NVIC_DIRECT 72u +#define MCHP_TACH2_NVIC_DIRECT 73u +#define MCHP_TACH3_NVIC_DIRECT 159u + +/* TACH Control register */ +#define MCHP_TACH_CONTROL_REG_OFS 0U +#define MCHP_TACH_CONTROL_MASK 0xffffdd03U + +/* Enable exceed high or low limit detection */ +#define MCHP_TACH_CTRL_EXCEED_LIM_EN_POS 0 +#define MCHP_TACH_CTRL_EXCEED_LIM_EN BIT(0) + +/* Enable TACH operation */ +#define MCHP_TACH_CTRL_EN_POS 1 +#define MCHP_TACH_CTRL_EN BIT(MCHP_TACH_CTRL_EN_POS) + +/* Enable input filter */ +#define MCHP_TACH_CTRL_FILTER_EN_POS 8 +#define MCHP_TACH_CTRL_FILTER_EN BIT(MCHP_TACH_CTRL_FILTER_EN_POS) + +/* Select read mode. Latch data on rising edge of selected trigger */ +#define MCHP_TACH_CTRL_READ_MODE_SEL_POS 10 +#define MCHP_TACH_CTRL_READ_MODE_INPUT 0U +#define MCHP_TACH_CTRL_READ_MODE_100K_CLOCK BIT(10) + +/* Select TACH edges for counter increment */ +#define MCHP_TACH_CTRL_NUM_EDGES_POS 11 +#define MCHP_TACH_CTRL_NUM_EDGES_MASK0 0x03U +#define MCHP_TACH_CTRL_NUM_EDGES_MASK SHLU32(0x03U, 11) +#define MCHP_TACH_CTRL_EDGES_2 0U +#define MCHP_TACH_CTRL_EDGES_3 SHLU32(1u, 11) +#define MCHP_TACH_CTRL_EDGES_5 SHLU32(2u, 11) +#define MCHP_TACH_CTRL_EDGES_9 SHLU32(3u, 11) + +/* Enable count ready interrupt */ +#define MCHP_TACH_CTRL_CNT_RDY_INT_EN_POS 14 +#define MCHP_TACH_CTRL_CNT_RDY_INT_EN BIT(14) + +/* Enable input toggle interrupt */ +#define MCHP_TACH_CTRL_TOGGLE_INT_EN_POS 15 +#define MCHP_TACH_CTRL_TOGGLE_INT_EN BIT(15) + +/* Read-only latched TACH pulse counter */ +#define MCHP_TACH_CTRL_COUNTER_POS 16 +#define MCHP_TACH_CTRL_COUNTER_MASK0 0xfffful +#define MCHP_TACH_CTRL_COUNTER_MASK SHLU32(0xffffU, 16) + +/* + * TACH Status register + * bits[0, 2-3] are R/W1C + * bit[1] is Read-Only + */ +#define MCHP_TACH_STATUS_REG_OFS 4U +#define MCHP_TACH_STATUS_MASK 0x0FU +#define MCHP_TACH_STS_EXCEED_LIMIT_POS 0 +#define MCHP_TACH_STS_EXCEED_LIMIT BIT(MCHP_TACH_STS_EXCEED_LIMIT_POS) +#define MCHP_TACH_STS_PIN_STATE_POS 1 +#define MCHP_TACH_STS_PIN_STATE_HI BIT(MCHP_TACH_STS_PIN_STATE_POS) +#define MCHP_TACH_STS_TOGGLE_POS 2 +#define MCHP_TACH_STS_TOGGLE BIT(MCHP_TACH_STS_TOGGLE_POS) +#define MCHP_TACH_STS_CNT_RDY_POS 3 +#define MCHP_TACH_STS_CNT_RDY BIT(MCHP_TACH_STS_CNT_RDY_POS) + +/* TACH High Limit Register */ +#define MCHP_TACH_HI_LIMIT_REG_OFS 8U +#define MCHP_TACH_HI_LIMIT_MASK 0xffffU + +/* TACH Low Limit Register */ +#define MCHP_TACH_LO_LIMIT_REG_OFS 0x0CU +#define MCHP_TACH_LO_LIMIT_MASK 0xffffU + +#endif /* #ifndef _COMPONENT_TACH_H */ +/* end tach.h */ +/** @} + */ diff --git a/mec/mec172x/component/tfdp.h b/mec/mec172x/component/tfdp.h new file mode 100644 index 0000000..6cdb897 --- /dev/null +++ b/mec/mec172x/component/tfdp.h @@ -0,0 +1,76 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file tfdp.h + * MEC172x TFDP Trace FIFO Debug Port Registers + */ +/** @defgroup MEC172x Peripherals TFDP + */ + +#ifndef _COMPONENT_TFDP_H +#define _COMPONENT_TFDP_H + +#include +#include + +#include +#include + +#define MCHP_TFDP_BASE_ADDR 0x40008C00ul + +#define MCHP_TFDP_DATA_OUT_ADDR ((MCHP_TFDP_BASE_ADDR) +0) +#define MCHP_TFDP_CTRL_ADDR ((MCHP_TFDP_BASE_ADDR) +4ul) + +#define MCHP_TFDP_CTRL_REG_MASK 0x7Ful +#define MCHP_TFDP_CTRL_EN_POS 0u +#define MCHP_TFDP_CTRL_EDGE_SEL_POS 1u +#define MCHP_TFDP_CTRL_DIV_SEL_POS 2u +#define MCHP_TFDP_CTRL_IP_DLY_POS 4u + +#define MCHP_TFDP_CTRL_EN BIT(0) +#define MCHP_TFDP_OUT_ON_FALLING_EDGE BIT(1) +#define MCHP_TFDP_CLK_AHB_DIV_2 0U +#define MCHP_TFDP_CLK_AHB_DIV_4 0x04U +#define MCHP_TFDP_CLK_AHB_DIV_8 0x08U +#define MCHP_TFDP_CLK_AHB_DIV_2_ALT 0x0CU + +/* Number of AHB clocks between each byte shifted out */ +#define MCHP_TFDP_IP_DLY_1 0U +#define MCHP_TFDP_IP_DLY_2 0x10U +#define MCHP_TFDP_IP_DLY_3 0x20U +#define MCHP_TFDP_IP_DLY_4 0x30U +#define MCHP_TFDP_IP_DLY_5 0x40U +#define MCHP_TFDP_IP_DLY_6 0x50U +#define MCHP_TFDP_IP_DLY_7 0x60U +#define MCHP_TFDP_IP_DLY_8 0x70U + +/* First byte indicates start of packet */ +#define MCHP_TFDP_PKT_START 0xFDu + +#endif /* #ifndef _COMPONENT_TFDP_H */ +/* end tfdp.h */ +/** @} + */ diff --git a/mec/mec172x/component/timer.h b/mec/mec172x/component/timer.h new file mode 100644 index 0000000..f05ab04 --- /dev/null +++ b/mec/mec172x/component/timer.h @@ -0,0 +1,495 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file timer.h + * MEC172x Timer definitions + */ +/** @defgroup MEC172x Peripherals Timers + */ + +#ifndef _COMPONENT_TIMER_H +#define _COMPONENT_TIMER_H + +#include +#include + +#include +#include + +/* + * Basic timers base address + * Offset between each timer block + */ +#define MCHP_B16TMR_BASE 0x40000C00ul +#define MCHP_B16TMR_INSTANCES 4u +#define MCHP_B32TMR_BASE 0x40000C80ul +#define MCHP_B32TMR_INSTANCES 2u + +/* Offset between instances of the Basic Timer blocks */ +#define MCHP_BTMR_INSTANCE_POS 5ul +#define MCHP_BTMR_INSTANCE_OFS 0x20U + +/* Base frequency of all basic timers is AHB clock */ +#define MCHP_BTMR_BASE_FREQ 48000000ul +#define MCHP_BTMR_MIN_FREQ (MCHP_BTMR_BASE_FREQ / 0x10000ul) + +/* 0 <= n < MCHP_B16TMR_INSTANCES */ +#define MCHP_B16TMR_ADDR(n) \ + (MCHP_B16TMR_BASE + ((uint32_t)(n) * MCHP_BTMR_INSTANCE_OFS)) + +#define MCHP_B16TMR0_ADDR 0x40000C00ul +#define MCHP_B16TMR1_ADDR 0x40000C20ul +#define MCHP_B16TMR2_ADDR 0x40000C40ul +#define MCHP_B16TMR3_ADDR 0x40000C60ul + +/* 0 <= n < MCHP_B32TMR_INSTANCES */ +#define MCHP_B32TMR_ADDR(n) \ + (MCHP_B32TMR_BASE + ((uint32_t)(n) << MCHP_BTMR_INSTANCE_POS)) + +#define MCHP_B32TMR0_ADDR 0x40000C80ul +#define MCHP_B32TMR1_ADDR 0x40000CA0ul + +/* + * Basic Timer Count Register (Offset +00h) + * 32-bit R/W + * 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0 + */ +#define MCHP_BTMR_CNT_OFS 0x00ul + +/* + * Basic Timer Preload Register (Offset +04h) + * 32-bit R/W + * 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0 + */ +#define MCHP_BTMR_PRELOAD_OFS 0x04 + +/* Basic Timer Status Register (Offset +08h) R/W1C */ +#define MCHP_BTMR_STS_OFS 0x08ul +#define MCHP_BTMR_STS_MASK 0x01ul +#define MCHP_BTMR_STS_ACTIVE_POS 0u +#define MCHP_BTMR_STS_ACTIVE 0x01ul + +/* Basic Timer Interrupt Enable Register (Offset +0Ch) */ +#define MCHP_BTMR_INTEN_OFS 0x0Cul +#define MCHP_BTMR_INTEN_MASK 0x01ul +#define MCHP_BTMR_INTEN_POS 0u +#define MCHP_BTMR_INTEN 0x01ul +#define MCHP_BTMR_INTDIS 0ul + +/* Basic Timer Control Register (Offset +10h) */ +#define MCHP_BTMR_CTRL_OFS 0x10ul +#define MCHP_BTMR_CTRL_MASK 0xFFFF00FDul + +#define MCHP_BTMR_CTRL_PRESCALE_POS 16u +#define MCHP_BTMR_CTRL_PRESCALE_MASK0 0xFFFFul +#define MCHP_BTMR_CTRL_PRESCALE_MASK 0xFFFF0000ul + +#define MCHP_BTMR_CTRL_HALT 0x80ul +#define MCHP_BTMR_CTRL_RELOAD 0x40ul +#define MCHP_BTMR_CTRL_START 0x20ul +#define MCHP_BTMR_CTRL_SOFT_RESET 0x10ul +#define MCHP_BTMR_CTRL_AUTO_RESTART 0x08ul +#define MCHP_BTMR_CTRL_COUNT_UP 0x04ul +#define MCHP_BTMR_CTRL_ENABLE 0x01ul +/* */ +#define MCHP_BTMR_CTRL_HALT_POS 7u +#define MCHP_BTMR_CTRL_RELOAD_POS 6u +#define MCHP_BTMR_CTRL_START_POS 5u +#define MCHP_BTMR_CTRL_SRESET_POS 4u +#define MCHP_BTMR_CTRL_AUTO_RESTART_POS 3u +#define MCHP_BTMR_CTRL_COUNT_DIR_POS 2u +#define MCHP_BTMR_CTRL_ENABLE_POS 0u + +/* Basic Timer interrupt routing */ +#define MCHP_B16TMR0_GIRQ 23u +#define MCHP_B16TMR1_GIRQ 23u +#define MCHP_B32TMR0_GIRQ 23u +#define MCHP_B32TMR1_GIRQ 23u + +/* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ +#define MCHP_B16TMR0_GIRQ_POS 0u +#define MCHP_B16TMR1_GIRQ_POS 1u +#define MCHP_B32TMR0_GIRQ_POS 4u +#define MCHP_B32TMR1_GIRQ_POS 5u + +#define MCHP_B16TMR0_GIRQ_VAL BIT(0) +#define MCHP_B16TMR1_GIRQ_VAL BIT(1) +#define MCHP_B16TMR2_GIRQ_VAL BIT(2) +#define MCHP_B16TMR3_GIRQ_VAL BIT(3) +#define MCHP_B32TMR0_GIRQ_VAL BIT(4) +#define MCHP_B32TMR1_GIRQ_VAL BIT(5) + +/* Basic timer GIRQ aggregated NVIC input */ +#define MCHP_B16TMR0_NVIC_AGGR 14u +#define MCHP_B16TMR1_NVIC_AGGR 14u +#define MCHP_B16TMR2_NVIC_AGGR 14u +#define MCHP_B16TMR3_NVIC_AGGR 14u +#define MCHP_B32TMR0_NVIC_AGGR 14u +#define MCHP_B32TMR1_NVIC_AGGR 14u + +/* Basic timer direct NVIC inputs */ +#define MCHP_B16TMR0_NVIC_DIRECT 136u +#define MCHP_B16TMR1_NVIC_DIRECT 137u +#define MCHP_B16TMR2_NVIC_DIRECT 138u +#define MCHP_B16TMR3_NVIC_DIRECT 139u +#define MCHP_B32TMR0_NVIC_DIRECT 140u +#define MCHP_B32TMR1_NVIC_DIRECT 141u + +/* =========================================================================*/ +/* ================ 16-bit Counter/Timer ================ */ +/* =========================================================================*/ +#define MCHP_CTMR_BASE 0x40000D00ul + +/* Offset between instances of the Basic Timer blocks */ +#define MCHP_CTMR_INSTANCE_POS 5ul +#define MCHP_CTMR_INSTANCE_OFS 0x20U + +/* 0 <= n < MCHP_CTMR_INSTANCES */ +#define MCHP_CTMR_ADDR(n) \ + (MCHP_CTMR_BASE + ((uint32_t)(n) * MCHP_CTMR_INSTANCE_OFS)) + +#define MCHP_CTMR0_ADDR 0x40000D00ul +#define MCHP_CTMR1_ADDR 0x40000D20ul +#define MCHP_CTMR2_ADDR 0x40000D40ul +#define MCHP_CTMR3_ADDR 0x40000D60ul + +/* 16-bit Counter-Timer Control Register: offset 0x00 (RW and RO) */ +#define MCHP_CTMR_CTRL_OFS 0x00U +#define MCHP_CTMR_CTRL_MASK 0x1fffU +#define MCHP_CTMR_CTRL_RW_MASK 0x07ffU +#define MCHP_CTMR_CTRL_RO_MASK 0x1800U +#define MCHP_CTMR_CTRL_EN_POS 0 +#define MCHP_CTMR_CTRL_RESET_POS 1 +#define MCHP_CTMR_CTRL_MODE_POS 2 +#define MCHP_CTMR_CTRL_INPOL_POS 4 +#define MCHP_CTMR_CTRL_UPDN_POS 5 +#define MCHP_CTMR_CTRL_TOUT_EN_POS 6 +#define MCHP_CTMR_CTRL_RLOAD_POS 7 +#define MCHP_CTMR_CTRL_FILT_BYP_POS 8 +#define MCHP_CTMR_CTRL_PD_POS 9 +#define MCHP_CTMR_CTRL_TOUT_POL_POS 10 +#define MCHP_CTMR_CTRL_SLP_EN_POS 11 /* RO */ +#define MCHP_CTMR_CTRL_CLK_REQ_POS 12 /* RO */ + +#define MCHP_CTMR_CTRL_EN BIT(MCHP_CTMR_CTRL_EN_POS) +#define MCHP_CTMR_CTRL_RESET BIT(MCHP_CTMR_CTRL_RESET_POS) +#define MCHP_CTMR_CTRL_MODE_MASK SHLU32(3u, 2) +#define MCHP_CTMR_CTRL_MODE_TIMER 0U +#define MCHP_CTMR_CTRL_MODE_EVENT SHLU32(1u, 2) +#define MCHP_CTMR_CTRL_MODE_ONESHOT SHLU32(2u, 2) +#define MCHP_CTMR_CTRL_MEAS_EVENT SHLU32(3u, 2) +#define MCHP_CTMR_CTRL_INPOL_LO BIT(MCHP_CTMR_CTRL_INPOL_POS) +#define MCHP_CTMR_CTRL_EV_UP BIT(MCHP_CTMR_CTRL_UPDN_POS) +#define MCHP_CTMR_CTRL_TM_TIN_DE_PAUSE BIT(MCHP_CTMR_CTRL_UPDN_POS) +#define MCHP_CTMR_CTRL_TOUT_EN BIT(MCHP_CTMR_CTRL_TOUT_EN_POS) +#define MCHP_CTMR_CTRL_RLOAD_NOW BIT(MCHP_CTMR_CTRL_RLOAD_POS) +#define MCHP_CTMR_CTRL_FILT_BYP_EN BIT(MCHP_CTMR_CTRL_FILT_BYP_POS) +#define MCHP_CTMR_CTRL_PD_NOW BIT(MCHP_CTMR_CTRL_PD_POS) +#define MCHP_CTMR_CTRL_TOUT_POL_LO BIT(MCHP_CTMR_CTRL_TOUT_POL_POS) +#define MCHP_CTMR_CTRL_SLP_EN_ACT BIT(MCHP_CTMR_CTRL_SLP_EN_POS) +#define MCHP_CTMR_CTRL_CLK_REQ_ACT BIT(MCHP_CTMR_CTRL_CLK_REQ_POS) + +/* 16-bit Counter-Timer Clock and Event Control Register: offset 0x04 (RW) */ +#define MCHP_CTMR_CEVC_OFS 0x04U +#define MCHP_CTMR_CEVC_MASK 0x0fefU +#define MCHP_CTMR_CEVC_TCLK_POS 0 +#define MCHP_CTMR_CEVC_EDGE_POS 5 +#define MCHP_CTMR_CEVC_EVENT_POS 7 +#define MCHP_CTMR_CEVC_FCLK_POS 8 +#define MCHP_CTMR_CEVC_TCLK_MASK 0x0fU +#define MCHP_CTMR_CEVC_TCLK_DIV_1 0U +#define MCHP_CTMR_CEVC_TCLK_DIV_2 1U +#define MCHP_CTMR_CEVC_TCLK_DIV_3 2U +#define MCHP_CTMR_CEVC_TCLK_DIV_4 3U +#define MCHP_CTMR_CEVC_EDGE_NONE SHLU32(3U, 5) +#define MCHP_CTMR_CEVC_EDGE_BOTH SHLU32(2U, 5) +#define MCHP_CTMR_CEVC_EDGE_RISING SHLU32(1U, 5) +#define MCHP_CTMR_CEVC_EDGE_FALLING 0U +#define MCHP_CTMR_CEVC_EVENT_TIN_EN BIT(7) +#define MCHP_CTMR_CEVC_FCLK_DIV_1 0U +#define MCHP_CTMR_CEVC_FCLK_DIV_2 SHLU32(1U, 8) +#define MCHP_CTMR_CEVC_FCLK_DIV_3 SHLU32(2U, 8) +#define MCHP_CTMR_CEVC_FCLK_DIV_4 SHLU32(3U, 8) + +/* 16-bit Counter-Timer Reload Register: Offset 0x08 (RW) */ +#define MCHP_CTMR_RELOAD_OFS 0x08U + +/* 16-bit Counter-Timer Count Register: Offset 0x0C (RO) */ +#define MCHP_CTMR_COUNT_OFS 0x0CU + + +/* =========================================================================*/ +/* ================ HTMR ================ */ +/* =========================================================================*/ + +#define MCHP_HTMR_BASE_ADDR 0x40009800ul +#define MCHP_HTMR_MAX_INSTANCES 2u +#define MCHP_HTMR_SPACING 0x20ul +#define MCHP_HTMR_SPACING_PWROF2 5u + +#define MCHP_HTMR_ADDR(n) \ + (MCHP_HTMR_BASE_ADDR + ((uint32_t)(n) * MCHP_HTMR_SPACING)) + +#define MCHP_HTMR0_ADDR 0x40009800ul +#define MCHP_HTMR1_ADDR 0x40009820ul + +/* + * Set count resolution in bit[0] + * 0 = 30.5 us (32786 Hz) + * 1 = 125 ms (8 Hz) + */ +#define MCHP_HTMR_CTRL_REG_MASK 0x01ul +#define MCHP_HTMR_CTRL_RESOL_POS 0u +#define MCHP_HTMR_CTRL_RESOL_MASK BIT(MCHP_HTMR_CTRL_EN_POS) +#define MCHP_HTMR_CTRL_RESOL_30US 0u +#define MCHP_HTMR_CTRL_RESOL_125MS BIT(MCHP_HTMR_CTRL_EN_POS) + +/* + * Hibernation timer is started and stopped by writing a value + * to the CNT (count) register. + * Writing a non-zero value resets and start the counter counting down. + * Writing 0 stops the timer. + */ +#define MCHP_HTMR_CNT_STOP_VALUE 0u + +/* Hibernation timer interrupt routing */ +#define MCHP_HTMR0_GIRQ 23u +#define MCHP_HTMR1_GIRQ 23u + +/* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ +#define MCHP_HTMR0_GIRQ_POS 16u +#define MCHP_HTMR1_GIRQ_POS 17u + +#define MCHP_HTMR0_GIRQ_VAL BIT(16) +#define MCHP_HTMR1_GIRQ_VAL BIT(17) + +/* Hibernation timer GIRQ aggregated NVIC input */ +#define MCHP_HTMR0_NVIC_AGGR 14u +#define MCHP_HTMR1_NVIC_AGGR 14u + +/* Hibernation timer direct NVIC inputs */ +#define MCHP_HTMR0_NVIC_DIRECT 112u +#define MCHP_HTMR1_NVIC_DIRECT 113u + +/* =========================================================================*/ +/* ================ Capture/Compare Timer ================ */ +/* =========================================================================*/ + +#define MCHP_CCT_BASE_ADDR 0x40001000ul +#define MCHP_CCT_MAX_INSTANCE 1u + +/* Control register at offset 0x00. Must use 32-bit access */ +#define MCHP_CCT_CTRL_ACTIVATE BIT(0) +#define MCHP_CCT_CTRL_FRUN_EN BIT(1) +#define MCHP_CCT_CTRL_FRUN_RESET BIT(2) /* self clearing bit */ +#define MCHP_CCT_CTRL_TCLK_MASK0 0x07ul +#define MCHP_CCT_CTRL_TCLK_MASK SHLU32(MCHP_CCT_CTRL_TCLK_MASK0, 4) +#define MCHP_CCT_CTRL_TCLK_DIV_1 0ul +#define MCHP_CCT_CTRL_TCLK_DIV_2 SHLU32(1u, 4) +#define MCHP_CCT_CTRL_TCLK_DIV_4 SHLU32(2u, 4) +#define MCHP_CCT_CTRL_TCLK_DIV_8 SHLU32(3u, 4) +#define MCHP_CCT_CTRL_TCLK_DIV_16 SHLU32(4u, 4) +#define MCHP_CCT_CTRL_TCLK_DIV_32 SHLU32(5u, 4) +#define MCHP_CCT_CTRL_TCLK_DIV_64 SHLU32(6u, 4) +#define MCHP_CCT_CTRL_TCLK_DIV_128 SHLU32(7u, 4) +#define MCHP_CCT_CTRL_COMP0_EN BIT(8) +#define MCHP_CCT_CTRL_COMP1_EN BIT(9) +#define MCHP_CCT_CTRL_COMP1_SET BIT(16) /* R/WS */ +#define MCHP_CCT_CTRL_COMP0_SET BIT(17) /* R/WS */ +#define MCHP_CCT_CTRL_COMP1_CLR BIT(24) /* R/W1C */ +#define MCHP_CCT_CTRL_COMP0_CLR BIT(25) /* R/W1C */ + + +/* Capture Compare timer interrupt routing */ +#define MCHP_CCT_GIRQ 18u + +/* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ +#define MCHP_CCT_TMR_GIRQ_POS 20u +#define MCHP_CCT_CAP0_GIRQ_POS 21u +#define MCHP_CCT_CAP1_GIRQ_POS 22u +#define MCHP_CCT_CAP2_GIRQ_POS 23u +#define MCHP_CCT_CAP3_GIRQ_POS 24u +#define MCHP_CCT_CAP4_GIRQ_POS 25u +#define MCHP_CCT_CAP5_GIRQ_POS 26u +#define MCHP_CCT_CMP0_GIRQ_POS 27u +#define MCHP_CCT_CMP1_GIRQ_POS 28u + +#define MCHP_CCT_TMR_GIRQ_VAL BIT(20) +#define MCHP_CCT_CAP0_GIRQ_VAL BIT(21) +#define MCHP_CCT_CAP1_GIRQ_VAL BIT(22) +#define MCHP_CCT_CAP2_GIRQ_VAL BIT(23) +#define MCHP_CCT_CAP3_GIRQ_VAL BIT(24) +#define MCHP_CCT_CAP4_GIRQ_VAL BIT(25) +#define MCHP_CCT_CAP5_GIRQ_VAL BIT(26) +#define MCHP_CCT_CMP0_GIRQ_VAL BIT(27) +#define MCHP_CCT_CMP1_GIRQ_VAL BIT(28) +#define MCHP_CCT_GIRQ_VAL_ALL 0x1FF00000ul + +/* Capture Compare timer GIRQ aggregated NVIC input */ +#define MCHP_CCT_NVIC_AGGR 10u + +/* Capture Compare timer direct NVIC inputs */ +#define MCHP_CCT_TMR_NVIC_DIRECT 146u +#define MCHP_CCT_CAP0_NVIC_DIRECT 147u +#define MCHP_CCT_CAP1_NVIC_DIRECT 148u +#define MCHP_CCT_CAP2_NVIC_DIRECT 149u +#define MCHP_CCT_CAP3_NVIC_DIRECT 150u +#define MCHP_CCT_CAP4_NVIC_DIRECT 151u +#define MCHP_CCT_CAP5_NVIC_DIRECT 152u +#define MCHP_CCT_CMP0_NVIC_DIRECT 153u +#define MCHP_CCT_CMP1_NVIC_DIRECT 154u + +/* =========================================================================*/ +/* ================ RTMR ================ */ +/* =========================================================================*/ + +#define MCHP_RTMR_BASE_ADDR 0x40007400ul + +#define MCHP_RTMR_FREQ_HZ 32768ul + +#define MCHP_RTMR_CTRL_MASK 0x1Ful +#define MCHP_RTMR_CTRL_BLK_EN_POS 0u +#define MCHP_RTMR_CTRL_BLK_EN_MASK BIT(MCHP_RTMR_CTRL_BLK_EN_POS) +#define MCHP_RTMR_CTRL_BLK_EN BIT(MCHP_RTMR_CTRL_BLK_EN_POS) + +#define MCHP_RTMR_CTRL_AUTO_RELOAD_POS 1u +#define MCHP_RTMR_CTRL_AUTO_RELOAD_MASK BIT(MCHP_RTMR_CTRL_AUTO_RELOAD_POS) +#define MCHP_RTMR_CTRL_AUTO_RELOAD BIT(MCHP_RTMR_CTRL_AUTO_RELOAD_POS) + +#define MCHP_RTMR_CTRL_START_POS 2u +#define MCHP_RTMR_CTRL_START_MASK BIT(MCHP_RTMR_CTRL_START_POS) +#define MCHP_RTMR_CTRL_START BIT(MCHP_RTMR_CTRL_START_POS) + +#define MCHP_RTMR_CTRL_HW_HALT_EN_POS 3u +#define MCHP_RTMR_CTRL_HW_HALT_EN_MASK BIT(MCHP_RTMR_CTRL_HW_HALT_EN_POS) +#define MCHP_RTMR_CTRL_HW_HALT_EN BIT(MCHP_RTMR_CTRL_HW_HALT_EN_POS) + +#define MCHP_RTMR_CTRL_FW_HALT_EN_POS 4u +#define MCHP_RTMR_CTRL_FW_HALT_EN_MASK BIT(MCHP_RTMR_CTRL_FW_HALT_EN_POS) +#define MCHP_RTMR_CTRL_FW_HALT_EN BIT(MCHP_RTMR_CTRL_FW_HALT_EN_POS) + +/* RTOS timer interrupt routing */ +#define MCHP_RTMR_GIRQ 23u + +/* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ +#define MCHP_RTMR_GIRQ_POS 10u + +#define MCHP_RTMR_GIRQ_VAL BIT(10) + +/* RTOS timer GIRQ aggregated NVIC input */ +#define MCHP_RTMR_NVIC_AGGR 14u + +/* RTOS timer direct NVIC inputs */ +#define MCHP_RTMR_NVIC_DIRECT 111u + +/* =========================================================================*/ +/* ================ WKTMR ================ */ +/* =========================================================================*/ + +#define MCHP_WKTMR_BASE_ADDR 0x4000AC80ul + +#define MCHP_WKTMR_CTRL_MASK 0x41ul +#define MCHP_WKTMR_CTRL_WT_EN_POS 0u +#define MCHP_WKTMR_CTRL_WT_EN_MASK BIT(MCHP_WKTMR_CTRL_WT_EN_POS) +#define MCHP_WKTMR_CTRL_WT_EN BIT(MCHP_WKTMR_CTRL_WT_EN_POS) +#define MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS 6u +#define MCHP_WKTMR_CTRL_PWRUP_EV_EN_MASK BIT(MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS) +#define MCHP_WKTMR_CTRL_PWRUP_EV_EN BIT(MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS) + +#define MCHP_WKTMR_ALARM_CNT_MASK 0x0FFFFFFFul +#define MCHP_WKTMR_TMR_CMP_MASK 0x0FFFFFFFul +#define MCHP_WKTMR_CLK_DIV_MASK 0x7FFFul + +#define MCHP_WKTMR_SS_MASK 0x0Ful +#define MCHP_WKTMR_SS_RATE_DIS 0x00ul +#define MCHP_WKTMR_SS_RATE_2HZ 0x01ul +#define MCHP_WKTMR_SS_RATE_4HZ 0x02ul +#define MCHP_WKTMR_SS_RATE_8HZ 0x03ul +#define MCHP_WKTMR_SS_RATE_16HZ 0x04ul +#define MCHP_WKTMR_SS_RATE_32HZ 0x05ul +#define MCHP_WKTMR_SS_RATE_64HZ 0x06ul +#define MCHP_WKTMR_SS_RATE_128HZ 0x07ul +#define MCHP_WKTMR_SS_RATE_256HZ 0x08ul +#define MCHP_WKTMR_SS_RATE_512HZ 0x09ul +#define MCHP_WKTMR_SS_RATE_1024HZ 0x0Aul +#define MCHP_WKTMR_SS_RATE_2048HZ 0x0Bul +#define MCHP_WKTMR_SS_RATE_4096HZ 0x0Cul +#define MCHP_WKTMR_SS_RATE_8192HZ 0x0Dul +#define MCHP_WKTMR_SS_RATE_16384HZ 0x0Eul +#define MCHP_WKTMR_SS_RATE_32768HZ 0x0Ful + +#define MCHP_WKTMR_SWKC_MASK 0x3C3ul +#define MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS 0ul +#define MCHP_WKTMR_SWKC_PWRUP_EV_STS_MASK \ + BIT(MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS) +#define MCHP_WKTMR_SWKC_PWRUP_EV_STS \ + BIT(MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS) +#define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS 4ul +#define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_MASK \ + BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS) +#define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS \ + BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS) +#define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS 5ul +#define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_MASK \ + BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS) +#define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN \ + BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS) +#define MCHP_WKTMR_SWKC_AUTO_RELOAD_POS 6ul +#define MCHP_WKTMR_SWKC_AUTO_RELOAD_MASK \ + BIT(MCHP_WKTMR_SWKC_AUTO_RELOAD_POS) +#define MCHP_WKTMR_SWKC_AUTO_RELOAD \ + BIT(MCHP_WKTMR_SWKC_AUTO_RELOAD_POS) + +/* Week timer interrupt routing */ +#define MCHP_WKTMR_GIRQ 21u + +/* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ +#define MCHP_WKTMR_ALARM_GIRQ_POS 3u +#define MCHP_WKTMR_SUBWK_GIRQ_POS 4u +#define MCHP_WKTMR_ONESEC_GIRQ_POS 5u +#define MCHP_WKTMR_SUBSEC_GIRQ_POS 6u +#define MCHP_WKTMR_SUSPWR_GIRQ_POS 7u + +#define MCHP_WKTMR_ALARM_GIRQ_VAL BIT(3) +#define MCHP_WKTMR_SUBWK_GIRQ_VAL BIT(4) +#define MCHP_WKTMR_ONESEC_GIRQ_VAL BIT(5) +#define MCHP_WKTMR_SUBSEC_GIRQ_VAL BIT(6) +#define MCHP_WKTMR_SUSPWR_GIRQ_VAL BIT(7) + +/* Capture Compare timer GIRQ aggregated NVIC input */ +#define MCHP_WKTMR_NVIC_AGGR 13u + +/* Capture Compare timer direct NVIC inputs */ +#define MCHP_WKTMR_ALARM_NVIC_DIRECT 114u +#define MCHP_WKTMR_SUBWK_NVIC_DIRECT 115u +#define MCHP_WKTMR_ONESEC_NVIC_DIRECT 116u +#define MCHP_WKTMR_SUBSEC_NVIC_DIRECT 117u +#define MCHP_WKTMR_SUSPWR_NVIC_DIRECT 118u + +#endif /* #ifndef _COMPONENT_TIMER_H */ +/* end timer.h */ +/** @} + */ diff --git a/mec/mec172x/component/uart.h b/mec/mec172x/component/uart.h new file mode 100644 index 0000000..bcfc531 --- /dev/null +++ b/mec/mec172x/component/uart.h @@ -0,0 +1,248 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file uart.h + * MEC172x UART Peripheral Library API + */ +/** @defgroup MEC172x Peripherals UART + */ + +#ifndef _COMPONENT_UART_H +#define _COMPONENT_UART_H + +#include +#include + +#include +#include + +#define MCHP_UART0_ID 0u +#define MCHP_UART1_ID 1u +#define MCHP_UART_MAX_ID 2u + +#define MCHP_UART_RX_FIFO_MAX_LEN 16u +#define MCHP_UART_TX_FIFO_MAX_LEN 16u + +#define MCHP_UART_BAUD_RATE_MIN 50ul +#define MCHP_UART_BAUD_RATE_MAX 1500000ul + +#define MCHP_UART0_BASE_ADDRESS 0x400F2400ul +#define MCHP_UART1_BASE_ADDRESS 0x400F2800ul +#define MCHP_UART_SPACING 0x400ul + +#define MCHP_UART_BASE_ADDR(n) \ + (MCHP_UART0_BASE_ADDRESS + ((uint32_t)(n) * 0x400ul)) + +#define MCHP_UART_GIRQ_NUM 15u +#define MCHP_UART_GIRQ_ID 7u +#define MCHP_UART0_GIRQ_POS 0u +#define MCHP_UART1_GIRQ_POS 1u +#define MCHP_UART0_GIRQ_VAL BIT(MCHP_UART0_GIRQ_POS) +#define MCHP_UART1_GIRQ_VAL BIT(MCHP_UART1_GIRQ_POS) +#define MCHP_UART0_NVIC 40u +#define MCHP_UART1_NVIC 41u +#define MCHP_UART2_NVIC 44u + +/* + * LCR DLAB=0 + * Transmit buffer(WO), Receive buffer(RO) + * LCR DLAB=1, BAUD rate divisor LSB + */ +#define MCHP_UART_RTXB_OFS 0u +#define MCHP_UART_BRGD_LSB_OFS 0u + +/* + * LCR DLAB=0 + * Interrupt Enable Register, R/W + * LCR DLAB=1, BAUD rate divisor MSB + */ +#define MCHP_UART_BRGD_MSB_OFS 1u +#define MCHP_UART_IER_OFS 1u +#define MCHP_UART_IER_MASK 0x0Ful +#define MCHP_UART_IER_ERDAI 0x01ul /* Received data available and timeouts */ +#define MCHP_UART_IER_ETHREI 0x02ul /* TX Holding register empty */ +#define MCHP_UART_IER_ELSI 0x04ul /* Errors: Overrun, Parity, Framing, and Break */ +#define MCHP_UART_IER_EMSI 0x08ul /* Modem Status */ +#define MCHP_UART_IER_ALL 0x0Ful + +/* FIFO Contro Register, Write-Only */ +#define MCHP_UART_FCR_OFS 2u +#define MCHP_UART_FCR_MASK 0xCFu +#define MCHP_UART_FCR_EXRF 0x01u /* Enable TX & RX FIFO's */ +#define MCHP_UART_FCR_CLR_RX_FIFO 0x02u /* Clear RX FIFO, bit is self-clearing */ +#define MCHP_UART_FCR_CLR_TX_FIFO 0x04u /* Clear TX FIFO, bit is self-clearing */ +#define MCHP_UART_FCR_DMA_EN 0x08u /* DMA Mode Enable. Not implemented */ +#define MCHP_UART_FCR_RX_FIFO_LVL_MASK 0xC0u /* RX FIFO trigger level mask */ +#define MCHP_UART_FCR_RX_FIFO_LVL_1 0x00u +#define MCHP_UART_FCR_RX_FIFO_LVL_4 0x40u +#define MCHP_UART_FCR_RX_FIFO_LVL_8 0x80u +#define MCHP_UART_FCR_RX_FIFO_LVL_14 0xC0u + +/* Interrupt Identification Register, Read-Only */ +#define MCHP_UART_IIR_OFS 2u +#define MCHP_UART_IIR_MASK 0xCFu +#define MCHP_UART_IIR_NOT_IPEND 0x01u +#define MCHP_UART_IIR_INTID_MASK0 0x07u +#define MCHP_UART_IIR_INTID_POS 1u +#define MCHP_UART_IIR_INTID_MASK 0x0Eu +#define MCHP_UART_IIR_FIFO_EN_MASK 0xC0u +/* interrupt values */ +#define MCHP_UART_IIR_INT_NONE 0x01u +#define MCHP_UART_IIR_INT_LS 0x06u /* Highest priority: Line status, overrun, framing, or break */ +#define MCHP_UART_IIR_INT_RX 0x04u /* Highest-1. RX data available or RX FIFO trigger level reached */ +#define MCHP_UART_IIR_INT_RX_TMOUT 0x0Cu /* Highest-2. RX timeout */ +#define MCHP_UART_IIR_INT_THRE 0x02u /* Highest-3. TX Holding register empty. */ +#define MCHP_UART_IIR_INT_MS 0x00u /* Highest-4. MODEM status. */ + +/* Line Control Register R/W */ +#define MCHP_UART_LCR_OFS 3u +#define MCHP_UART_LCR_WORD_LEN_MASK 0x03u +#define MCHP_UART_LCR_WORD_LEN_5 0x00u +#define MCHP_UART_LCR_WORD_LEN_6 0x01u +#define MCHP_UART_LCR_WORD_LEN_7 0x02u +#define MCHP_UART_LCR_WORD_LEN_8 0x03u +#define MCHP_UART_LCR_STOP_BIT_1 0x00u +#define MCHP_UART_LCR_STOP_BIT_2 0x04u /* 2 for 6-8 bits or 1.5 for 5 bits */ +#define MCHP_UART_LCR_PARITY_NONE 0x00u +#define MCHP_UART_LCR_PARITY_EN 0x08u +#define MCHP_UART_LCR_PARITY_ODD 0x00u +#define MCHP_UART_LCR_PARITY_EVEN 0x10u +#define MCHP_UART_LCR_STICK_PARITY 0x20u +#define MCHP_UART_LCR_BREAK_EN 0x40u +#define MCHP_UART_LCR_DLAB_EN 0x80u + +/* MODEM Control Register R/W */ +#define MCHP_UART_MCR_OFS 4u +#define MCHP_UART_MCR_MASK 0x1Fu +#define MCHP_UART_MCR_DTRn 0x01u +#define MCHP_UART_MCR_RTSn 0x02u +#define MCHP_UART_MCR_OUT1 0x04u +#define MCHP_UART_MCR_OUT2 0x08u +#define MCHP_UART_MCR_LOOPBCK_EN 0x10u + +/* Line Status Register RO */ +#define MCHP_UART_LSR_OFS 5u +#define MCHP_UART_LSR_DATA_RDY 0x01u +#define MCHP_UART_LSR_OVERRUN 0x02u +#define MCHP_UART_LSR_PARITY 0x04u +#define MCHP_UART_LSR_FRAME 0x08u +#define MCHP_UART_LSR_RX_BREAK 0x10u +#define MCHP_UART_LSR_THRE 0x20u +#define MCHP_UART_LSR_TEMT 0x40u +#define MCHP_UART_LSR_FIFO_ERR 0x80u +#define MCHP_UART_LSR_ANY 0xFFu + +/* MODEM Status Register RO */ +#define MCHP_UART_MSR_OFS 6u +#define MCHP_UART_MSR_DCTS 0x01u +#define MCHP_UART_MSR_DDSR 0x02u +#define MCHP_UART_MSR_TERI 0x04u +#define MCHP_UART_MSR_DDCD 0x08u +#define MCHP_UART_MSR_CTS 0x10u +#define MCHP_UART_MSR_DSR 0x20u +#define MCHP_UART_MSR_RI 0x40u +#define MCHP_UART_MSR_DCD 0x80u + +/* Scratch Register RO */ +#define MCHP_UART_SCR_OFS 7u + +/* UART Logical Device Activate Register */ +#define MCHP_UART_LD_ACT 0x330ul +#define MCHP_UART_LD_ACTIVATE 0x01ul + +/* UART Logical Device Config Register */ +#define MCHP_UART_LD_CFG 0x3F0ul +#define MCHP_UART_LD_CFG_INTCLK 0U +#define MCHP_UART_LD_CFG_NO_INVERT 0U +#define MCHP_UART_LD_CFG_RESET_SYS 0U +#define MCHP_UART_LD_CFG_EXTCLK BIT(0) +#define MCHP_UART_LD_CFG_RESET_VCC BIT(1) +#define MCHP_UART_LD_CFG_INVERT BIT(2) + +/* BAUD rate generator */ +#define MCHP_UART_INT_CLK_24M BIT(15) + +/* 1.8MHz internal clock source */ +#define MCHP_UART_1P8M_BAUD_50 2304u +#define MCHP_UART_1P8M_BAUD_110 1536u +#define MCHP_UART_1P8M_BAUD_150 768u +#define MCHP_UART_1P8M_BAUD_300 384u +#define MCHP_UART_1P8M_BAUD_1200 96u +#define MCHP_UART_1P8M_BAUD_2400 48u +#define MCHP_UART_1P8M_BAUD_9600 12u +#define MCHP_UART_1P8M_BAUD_19200 6u +#define MCHP_UART_1P8M_BAUD_38400 3u +#define MCHP_UART_1P8M_BAUD_57600 2u +#define MCHP_UART_1P8M_BAUD_115200 1u + +/* 24MHz internal clock source. n = 24e6 / (BAUD * 16) = 1500000 / BAUD */ +#define MCHP_UART_24M_BAUD_115200 ((13u) + (MCHP_UART_INT_CLK_24M)) +#define MCHP_UART_24M_BAUD_57600 ((26u) + (MCHP_UART_INT_CLK_24M)) + +/* + * Register access by UART zero based ID + * 0 <= uart id <= 1 + */ +#define MCHP_UART_TXB_WO_ID(id) \ + REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_RTXB_OFS) +#define MCHP_UART_RXB_RO_ID(id) \ + REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_RTXB_OFS) +#define MCHP_UART_BRGD_LSB_ID(id) \ + REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_BRGD_LSB_OFS) +#define MCHP_UART_BRGD_MSB_ID(id) \ + REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_BRGD_MSB_OFS) +#define MCHP_UART_FCR_WO_ID(id) \ + REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_FCR_OFS) +#define MCHP_UART_IIR_RO_ID(id) \ + REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_IIR_OFS) +#define MCHP_UART_LCR_ID(id) \ + REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_LCR_OFS) +#define MCHP_UART_MCR_ID(id) \ + REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_MCR_OFS) +#define MCHP_UART_LSR_RO_ID(id) \ + REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_LSR_OFS) +#define MCHP_UART_MSR_RO_ID(id) \ + REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_MSR_OFS) +#define MCHP_UART_SCR_ID(id) \ + REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_SCR_OFS) + +/* Register access by UART base address */ +#define MCHP_UART_TXB_WO(ba) REG8_OFS((ba), MCHP_UART_RTXB_OFS) +#define MCHP_UART_RXB_RO(ba) REG8_OFS((ba), MCHP_UART_RTXB_OFS) +#define MCHP_UART_BRGD_LSB(ba) REG8_OFS((ba), MCHP_UART_BRGD_LSB_OFS) +#define MCHP_UART_BRGD_MSB(ba) REG8_OFS((ba), MCHP_UART_BRGD_MSB_OFS) +#define MCHP_UART_FCR_WO(ba) REG8_OFS((ba), MCHP_UART_FCR_OFS) +#define MCHP_UART_IIR_RO(ba) REG8_OFS((ba), MCHP_UART_IIR_OFS) +#define MCHP_UART_LCR(ba) REG8_OFS((ba), MCHP_UART_LCR_OFS) +#define MCHP_UART_MCR(ba) REG8_OFS((ba), MCHP_UART_MCR_OFS) +#define MCHP_UART_LSR_RO(ba) REG8_OFS((ba), MCHP_UART_LSR_OFS) +#define MCHP_UART_MSR_RO(ba) REG8_OFS((ba), MCHP_UART_MSR_OFS) +#define MCHP_UART_SCR(ba) REG8_OFS((ba), MCHP_UART_SCR_OFS) + +#endif /* #ifndef _COMPONENT_MCHP_UART_H */ +/* end uart.h */ +/** @} + */ diff --git a/mec/mec172x/component/vbat.h b/mec/mec172x/component/vbat.h new file mode 100644 index 0000000..ad07a61 --- /dev/null +++ b/mec/mec172x/component/vbat.h @@ -0,0 +1,260 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file vbat.h + * MEC172x VBAT Registers and memory definitions + */ +/** @defgroup MEC172x Peripherals VBAT + */ + +#ifndef _COMPONENT_VBAT_H +#define _COMPONENT_VBAT_H + +#include +#include + +#include +#include + +/* VBAT Registers Registers */ +#define MCHP_VBAT_REGISTERS_ADDR 0x4000A400ul +#define MCHP_VBAT_MEMORY_ADDR 0x4000A800ul +#define MCHP_VBAT_MEMORY_SIZE 128ul + +/* Offset 0x00 Power-Fail and Reset Status */ +#define MCHP_VBATR_PFRS_OFS 0ul +#define MCHP_VBATR_PFRS_MASK 0x7Cul +#define MCHP_VBATR_PFRS_SYS_RST_POS 2u +#define MCHP_VBATR_PFRS_JTAG_POS 3u +#define MCHP_VBATR_PFRS_RESETI_POS 4u +#define MCHP_VBATR_PFRS_WDT_POS 5u +#define MCHP_VBATR_PFRS_SYSRESETREQ_POS 6u +#define MCHP_VBATR_PFRS_VBAT_RST_POS 7u + +#define MCHP_VBATR_PFRS_SYS_RST BIT(2) +#define MCHP_VBATR_PFRS_JTAG BIT(3) +#define MCHP_VBATR_PFRS_RESETI BIT(4) +#define MCHP_VBATR_PFRS_WDT BIT(5) +#define MCHP_VBATR_PFRS_SYSRESETREQ BIT(6) +#define MCHP_VBATR_PFRS_VBAT_RST BIT(7) + +/* Offset 0x08 32K Clock Source register */ +#define MCHP_VBATR_CS_OFS 0x08ul +#define MCHP_VBATR_CS_MASK 0x71f1ul +#define MCHP_VBATR_CS_SO_EN_POS 0 +#define MCHP_VBATR_CS_XTAL_EN_POS 8 +#define MCHP_VBATR_CS_XTAL_SEL_POS 9 +#define MCHP_VBATR_CS_XTAL_DHC_POS 10 +#define MCHP_VBATR_CS_XTAL_CNTR_POS 11 +#define MCHP_VBATR_CS_PCS_POS 16 +#define MCHP_VBATR_CS_DI32_VTR_OFF_POS 18 + +/* Enable and start internal 32KHz Silicon Oscillator */ +#define MCHP_VBATR_CS_SO_EN BIT(0) +/* Enable and start the external crystal */ +#define MCHP_VBATR_CS_XTAL_EN BIT(8) +/* single ended crystal on XTAL2 instead of parallel across XTAL1 and XTAL2 */ +#define MCHP_VBATR_CS_XTAL_SE BIT(9) +/* disable XTAL high startup current */ +#define MCHP_VBATR_CS_XTAL_DHC BIT(10) +/* crystal amplifier gain control */ +#define MCHP_VBATR_CS_XTAL_CNTR_MSK 0x1800u +#define MCHP_VBATR_CS_XTAL_CNTR_DG 0x0800u +#define MCHP_VBATR_CS_XTAL_CNTR_RG 0x1000u +#define MCHP_VBATR_CS_XTAL_CNTR_MG 0x1800u +/* Select source of peripheral 32KHz clock */ +#define MCHP_VBATR_CS_PCS_MSK 0x30000u +/* 32K silicon OSC when chip powered by VBAT or VTR */ +#define MCHP_VBATR_CS_PCS_VTR_VBAT_SO 0x00000u +/* 32K external crystal when chip powered by VBAT or VTR */ +#define MCHP_VBATR_CS_PCS_VTR_VBAT_XTAL 0x10000u +/* 32K input pin on VTR. Switch to Silicon OSC on VBAT */ +#define MCHP_VBATR_CS_PCS_VTR_PIN_SO 0x20000u +/* 32K input pin on VTR. Switch to crystal on VBAT */ +#define MCHP_VBATR_CS_PCS_VTR_PIN_XTAL 0x30000u +/* Disable internal 32K VBAT clock source when VTR is off */ +#define MCHP_VBATR_CS_DI32_VTR_OFF BIT(18) + +/* Monotonic Counter least significant word (32-bit) + * Read-only. Incrementes by one on read. */ +#define MCHP_VBATR_MCNT_LSW_OFS 0x20ul + +/* Monotonic Counter most significant word (32-bit). Read-Write */ +#define MCHP_VBATR_MCNT_MSW_OFS 0x24ul + +/* ROM Feature register */ +#define MCHP_VBATR_ROM_FEAT_OFS 0x28ul + +/* Embedded Reset Debounce Enable register */ +#define MCHP_VBATR_EMBRD_EN_OFS 0x34ul +#define MCHP_VBATR_EMBRD_EN BIT(0) + +/* Register access */ +#define MCHP_VBATR_PFRS() \ + REG8(MCHP_VBAT_REGISTERS_ADDR + MCHP_VBATR_PFRS_OFS) + +#define MCHP_VBATR_CS() \ + REG32(MCHP_VBAT_REGISTERS_ADDR + MCHP_VBATR_CS_OFS) + +#define MCHP_VBATR_MCNT_LO() \ + REG32(MCHP_VBAT_REGISTERS_ADDR + MCHP_VBATR_MCNT_LSW_OFS) + +#define MCHP_VBATR_MCNT_HI() \ + REG32(MCHP_VBAT_REGISTERS_ADDR + MCHP_VBATR_MCNT_MSW_OFS) + +#define MCHP_VBATR_EMBRD() \ + REG32(MCHP_VBAT_REGISTERS_ADDR + MCHP_VBATR_EMBRD_EN_OFS) + +/* -------------- VBAT Powered Control Interface (VCI) ------------------ */ +#define MCHP_VCI_BASE_ADDR 0x4000AE00ul + +/* VCI interrupts */ +#define MCHP_VCI_OVRD_GIRQ 21u +#define MCHP_VCI_IN0_GIRQ 21u +#define MCHP_VCI_IN1_GIRQ 21u +#define MCHP_VCI_IN2_GIRQ 21u +#define MCHP_VCI_IN3_GIRQ 21u +#define MCHP_VCI_IN4_GIRQ 21u + +/* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ +#define MCHP_VCI_OVRD_GIRQ_POS 10u +#define MCHP_VCI_IN0_GIRQ_POS 11u +#define MCHP_VCI_IN1_GIRQ_POS 12u +#define MCHP_VCI_IN2_GIRQ_POS 13u +#define MCHP_VCI_IN3_GIRQ_POS 14u +#define MCHP_VCI_IN4_GIRQ_POS 15u + +#define MCHP_VCI_OVRD_GIRQ_VAL BIT(MCHP_VCI_OVRD_GIRQ_POS) +#define MCHP_VCI_IN0_GIRQ_VAL BIT(MCHP_VCI_IN0_GIRQ_POS) +#define MCHP_VCI_IN1_GIRQ_VAL BIT(MCHP_VCI_IN1_GIRQ_POS) +#define MCHP_VCI_IN2_GIRQ_VAL BIT(MCHP_VCI_IN2_GIRQ_POS) +#define MCHP_VCI_IN3_GIRQ_VAL BIT(MCHP_VCI_IN3_GIRQ_POS) +#define MCHP_VCI_IN4_GIRQ_VAL BIT(MCHP_VCI_IN4_GIRQ_POS) + +/* VCI GIRQ aggregated NVIC input */ +#define MCHP_VCI_OVRD_NVIC_AGGR 13u +#define MCHP_VCI_IN0_NVIC_AGGR 13u +#define MCHP_VCI_IN1_NVIC_AGGR 13u +#define MCHP_VCI_IN2_NVIC_AGGR 13u +#define MCHP_VCI_IN3_NVIC_AGGR 13u +#define MCHP_VCI_IN4_NVIC_AGGR 13u + +/* VCI direct NVIC inputs */ +#define MCHP_VCI_OVRD_NVIC_DIRECT 121u +#define MCHP_VCI_IN0_NVIC_DIRECT 122u +#define MCHP_VCI_IN1_NVIC_DIRECT 123u +#define MCHP_VCI_IN2_NVIC_DIRECT 124u +#define MCHP_VCI_IN3_NVIC_DIRECT 125u +#define MCHP_VCI_IN4_NVIC_DIRECT 126u + +/* VCI Config register */ +#define MCHP_VCI_CFG_REG_OFS 0u +#define MCHP_VCI_CFG_REG_MASK 0x71F8Ful +#define MCHP_VCI_CFG_IN_MASK 0x7Fu +#define MCHP_VCI_CFG_IN0_HI 0x01u +#define MCHP_VCI_CFG_IN1_HI 0x02u +#define MCHP_VCI_CFG_IN2_HI 0x04u +#define MCHP_VCI_CFG_IN3_HI 0x08u +#define MCHP_VCI_CFG_IN4_HI 0x10u +#define MCHP_VCI_VCI_OVRD_IN_HI BIT(8) +#define MCHP_VCI_VCI_OUT_HI BIT(9) +#define MCHP_VCI_FW_CTRL_EN BIT(10) +#define MCHP_VCI_FW_EXT_SEL BIT(11) +#define MCHP_VCI_FILTER_BYPASS BIT(12) +#define MCHP_VCI_WEEK_ALARM BIT(16) +#define MCHP_VCI_RTC_ALARM BIT(17) +#define MCHP_VCI_SYS_PWR_PRES BIT(18) + +/* VCI Latch Enable register */ +/* VCI Latch Reset register */ +#define MCHP_VCI_LE_REG_OFS 4u +#define MCHP_VCI_LR_REG_OFS 8u +#define MCHP_VCI_LER_REG_MASK 0x3007Ful +#define MCHP_VCI_LER_IN_MASK 0x7Fu +#define MCHP_VCI_LER_IN0 0x01u +#define MCHP_VCI_LER_IN1 0x02u +#define MCHP_VCI_LER_IN2 0x04u +#define MCHP_VCI_LER_IN3 0x08u +#define MCHP_VCI_LER_IN4 0x10u +#define MCHP_VCI_LER_WEEK_ALARM BIT(16) +#define MCHP_VCI_LER_RTC_ALARM BIT(17) + +/* VCI Input Enable register */ +#define MCHP_VCI_INPUT_EN_REG_OFS 0x0Cu +#define MCHP_VCI_INPUT_EN_REG_MASK 0x7Ful +#define MCHP_VCI_INPUT_EN_IE_MASK 0x7Fu +#define MCHP_VCI_INPUT_EN_IN0 0x01u +#define MCHP_VCI_INPUT_EN_IN1 0x02u +#define MCHP_VCI_INPUT_EN_IN2 0x04u +#define MCHP_VCI_INPUT_EN_IN3 0x08u +#define MCHP_VCI_INPUT_EN_IN4 0x10u + +/* VCI Hold Off Count register */ +#define MCHP_VCI_HDO_REG_OFS 0x10u +#define MCHP_VCI_HDO_REG_MASK 0xFFul + +/* VCI Polarity register */ +#define MCHP_VCI_POL_REG_OFS 0x14u +#define MCHP_VCI_POL_REG_MASK 0x7Ful +#define MCHP_VCI_POL_IE30_MASK 0x0Fu +#define MCHP_VCI_POL_ACT_HI_IN0 0x01u +#define MCHP_VCI_POL_ACT_HI_IN1 0x02u +#define MCHP_VCI_POL_ACT_HI_IN2 0x04u +#define MCHP_VCI_POL_ACT_HI_IN3 0x08u +#define MCHP_VCI_POL_ACT_HI_IN4 0x10u + +/* VCI Positive Edge Detect register */ +#define MCHP_VCI_PDET_REG_OFS 0x18u +#define MCHP_VCI_PDET_REG_MASK 0x7Ful +#define MCHP_VCI_PDET_IN0 0x01u +#define MCHP_VCI_PDET_IN1 0x02u +#define MCHP_VCI_PDET_IN2 0x04u +#define MCHP_VCI_PDET_IN3 0x08u +#define MCHP_VCI_PDET_IN4 0x10u + +/* VCI Positive Edge Detect register */ +#define MCHP_VCI_NDET_REG_OFS 0x1Cu +#define MCHP_VCI_NDET_REG_MASK 0x7Ful +#define MCHP_VCI_NDET_IN0 0x01u +#define MCHP_VCI_NDET_IN1 0x02u +#define MCHP_VCI_NDET_IN2 0x04u +#define MCHP_VCI_NDET_IN3 0x08u +#define MCHP_VCI_NDET_IN4 0x10u + +/* VCI Buffer Enable register */ +#define MCHP_VCI_BEN_REG_OFS 0x20u +#define MCHP_VCI_BEN_REG_MASK 0x7Ful +#define MCHP_VCI_BEN_IE30_MASK 0x0Fu +#define MCHP_VCI_BEN_IN0 0x01u +#define MCHP_VCI_BEN_IN1 0x02u +#define MCHP_VCI_BEN_IN2 0x04u +#define MCHP_VCI_BEN_IN3 0x08u +#define MCHP_VCI_BEN_IN4 0x10u + +#endif /* #ifndef _COMPONENT_VBAT_H */ +/* end vbat.h */ +/** @} + */ diff --git a/mec/mec172x/component/wdt.h b/mec/mec172x/component/wdt.h new file mode 100644 index 0000000..f1fde18 --- /dev/null +++ b/mec/mec172x/component/wdt.h @@ -0,0 +1,133 @@ +/** + * + * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/** @file wdt.h + * MEC172x Watch Dog Timer Registers + */ +/** @defgroup MEC172x Peripherals WDT + */ + +#ifndef _COMPONENT_WDT_H +#define _COMPONENT_WDT_H + +#include +#include + +#include +#include + +/* =========================================================================*/ +/* ================ WDT ====================*/ +/* =========================================================================*/ + +#define MCHP_WDT_BASE_ADDR 0x40000400ul + +/* WDT Interrupt */ +#define MCHP_WDT_GIRQ 21u +#define MCHP_WDT_GIRQ_NVIC 13u +#define MCHP_WDT_GIRQ_NVIC_DIRECT 171u + +/* Bit position in Interrupt Aggregator GIRQ registers */ +#define MCHP_WDT_GIRQ_POS 2u + +/* Interrupt Aggregator Source, Enable Set/Clear registers value */ +#define MCHP_WDT_GIRQ_VAL BIT(MCHP_WDT_GIRQ_POS) + + +/* Load register */ +#define MCHP_WDT_LOAD_REG_OFS 0x00ul +#define MCHP_WDT_LOAD_REG_MASK 0xFFFFul + +/* Control register */ +#define MCHP_WDT_CTRL_REG_OFS 0x04ul +#define MCHP_WDT_CTRL_REG_MASK 0x021Dul +#define MCHP_WDT_CTRL_EN_POS 0u +#define MCHP_WDT_CTRL_EN_MASK BIT(MCHP_WDT_CTRL_EN_POS) +#define MCHP_WDT_CTRL_EN BIT(MCHP_WDT_CTRL_EN_POS) +#define MCHP_WDT_CTRL_HTMR_STALL_POS 2u +#define MCHP_WDT_CTRL_HTMR_STALL_MASK BIT(MCHP_WDT_CTRL_HTMR_STALL_POS) +#define MCHP_WDT_CTRL_HTMR_STALL_EN BIT(MCHP_WDT_CTRL_HTMR_STALL_POS) +#define MCHP_WDT_CTRL_WKTMR_STALL_POS 3u +#define MCHP_WDT_CTRL_WKTMR_STALL_MASK BIT(MCHP_WDT_CTRL_WKTMR_STALL_POS) +#define MCHP_WDT_CTRL_WKTMR_STALL_EN BIT(MCHP_WDT_CTRL_WKTMR_STALL_POS) +#define MCHP_WDT_CTRL_JTAG_STALL_POS 4u +#define MCHP_WDT_CTRL_JTAG_STALL_MASK BIT(MCHP_WDT_CTRL_JTAG_STALL_POS) +#define MCHP_WDT_CTRL_JTAG_STALL_EN BIT(MCHP_WDT_CTRL_JTAG_STALL_POS) +/* + * WDT mode selecting action taken upon count expiration. + * 0 = Generate chip reset + * 1 = Clear this bit, + * Set event status + * Generate interrupt if event IEN bit is set + * Kick WDT causing it to reload from LOAD register + * If interrupt is enabled in GIRQ21 and NVIC then the EC will jump + * to the WDT ISR. + */ +#define MCHP_WDT_CTRL_MODE_POS 9u +#define MCHP_WDT_CTRL_MODE_MASK BIT(MCHP_WDT_CTRL_MODE_POS) +#define MCHP_WDT_CTRL_MODE_RESET 0ul +#define MCHP_WDT_CTRL_MODE_IRQ BIT(MCHP_WDT_CTRL_MODE_POS) + +/* WDT Kick register. Write any value to reload counter */ +#define MCHP_WDT_KICK_REG_OFS 0x08ul +#define MCHP_WDT_KICK_REG_MASK 0xFFul +#define MCHP_WDT_KICK_VAL 0 + +/* WDT Count register. Read only */ +#define MCHP_WDT_CNT_RO_REG_OFS 0x0Cul +#define MCHP_WDT_CNT_RO_REG_MASK 0xFFFFul + +/* Status Register */ +#define MCHP_WDT_STS_REG_OFS 0x10ul +#define MCHP_WDT_STS_REG_MASK 0x01ul +#define MCHP_WDT_STS_EVENT_IRQ_POS 0u +#define MCHP_WDT_STS_EVENT_IRQ BIT(MCHP_WDT_STS_EVENT_IRQ_POS) + +/* Interrupt Enable Register */ +#define MCHP_WDT_IEN_REG_OFS 0x14ul +#define MCHP_WDT_IEN_REG_MASK 0x01ul +#define MCHP_WDT_IEN_EVENT_IRQ_POS 0u +#define MCHP_WDT_IEN_EVENT_IRQ_MASK BIT(MCHP_WDT_IEN_EVENT_IRQ_POS) +#define MCHP_WDT_IEN_EVENT_IRQ_EN BIT(MCHP_WDT_IEN_EVENT_IRQ_POS) + +/* Register access */ +#define MCHP_WDT_LOAD_REG_ADDR (MCHP_WDT_BASE_ADDR + MCHP_WDT_LOAD_REG_OFS) +#define MCHP_WDT_CTRL_REG_ADDR (MCHP_WDT_BASE_ADDR + MCHP_WDT_CTRL_REG_OFS) +#define MCHP_WDT_KICK_REG_ADDR (MCHP_WDT_BASE_ADDR + MCHP_WDT_KICK_REG_OFS) +#define MCHP_WDT_STS_REG_ADDR (MCHP_WDT_BASE_ADDR + MCHP_WDT_STS_REG_OFS) +#define MCHP_WDT_IEN_REG_ADDR (MCHP_WDT_BASE_ADDR + MCHP_WDT_IEN_REG_OFS) + +#define MCHP_WDT_LOAD() REG16(MCHP_WDT_LOAD_REG_ADDR) +#define MCHP_WDT_CTRL() REG16(MCHP_WDT_CTRL_REG_ADDR) +#define MCHP_WDT_KICK() REG8(MCHP_WDT_KICK_REG_ADDR) +#define MCHP_WDT_CNT() REG16(MCHP_WDT_CNT_REG_ADDR) +#define MCHP_WDT_STS() REG8(MCHP_WDT_STS_REG_ADDR) +#define MCHP_WDT_IEN() REG8(MCHP_WDT_IEN_REG_ADDR) + +#endif /* #ifndef _COMPONENT_WDT_H */ +/* end wdt.h */ +/** @} + */