RSS: Add SIC MPC

Change-Id: Ie2e0be4f9e3cb72a457425566eec07d49015f5a6
Signed-off-by: Raef Coles <[email protected]>

Author: RcColes

platform/ext/target/arm/rss/common/cmsis_drivers/Driver_MPC.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2016-2023 Arm Limited. All rights reserved.
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -342,3 +342,143 @@ ARM_DRIVER_MPC Driver_VM1_MPC = {
     .LockDown         = VM1_MPC_LockDown,
 };
 #endif /* RTE_VM1_MPC */
+
+#if (RTE_SIC_MPC)
+/* Ranges controlled by this SIC_MPC */
+static const struct mpc_sie_memory_range_t MPC_SIC_RANGE_S = {
+    .base         = MPC_SIC_RANGE_BASE_S,
+    .limit        = MPC_SIC_RANGE_LIMIT_S,
+    .range_offset = 0,
+    .attr         = MPC_SIE_SEC_ATTR_SECURE
+};
+
+static const struct mpc_sie_memory_range_t MPC_SIC_RANGE_NS = {
+    .base         = MPC_SIC_RANGE_BASE_NS,
+    .limit        = MPC_SIC_RANGE_LIMIT_NS,
+    .range_offset = 0,
+    .attr         = MPC_SIE_SEC_ATTR_NONSECURE
+};
+
+#define MPC_SIC_RANGE_LIST_LEN  2u
+static const struct mpc_sie_memory_range_t*
+    MPC_SIC_RANGE_LIST[MPC_SIC_RANGE_LIST_LEN] = {
+        &MPC_SIC_RANGE_S,
+        &MPC_SIC_RANGE_NS
+    };
+
+/* SIC_MPC Driver wrapper functions */
+static int32_t SIC_MPC_Initialize(void)
+{
+    enum mpc_sie_error_t ret;
+
+    ret = mpc_sie_init(&MPC_SIC_DEV,
+                       MPC_SIC_RANGE_LIST,
+                       MPC_SIC_RANGE_LIST_LEN);
+
+    return error_trans(ret);
+}
+
+static int32_t SIC_MPC_Uninitialize(void)
+{
+    /* Nothing to be done */
+    return ARM_DRIVER_OK;
+}
+
+static int32_t SIC_MPC_GetBlockSize(uint32_t *blk_size)
+{
+    enum mpc_sie_error_t ret;
+
+    ret = mpc_sie_get_block_size(&MPC_SIC_DEV, blk_size);
+
+    return error_trans(ret);
+}
+
+static int32_t SIC_MPC_GetCtrlConfig(uint32_t *ctrl_val)
+{
+    enum mpc_sie_error_t ret;
+
+    ret = mpc_sie_get_ctrl(&MPC_SIC_DEV, ctrl_val);
+
+    return error_trans(ret);
+}
+
+static int32_t SIC_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+    enum mpc_sie_error_t ret;
+
+    ret = mpc_sie_set_ctrl(&MPC_SIC_DEV, ctrl);
+
+    return error_trans(ret);
+}
+
+static int32_t SIC_MPC_GetRegionConfig(uintptr_t base,
+                                       uintptr_t limit,
+                                       ARM_MPC_SEC_ATTR *attr)
+{
+    enum mpc_sie_error_t ret;
+
+    ret = mpc_sie_get_region_config(&MPC_SIC_DEV, base, limit,
+                                    (enum mpc_sie_sec_attr_t*)attr);
+
+    return error_trans(ret);
+}
+
+static int32_t SIC_MPC_ConfigRegion(uintptr_t base,
+                                    uintptr_t limit,
+                                    ARM_MPC_SEC_ATTR attr)
+{
+    enum mpc_sie_error_t ret;
+
+    ret = mpc_sie_config_region(&MPC_SIC_DEV, base, limit,
+                                (enum mpc_sie_sec_attr_t)attr);
+
+    return error_trans(ret);
+}
+
+static int32_t SIC_MPC_EnableInterrupt(void)
+{
+    enum mpc_sie_error_t ret;
+
+    ret = mpc_sie_irq_enable(&MPC_SIC_DEV);
+
+    return error_trans(ret);
+}
+
+static void SIC_MPC_DisableInterrupt(void)
+{
+    mpc_sie_irq_disable(&MPC_SIC_DEV);
+}
+
+
+static void SIC_MPC_ClearInterrupt(void)
+{
+    mpc_sie_clear_irq(&MPC_SIC_DEV);
+}
+
+static uint32_t SIC_MPC_InterruptState(void)
+{
+    return mpc_sie_irq_state(&MPC_SIC_DEV);
+}
+
+static int32_t SIC_MPC_LockDown(void)
+{
+    return mpc_sie_lock_down(&MPC_SIC_DEV);
+}
+
+/* SIC_MPC Driver CMSIS access structure */
+ARM_DRIVER_MPC Driver_SIC_MPC = {
+    .GetVersion       = ARM_MPC_GetVersion,
+    .Initialize       = SIC_MPC_Initialize,
+    .Uninitialize     = SIC_MPC_Uninitialize,
+    .GetBlockSize     = SIC_MPC_GetBlockSize,
+    .GetCtrlConfig    = SIC_MPC_GetCtrlConfig,
+    .SetCtrlConfig    = SIC_MPC_SetCtrlConfig,
+    .ConfigRegion     = SIC_MPC_ConfigRegion,
+    .GetRegionConfig  = SIC_MPC_GetRegionConfig,
+    .EnableInterrupt  = SIC_MPC_EnableInterrupt,
+    .DisableInterrupt = SIC_MPC_DisableInterrupt,
+    .ClearInterrupt   = SIC_MPC_ClearInterrupt,
+    .InterruptState   = SIC_MPC_InterruptState,
+    .LockDown         = SIC_MPC_LockDown,
+};
+#endif /* RTE_SIC_MPC */

platform/ext/target/arm/rss/common/cmsis_drivers/config/RTE_Device.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023 Arm Limited. All rights reserved.
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -31,6 +31,12 @@
 // <i> Configuration settings for Driver_VM1_MPC in component ::Drivers:MPC
 #define   RTE_VM1_MPC                 1
 
+// <q> MPC (Memory Protection Controller) [Driver_SIC_MPC]
+// <i> Configuration settings for Driver_SIC_MPC in component ::Drivers:MPC
+#ifdef RSS_XIP
+#define   RTE_SIC_MPC                 1
+#endif /* RSS_XIP */
+
 // <q> PPC (Peripheral Protection Controller) [PPC_RSS_MAIN0]
 // <i> Configuration settings for Driver_PPC_RSS_MAIN0 in component ::Drivers:PPC
 #define   RTE_PPC_RSS_MAIN0             1

platform/ext/target/arm/rss/common/cmsis_drivers/config/cmsis_driver_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023 Arm Limited. All rights reserved.
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -27,6 +27,9 @@
 
 #define MPC_VM0_DEV                  MPC_VM0_DEV_S
 #define MPC_VM1_DEV                  MPC_VM1_DEV_S
+#ifdef RSS_XIP
+#define MPC_SIC_DEV                  MPC_SIC_DEV_S
+#endif /* RSS_XIP */
 
 #define PPC_RSS_MAIN0_DEV            PPC_RSS_MAIN0_DEV_S
 #define PPC_RSS_MAIN_EXP0_DEV        PPC_RSS_MAIN_EXP0_DEV_S

platform/ext/target/arm/rss/common/device/config/device_cfg.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023 Arm Limited. All rights reserved.
  *
  * Licensed under the Apache License Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -29,6 +29,9 @@
 /* ARM Memory Protection Controller (MPC) */
 #define MPC_VM0_S
 #define MPC_VM1_S
+#ifdef RSS_XIP
+#define MPC_SIC_S
+#endif /* RSS_XIP */
 
 /* ARM Peripheral Protection Controllers (PPC) */
 #define PPC_RSS_MAIN0_S

platform/ext/target/arm/rss/common/device/include/device_definition.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023 Arm Limited. All rights reserved.
  *
  * Licensed under the Apache License Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -181,6 +181,11 @@ extern struct mpc_sie_dev_t MPC_VM0_DEV_S;
 extern struct mpc_sie_dev_t MPC_VM1_DEV_S;
 #endif
 
+#ifdef MPC_SIC_S
+#include "mpc_sie_drv.h"
+extern struct mpc_sie_dev_t MPC_SIC_DEV_S;
+#endif
+
 /* Message Handling Units (MHU) */
 #ifdef MHU_AP_TO_RSS
 #include "mhu_v2_x.h"

platform/ext/target/arm/rss/common/device/source/device_definition.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023 Arm Limited. All rights reserved.
  *
  * Licensed under the Apache License Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -440,6 +440,18 @@ struct mpc_sie_dev_t MPC_VM1_DEV_S = {
     &(MPC_VM1_DEV_DATA_S)};
 #endif
 
+#ifdef MPC_SIC_S
+static const struct mpc_sie_dev_cfg_t MPC_SIC_DEV_CFG_S = {
+    .base = MPC_SIC_BASE_S};
+static struct mpc_sie_dev_data_t MPC_SIC_DEV_DATA_S = {
+    .range_list = 0,
+    .nbr_of_ranges = 0,
+    .is_initialized = false };
+struct mpc_sie_dev_t MPC_SIC_DEV_S = {
+    &(MPC_SIC_DEV_CFG_S),
+    &(MPC_SIC_DEV_DATA_S)};
+#endif
+
 /* Message Handling Units (MHU) */
 #ifdef MHU_AP_TO_RSS
 struct mhu_v2_x_dev_t MHU_AP_TO_RSS_DEV = {

platform/ext/target/arm/rss/common/partition/platform_base_address.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022 Arm Limited
+ * Copyright (c) 2019-2023 Arm Limited
  *
  * Licensed under the Apache License Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -93,6 +93,7 @@
 #define GPIO1_CMSDK_BASE_S               0x50101000 /* GPIO 1 Secure base address */
 #define SIC_BASE_S                       0x50140000 /* SIC Secure base address */
 #define ATU_BASE_S                       0x50150000 /* ATU Secure base address */
+#define MPC_SIC_BASE_S                   0x50151000 /* SIC Memory Protection Controller Secure base address */
 #define SYSCNTR_CNTRL_BASE_S             0x5015A000 /* System Counter Control Secure base address */
 #define SYSCNTR_READ_BASE_S              0x5015B000 /* System Counter Read Secure base address */
 #define MHU0_SENDER_BASE_S               0x50160000 /* Combined MHU 0 Sender Secure base address */
@@ -173,4 +174,12 @@
 #define MPC_VM1_RANGE_LIMIT_S            (VM1_BASE_S + VM1_SIZE-1)
 #define MPC_VM1_RANGE_OFFSET_S           (0x0)
 
+/* SIC -- 1 MiB */
+#define MPC_SIC_RANGE_BASE_NS            (SIC_HOST_BASE_NS)
+#define MPC_SIC_RANGE_LIMIT_NS           (SIC_HOST_BASE_NS + SIC_MAPPABLE_SIZE-1)
+#define MPC_SIC_RANGE_OFFSET_NS          (0x0)
+#define MPC_SIC_RANGE_BASE_S             (SIC_HOST_BASE_S)
+#define MPC_SIC_RANGE_LIMIT_S            (SIC_HOST_BASE_S + SIC_MAPPABLE_SIZE-1)
+#define MPC_SIC_RANGE_OFFSET_S           (0x0)
+
 #endif  /* __PLATFORM_BASE_ADDRESS_H__ */

platform/ext/target/arm/rss/common/target_cfg.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023 Arm Limited. All rights reserved.
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -92,6 +92,7 @@ const struct dma350_remap_list_t dma350_address_remap = {
 /* Import MPC drivers */
 extern ARM_DRIVER_MPC Driver_VM0_MPC;
 extern ARM_DRIVER_MPC Driver_VM1_MPC;
+extern ARM_DRIVER_MPC Driver_SIC_MPC;
 
 /* Import PPC drivers */
 extern DRIVER_PPC_RSS Driver_PPC_RSS_MAIN0;