dts: mimxrt685s/hifi4: Reorganise memory layout

Rework linker file for mimxrt685s/hifi4 - clarify region names, fix
nonsensical text region size. Move hifi4 data and text regions from
ITCM/DTCM to the main SRAM (partitions 28 and 29). Modify load regions
and cut memory allocation for mimxrt685s/cm33 to prevent overlaps. Move
intList section before mimxrt685s/hifi4's ITCM to prevent output image
size inflation (with fill bytes).

This change was motivated by the DSP's ITCM and DTCM not being big
enough for Zephyr audio applications.

Signed-off-by: Vit Stanicek <[email protected]>

Author: VitekST

dts/arm/nxp/nxp_rt6xx_common.dtsi

@@ -60,20 +60,20 @@
 
 			status = "disabled";
 
-			region@24000000 {
-				reg = <0x24000000 DT_SIZE_K(64)>;
-				type = <NXP_RTXXX_ADSP_REGION_DATA>;
-			};
-
 			region@24020000 {
 				reg = <0x24020000 DT_SIZE_K(1)>;
 				type = <NXP_RTXXX_ADSP_REGION_RESET>;
 			};
 
-			region@24020400 {
-				reg = <0x24020400 DT_SIZE_K(63)>;
+			region@20400000 {
+				reg = <0x20400000 DT_SIZE_K(256)>;
 				type = <NXP_RTXXX_ADSP_REGION_TEXT>;
 			};
+
+			region@20440000 {
+				reg = <0x20440000 DT_SIZE_K(256)>;
+				type = <NXP_RTXXX_ADSP_REGION_DATA>;
+			};
 		};
 	};
 };
@@ -98,7 +98,7 @@
 
 	sram0: memory@180000 {
 		compatible = "mmio-sram";
-		reg = <0x180000 DT_SIZE_K(3072)>;
+		reg = <0x180000 DT_SIZE_K(2560)>;
 	};
 
 	sram1: memory@40140000 {

dts/xtensa/nxp/nxp_rt685_hifi4.dtsi

@@ -49,10 +49,6 @@
 			adsp_reset: memory@24020000 {
 				reg = <0x24020000 DT_SIZE_K(1)>;
 			};
-
-			adsp_text: memory@24020400 {
-				reg = <0x24020400 DT_SIZE_K(63)>;
-			};
 		};
 
 		dtcm: memory@24000000 {
@@ -62,9 +58,31 @@
 			compatible = "mmio-sram";
 
 			reg = <0x24000000 DT_SIZE_K(64)>;
+		};
+
+		ram0_cached: memory@200000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			device_type = "memory";
+			compatible = "mmio-sram";
+
+			reg = <0x00200000 DT_SIZE_K(512)>;
+		};
+
+		ram0_noncached: memory@20400000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			device_type = "memory";
+			compatible = "mmio-sram";
+
+			reg = <0x20400000 DT_SIZE_K(512)>;
+
+			adsp_text: memory@20400000 {
+				reg = <0x20400000 DT_SIZE_K(256)>;
+			};
 
-			adsp_data: memory@24000000 {
-				reg = <0x24000000 DT_SIZE_K(64)>;
+			adsp_data: memory@20440000 {
+				reg = <0x20440000 DT_SIZE_K(256)>;
 			};
 		};
 

soc/nxp/imxrt/imxrt6xx/hifi4/include/soc/memory.h

@@ -10,19 +10,19 @@
 
 #include <autoconf.h>
 
-#define IRAM_BASE (CONFIG_RT685_ADSP_TEXT_MEM_ADDR)
-#define IRAM_SIZE (CONFIG_RT685_ADSP_TEXT_MEM_SIZE)
+#define TEXT_BASE (CONFIG_RT685_ADSP_TEXT_MEM_ADDR)
+#define TEXT_SIZE (CONFIG_RT685_ADSP_TEXT_MEM_SIZE)
 
-#define SDRAM0_BASE (CONFIG_RT685_ADSP_DATA_MEM_ADDR)
-#define SDRAM0_SIZE (CONFIG_RT685_ADSP_DATA_MEM_SIZE - CONFIG_RT685_ADSP_STACK_SIZE)
+#define DATA_BASE (CONFIG_RT685_ADSP_DATA_MEM_ADDR)
+#define DATA_SIZE (CONFIG_RT685_ADSP_DATA_MEM_SIZE - CONFIG_RT685_ADSP_STACK_SIZE)
 
 /* The reset vector address in SRAM and its size. */
 #define XCHAL_RESET_VECTOR0_PADDR_IRAM (CONFIG_RT685_ADSP_RESET_MEM_ADDR)
 #define MEM_RESET_TEXT_SIZE            (0x2e0)
 #define MEM_RESET_LIT_SIZE             (0x120)
 
 /* Base address of all interrupt vectors in IRAM. */
-#define XCHAL_VECBASE_RESET_PADDR_IRAM (IRAM_BASE)
+#define XCHAL_VECBASE_RESET_PADDR_IRAM (TEXT_BASE)
 #define MEM_VECBASE_LIT_SIZE           (0x178)
 
 /* Vector and literal sizes. */
@@ -39,13 +39,13 @@
 #define XCHAL_USER_VECTOR_PADDR_IRAM      (XCHAL_INT_VECTOR_ADDR(0x21C))
 #define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x23C))
 
-/* Location for the intList section which is later used to construct the
+
+/* Size and location of the intList section. Later used to construct the
  * Interrupt Descriptor Table (IDT). This is a bogus address as this
- * section will be stripped off in the final image.
+ * section will be stripped off in the final image. Situated before the DSP's
+ * ITCM - prevents memory region inflation in zephyr_pre0.elf.
  */
-#define IDT_BASE (IRAM_BASE + IRAM_SIZE)
-
-/* Size of the Interrupt Descriptor Table (IDT). */
 #define IDT_SIZE (0x2000)
+#define IDT_BASE (CONFIG_RT685_ADSP_RESET_MEM_ADDR - IDT_SIZE)
 
 #endif

soc/nxp/imxrt/imxrt6xx/hifi4/linker.ld

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,8 +13,8 @@ OUTPUT_ARCH(xtensa)
 #include <zephyr/linker/linker-tool.h>
 #include <zephyr/linker/sections.h>
 
-#define RAMABLE_REGION sdram0 :sdram0_phdr
-#define ROMABLE_REGION sdram0 :sdram0_phdr
+#define RAMABLE_REGION adsp_data :adsp_data_phdr
+#define ROMABLE_REGION adsp_data :adsp_data_phdr
 
 MEMORY
 {
@@ -69,12 +69,12 @@ MEMORY
   vector_double_text :
     org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM,
     len = MEM_VECT_TEXT_SIZE
-  iram_text_start :
+  adsp_text :
     org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE,
-    len = (IRAM_BASE + IRAM_SIZE) - (XCHAL_DOUBLEEXC_VECTOR_PADDR + MEM_VECT_TEXT_SIZE)
-  sdram0 :
-    org = SDRAM0_BASE,
-    len = SDRAM0_SIZE
+    len = TEXT_SIZE - MEM_VECT_TEXT_SIZE
+  adsp_data :
+    org = DATA_BASE,
+    len = DATA_SIZE
 #ifdef CONFIG_GEN_ISR_TABLES
   IDT_LIST :
     org = IDT_BASE,
@@ -102,8 +102,8 @@ PHDRS
   vector_user_lit_phdr PT_LOAD;
   vector_double_text_phdr PT_LOAD;
   vector_double_lit_phdr PT_LOAD;
-  iram_text_start_phdr PT_LOAD;
-  sdram0_phdr PT_LOAD;
+  adsp_text_phdr PT_LOAD;
+  adsp_data_phdr PT_LOAD;
 }
 
 PROVIDE(_memmap_reset_vector = XCHAL_RESET_VECTOR0_PADDR_IRAM);
@@ -259,7 +259,7 @@ SECTIONS
     _iram_text_start = ABSOLUTE(.);
     *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
     _iram_text_end = ABSOLUTE(.);
-  } >iram_text_start :iram_text_start_phdr
+  } >adsp_text :adsp_text_phdr
 
   .rodata : ALIGN(4)
   {
@@ -295,14 +295,14 @@ SECTIONS
     LONG(_bss_end)
     _bss_table_end = ABSOLUTE(.);
     __rodata_region_end = ABSOLUTE(.);
-  } >sdram0 :sdram0_phdr
+  } >adsp_data :adsp_data_phdr
 
   .module_init : ALIGN(4)
   {
    _module_init_start = ABSOLUTE(.);
     *(*.initcall)
     _module_init_end = ABSOLUTE(.);
-  } >sdram0 :sdram0_phdr
+  } >adsp_data :adsp_data_phdr
 
   .text : ALIGN(4)
   {
@@ -319,21 +319,21 @@ SECTIONS
     *(.gnu.version)
     _text_end = ABSOLUTE(.);
     _etext = .;
-  } >iram_text_start :iram_text_start_phdr
+  } >adsp_text :adsp_text_phdr
 
 #include <zephyr/linker/common-rom.ld>
 
   .fw_ready : ALIGN(4)
   {
     KEEP(*(".fw_ready"));
     KEEP (*(.fw_ready_metadata))
-  } >sdram0 :sdram0_phdr
+  } >adsp_data :adsp_data_phdr
 
   .noinit : ALIGN(4)
   {
     *(.noinit)
     *(.noinit.*)
-  } >sdram0 :sdram0_phdr
+  } >adsp_data :adsp_data_phdr
 
   .data : ALIGN(4)
   {
@@ -357,7 +357,7 @@ SECTIONS
     *(.gna_model)
     __data_end = ABSOLUTE(.);
     . = ALIGN(4096);
-  } >sdram0 :sdram0_phdr
+  } >adsp_data :adsp_data_phdr
 
   .lit4 : ALIGN(4)
   {
@@ -366,7 +366,7 @@ SECTIONS
     *(.lit4.*)
     *(.gnu.linkonce.lit4.*)
     _lit4_end = ABSOLUTE(.);
-  } >sdram0 :sdram0_phdr
+  } >adsp_data :adsp_data_phdr
 
 #include <zephyr/linker/common-ram.ld>
 
@@ -389,7 +389,7 @@ SECTIONS
     *(COMMON)
     . = ALIGN (8);
     _bss_end = ABSOLUTE(.);
-  } >sdram0 :sdram0_phdr
+  } >adsp_data :adsp_data_phdr
 
   .heap_mem (NOLOAD) : ALIGN(8)
   {
@@ -398,14 +398,14 @@ SECTIONS
     *(*.heap_mem)
     _heap_mem_end = ABSOLUTE(.);
 
-  } >sdram0 :sdram0_phdr
+  } >adsp_data :adsp_data_phdr
 
   /* stack */
   _end = ALIGN (8);
 
   /DISCARD/ : { *(.note.GNU-stack) }
-  _heap_sentry = SDRAM0_BASE + SDRAM0_SIZE;
-  __stack = SDRAM0_BASE + SDRAM0_SIZE;
+  _heap_sentry = DATA_BASE + DATA_SIZE;
+  __stack = DATA_BASE + DATA_SIZE;
   .comment  0 :  { *(.comment) }
   .debug  0 :  { *(.debug) }
   .line  0 :  { *(.line) }