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dcpleungnashif
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soc: intel_adsp/ace: fix condition to check core power bit
The conditionals to check if the CPA bit is already set or cleared are incorrect. This results in the code always asserting. So fix those. Signed-off-by: Daniel Leung <[email protected]>
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soc/xtensa/intel_adsp/ace/multiprocessing.c

+9-4
Original file line numberDiff line numberDiff line change
@@ -63,11 +63,13 @@ void soc_start_core(int cpu_num)
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DFDSPBRCP.capctl[cpu_num].ctl |= DFDSPBRCP_CTL_SPA;
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/* Waiting for power up */
66-
while (~(DFDSPBRCP.capctl[cpu_num].ctl & DFDSPBRCP_CTL_CPA) && --retry) {
66+
while (((DFDSPBRCP.capctl[cpu_num].ctl & DFDSPBRCP_CTL_CPA) != DFDSPBRCP_CTL_CPA) &&
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(retry > 0)) {
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k_busy_wait(HW_STATE_CHECK_DELAY);
69+
retry--;
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}
6971

70-
if (!retry) {
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if (retry == 0) {
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__ASSERT(false, "%s secondary core has not powered up", __func__);
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}
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}
@@ -118,10 +120,13 @@ int soc_adsp_halt_cpu(int id)
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DFDSPBRCP.capctl[id].ctl &= ~DFDSPBRCP_CTL_SPA;
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/* Waiting for power off */
121-
while (DFDSPBRCP.capctl[id].ctl & DFDSPBRCP_CTL_CPA && --retry)
123+
while (((DFDSPBRCP.capctl[id].ctl & DFDSPBRCP_CTL_CPA) == DFDSPBRCP_CTL_CPA) &&
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(retry > 0)) {
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k_busy_wait(HW_STATE_CHECK_DELAY);
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retry--;
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}
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124-
if (!retry) {
129+
if (retry == 0) {
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__ASSERT(false, "%s secondary core has not powered down", __func__);
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return -EINVAL;
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}

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