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boards: arm: Introduce Google Dragonclaw Development Board
Dragonclaw is a board created by Google for fingerprint-related functionality development. Board schematics, layout and BOM is available at: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/docs/schematics/dragonclaw Signed-off-by: Patryk Duda <[email protected]>
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‎boards/arm/google_dragonclaw/Kconfig.board

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# Copyright (c) 2022 Google LLC
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_GOOGLE_DRAGONCLAW
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bool "Google Dragonclaw Development Board"
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depends on SOC_STM32F412CX

‎boards/arm/google_dragonclaw/Kconfig.defconfig

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# Copyright (c) 2022 Google LLC
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_GOOGLE_DRAGONCLAW
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config BOARD
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default "google_dragonclaw"
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endif # BOARD_GOOGLE_DRAGONCLAW

‎boards/arm/google_dragonclaw/board.cmake

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# Copyright (c) 2022 Google LLC
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(jlink "--device=STM32F412CG" "--speed=4000")
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

‎boards/arm/google_dragonclaw/doc/index.rst

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.. _google_dragonclaw_board:
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Google Dragonclaw Development Board
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###################################
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Overview
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********
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Dragonclaw is a board created by Google for fingerprint-related functionality
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development. See the `Dragonclaw Schematics`_ for board schematics, layout and
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BOM.
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Board has connectors for fingerprint sensors. Console is exposed over μServo
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connector. MCU can be flashed using μServo or SWD.
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Hardware
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********
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- STM32F412CGU6 UFQFPN48 package
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Peripherial Mapping
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===================
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- USART_1 TX/RX : PA9/PA10
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- USART_2 TX/RX : PA2/PA3
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- SPI_1 CS/CLK/MISO/MOSI : PA4/PA5/PA6/PA7
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- SPI_2 CS/CLK/MISO/MOSI : PB12/PB13/PB14/PB15
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Programming and Debugging
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*************************
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Build application as usual for the ``dragonclaw`` board, and flash
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using μServo or an external J-Link connected to J4. If μServo is used, please
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follow the `Chromium EC Flashing Documentation`_.
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Debugging
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=========
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Use SWD with a J-Link or ST-Link. Remember that SW2 must be set to CORESIGHT.
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References
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**********
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.. target-notes::
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.. _Dragonclaw Schematics:
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https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/docs/schematics/dragonclaw
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.. _Chromium EC Flashing Documentation:
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https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board

‎boards/arm/google_dragonclaw/google_dragonclaw.dts

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/*
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* Copyright (c) 2022 Google LLC
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <st/f4/stm32f412Xg.dtsi>
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#include <st/f4/stm32f412z(e-g)tx-pinctrl.dtsi>
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/ {
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model = "Google Dragonclaw development board";
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compatible = "google,dragonclaw-fpmcu";
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chosen {
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zephyr,console = &usart2;
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zephyr,shell-uart = &usart2;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,flash-controller = &flash;
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};
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};
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&clk_hsi {
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/* HSI clock frequency is 16MHz */
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status = "okay";
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};
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&clk_lsi {
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/* LSI clock frequency is 32768kHz */
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status = "okay";
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};
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&pll {
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div-m = <8>;
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mul-n = <192>; /* 16MHz * 192/8 = 384MHz VCO clock */
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div-p = <4>; /* 96MHz PLL general clock output */
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div-q = <8>; /* 48MHz PLL output for USB, SDIO, RNG */
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clocks = <&clk_hsi>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>; /* Select PLL as SYSCLK source (96MHz) */
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ahb-prescaler = <1>; /* SYSCLK not divided */
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clock-frequency = <DT_FREQ_M(96)>; /* AHB frequency */
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apb1-prescaler = <2>; /* AHB clock divided by 2 */
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apb2-prescaler = <2>; /* AHB clock divided by 2 */
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};
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/* USART1: AP UART (Host Commands and MKBP) */
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&usart1 {
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pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
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pinctrl-names = "default";
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current-speed = <115200>;
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status = "okay";
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};
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/* USART2: Servo UART (console) */
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&usart2 {
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pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
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pinctrl-names = "default";
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current-speed = <115200>;
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status = "okay";
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};
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/* SPI1: communication with the AP */
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&spi1 {
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pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5
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&spi1_miso_pa6 &spi1_mosi_pa7>;
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pinctrl-names = "default";
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status = "okay";
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};
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/* SPI2: communication with the fingerprint sensor */
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&spi2 {
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pinctrl-0 = <&spi2_nss_pb12 &spi2_sck_pb13
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&spi2_miso_pb14 &spi2_mosi_pb15>;
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pinctrl-names = "default";
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status = "okay";
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};
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&rtc {
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
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<&rcc STM32_SRC_LSI RTC_SEL(2)>;
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status = "okay";
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backup_regs {
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status = "okay";
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};
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};
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/*
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* The board uses STM32F412CG in UFQFPN48 package in which gpio[c-h] is not
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* exposed, so disable it.
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*/
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&gpioc {status = "disabled";};
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&gpiod {status = "disabled";};
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&gpioe {status = "disabled";};
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&gpiof {status = "disabled";};
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&gpiog {status = "disabled";};
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&gpioh {status = "disabled";};

‎boards/arm/google_dragonclaw/google_dragonclaw.yaml

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identifier: google_dragonclaw
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name: Google Dragonclaw Development Board
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type: mcu
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arch: arm
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toolchain:
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- zephyr
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- gnuarmemb
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- xtools
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ram: 256
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flash: 1024

‎boards/arm/google_dragonclaw/google_dragonclaw_defconfig

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# Copyright (c) 2022 Google Inc
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SOC_SERIES_STM32F4X=y
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CONFIG_SOC_STM32F412CX=y
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CONFIG_BOARD_GOOGLE_DRAGONCLAW=y
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# Serial Drivers
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CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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# Console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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# GPIO Controller
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CONFIG_GPIO=y
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# Clock Controller
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CONFIG_CLOCK_CONTROL=y
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# Pin Controller
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CONFIG_PINCTRL=y
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# Enable MPU and HW stack protection
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CONFIG_ARM_MPU=y
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CONFIG_HW_STACK_PROTECTION=y

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