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AlessandroLuoAlessandroLuo
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dts: power: ambiq: change to use ambiq HAL to do power-on config
Changed to use ambiq HAL to do power-on config, no need to bind pwrcfg any more Signed-off-by: Hao Luo <[email protected]>
1 parent 276d447 commit 239b33e

8 files changed

+7
-109
lines changed

‎drivers/serial/uart_pl011_ambiq.h

+6-36
Original file line numberDiff line numberDiff line change
@@ -158,48 +158,18 @@ static int uart_ambiq_pm_action(const struct device *dev, enum pm_device_action
158158
}
159159
#endif /* CONFIG_PM_DEVICE */
160160

161-
/* Problem: writes to power configure register takes some time to take effective.
162-
* Solution: Check device's power status to ensure that register has taken effective.
163-
* Note: busy wait is not allowed to use here due to UART is initiated before timer starts.
164-
*/
165-
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
166-
#define DEVPWRSTATUS_OFFSET 0x10
167-
#define HCPA_MASK 0x4
168-
#define AMBIQ_UART_DEFINE(n) \
169-
PM_DEVICE_DT_INST_DEFINE(n, uart_ambiq_pm_action); \
170-
static int pwr_on_ambiq_uart_##n(void) \
171-
{ \
172-
uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
173-
DT_INST_PHA(n, ambiq_pwrcfg, offset); \
174-
uint32_t pwr_status_addr = addr + DEVPWRSTATUS_OFFSET; \
175-
sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
176-
while (!(sys_read32(pwr_status_addr) & HCPA_MASK)) { \
177-
}; \
178-
return 0; \
179-
} \
180-
static inline int clk_enable_ambiq_uart_##n(const struct device *dev, uint32_t clk) \
181-
{ \
182-
return clk_enable_ambiq_uart(dev, clk); \
183-
}
184-
#else
185-
#define DEVPWRSTATUS_OFFSET 0x4
186-
#define AMBIQ_UART_DEFINE(n) \
161+
#define AMBIQ_UART_DEFINE(n) \
187162
PM_DEVICE_DT_INST_DEFINE(n, uart_ambiq_pm_action); \
188163
static int pwr_on_ambiq_uart_##n(void) \
189164
{ \
190-
uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
191-
DT_INST_PHA(n, ambiq_pwrcfg, offset); \
192-
uint32_t pwr_status_addr = addr + DEVPWRSTATUS_OFFSET; \
193-
sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
194-
while ((sys_read32(pwr_status_addr) & DT_INST_PHA(n, ambiq_pwrcfg, mask)) != \
195-
DT_INST_PHA(n, ambiq_pwrcfg, mask)) { \
196-
}; \
197-
return 0; \
165+
uint32_t module = (DT_INST_REG_ADDR(n) - UART0_BASE) / (UART1_BASE - UART0_BASE); \
166+
am_hal_pwrctrl_periph_e eUARTPowerModule = \
167+
((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_UART0 + module)); \
168+
return am_hal_pwrctrl_periph_enable(eUARTPowerModule); \
198169
} \
199170
static inline int clk_enable_ambiq_uart_##n(const struct device *dev, uint32_t clk) \
200171
{ \
201-
return clk_enable_ambiq_uart(dev, clk); \
172+
return clk_enable_ambiq_uart(dev, clk); \
202173
}
203-
#endif
204174

205175
#endif /* ZEPHYR_DRIVERS_SERIAL_UART_PL011_AMBIQ_H_ */

‎dts/arm/ambiq/ambiq_apollo3_blue.dtsi

-8
Original file line numberDiff line numberDiff line change
@@ -90,12 +90,6 @@
9090
};
9191
};
9292

93-
pwrcfg: pwrcfg@40021000 {
94-
compatible = "ambiq,pwrctrl";
95-
reg = <0x40021000 0x400>;
96-
#pwrcfg-cells = <2>;
97-
};
98-
9993
stimer0: stimer@40008140 {
10094
compatible = "ambiq,stimer";
10195
reg = <0x40008140 0x80>;
@@ -182,7 +176,6 @@
182176
interrupt-names = "UART0";
183177
status = "disabled";
184178
clocks = <&uartclk>;
185-
ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
186179
zephyr,pm-device-runtime-auto;
187180
};
188181

@@ -193,7 +186,6 @@
193186
interrupt-names = "UART1";
194187
status = "disabled";
195188
clocks = <&uartclk>;
196-
ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
197189
zephyr,pm-device-runtime-auto;
198190
};
199191

‎dts/arm/ambiq/ambiq_apollo3p_blue.dtsi

-8
Original file line numberDiff line numberDiff line change
@@ -108,12 +108,6 @@
108108
};
109109
};
110110

111-
pwrcfg: pwrcfg@40021000 {
112-
compatible = "ambiq,pwrctrl";
113-
reg = <0x40021000 0x400>;
114-
#pwrcfg-cells = <2>;
115-
};
116-
117111
stimer0: stimer@40008140 {
118112
compatible = "ambiq,stimer";
119113
reg = <0x40008140 0x80>;
@@ -200,7 +194,6 @@
200194
interrupt-names = "UART0";
201195
status = "disabled";
202196
clocks = <&uartclk>;
203-
ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
204197
zephyr,pm-device-runtime-auto;
205198
};
206199

@@ -211,7 +204,6 @@
211204
interrupt-names = "UART1";
212205
status = "disabled";
213206
clocks = <&uartclk>;
214-
ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
215207
zephyr,pm-device-runtime-auto;
216208
};
217209

‎dts/arm/ambiq/ambiq_apollo4p.dtsi

-10
Original file line numberDiff line numberDiff line change
@@ -92,12 +92,6 @@
9292
};
9393
};
9494

95-
pwrcfg: pwrcfg@40021000 {
96-
compatible = "ambiq,pwrctrl";
97-
reg = <0x40021000 0x400>;
98-
#pwrcfg-cells = <2>;
99-
};
100-
10195
stimer0: stimer@40008800 {
10296
compatible = "ambiq,stimer";
10397
reg = <0x40008800 0x80>;
@@ -121,7 +115,6 @@
121115
interrupt-names = "UART0";
122116
status = "disabled";
123117
clocks = <&uartclk>;
124-
ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
125118
};
126119

127120
uart1: uart@4001d000 {
@@ -131,7 +124,6 @@
131124
interrupt-names = "UART1";
132125
status = "disabled";
133126
clocks = <&uartclk>;
134-
ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
135127
};
136128

137129
uart2: uart@4001e000 {
@@ -141,7 +133,6 @@
141133
interrupt-names = "UART2";
142134
status = "disabled";
143135
clocks = <&uartclk>;
144-
ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
145136
};
146137

147138
uart3: uart@4001f000 {
@@ -151,7 +142,6 @@
151142
interrupt-names = "UART3";
152143
status = "disabled";
153144
clocks = <&uartclk>;
154-
ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
155145
};
156146

157147
iom0: iom@40050000 {

‎dts/arm/ambiq/ambiq_apollo4p_blue.dtsi

-10
Original file line numberDiff line numberDiff line change
@@ -73,12 +73,6 @@
7373
};
7474
};
7575

76-
pwrcfg: pwrcfg@40021000 {
77-
compatible = "ambiq,pwrctrl";
78-
reg = <0x40021000 0x400>;
79-
#pwrcfg-cells = <2>;
80-
};
81-
8276
stimer0: stimer@40008800 {
8377
compatible = "ambiq,stimer";
8478
reg = <0x40008800 0x80>;
@@ -102,7 +96,6 @@
10296
interrupt-names = "UART0";
10397
status = "disabled";
10498
clocks = <&uartclk>;
105-
ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
10699
};
107100
uart1: uart@4001d000 {
108101
compatible = "ambiq,uart", "arm,pl011";
@@ -111,7 +104,6 @@
111104
interrupt-names = "UART1";
112105
status = "disabled";
113106
clocks = <&uartclk>;
114-
ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
115107
};
116108

117109
uart2: uart@4001e000 {
@@ -121,7 +113,6 @@
121113
interrupt-names = "UART2";
122114
status = "disabled";
123115
clocks = <&uartclk>;
124-
ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
125116
};
126117

127118
uart3: uart@4001f000 {
@@ -131,7 +122,6 @@
131122
interrupt-names = "UART3";
132123
status = "disabled";
133124
clocks = <&uartclk>;
134-
ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
135125
};
136126

137127
iom0: iom@40050000 {

‎dts/bindings/power/ambiq,pwrctrl.yaml

-22
This file was deleted.

‎dts/bindings/power/ambiq-pwrcfg.yaml

-11
This file was deleted.

‎dts/bindings/serial/ambiq,uart.yaml

+1-4
Original file line numberDiff line numberDiff line change
@@ -5,14 +5,11 @@ description: Ambiq UART controller (PL011 compatible)
55

66
compatible: "ambiq,uart"
77

8-
include: ["arm,pl011.yaml", pinctrl-device.yaml, ambiq-pwrcfg.yaml]
8+
include: ["arm,pl011.yaml", pinctrl-device.yaml]
99

1010
properties:
1111
pinctrl-0:
1212
required: true
1313

1414
pinctrl-names:
1515
required: true
16-
17-
ambiq,pwrcfg:
18-
required: true

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