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drivers: adc: add a driver for the CH32V003 ADC
The CH32V003 has a 8 channel, 10 bit onboard ADC. Add an immediate mode driver and the appropriate pinctrl bindings. Note that the CH32V003 GPIO pins have both a floating input and an analogue input mode, and the pinctrl is needed to put the pin in analogue mode. Signed-off-by: Michael Hope <[email protected]>
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‎drivers/adc/CMakeLists.txt

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Original file line numberDiff line numberDiff line change
@@ -60,3 +60,4 @@ zephyr_library_sources_ifdef(CONFIG_ADC_MAX32 adc_max32.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_AD4114 adc_ad4114.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_AD7124 adc_ad7124.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_AD405X adc_ad405x.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_CH32V00X adc_ch32v00x.c)

‎drivers/adc/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -144,4 +144,6 @@ source "drivers/adc/Kconfig.ad7124"
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source "drivers/adc/Kconfig.ad405x"
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source "drivers/adc/Kconfig.ch32v00x"
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endif # ADC

‎drivers/adc/Kconfig.ch32v00x

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@@ -0,0 +1,9 @@
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# Copyright (c) Michael Hope <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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config ADC_CH32V00X
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bool "WCH CH32V00x ADC Driver"
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default y
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depends on DT_HAS_WCH_ADC_ENABLED
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help
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Enable the WCH CH32V00x family Analog-to-Digital Converter (ADC) driver.

‎drivers/adc/adc_ch32v00x.c

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@@ -0,0 +1,163 @@
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/*
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* Copyright (c) 2025 Michael Hope
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT wch_adc
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#include <ch32fun.h>
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#include <zephyr/drivers/adc.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/clock_control.h>
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struct adc_ch32v00x_data {
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};
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struct adc_ch32v00x_config {
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ADC_TypeDef *regs;
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const struct pinctrl_dev_config *pin_cfg;
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const struct device *clock_dev;
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uint8_t clock_id;
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};
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static int adc_ch32v00x_channel_setup(const struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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if (channel_cfg->gain != ADC_GAIN_1) {
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return -EINVAL;
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}
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if (channel_cfg->reference != ADC_REF_INTERNAL) {
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return -EINVAL;
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}
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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return -EINVAL;
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}
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if (channel_cfg->differential) {
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return -EINVAL;
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}
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if (channel_cfg->channel_id >= 10) {
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return -EINVAL;
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}
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return 0;
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}
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static int adc_ch32v00x_read(const struct device *dev, const struct adc_sequence *sequence)
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{
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const struct adc_ch32v00x_config *config = dev->config;
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ADC_TypeDef *regs = config->regs;
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uint32_t channels = sequence->channels;
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int rsqr = 2;
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int sequence_id = 0;
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int total_channels = 0;
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int i;
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uint16_t *samples = sequence->buffer;
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if (sequence->options != NULL) {
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return -ENOTSUP;
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}
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if (sequence->resolution != 10) {
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return -EINVAL;
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}
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if (sequence->oversampling != 0) {
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return -ENOTSUP;
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}
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if (sequence->channels >= (1 << 10)) {
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return -EINVAL;
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}
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if (sequence->calibrate) {
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regs->CTLR2 |= ADC_RSTCAL;
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while ((regs->CTLR2 & ADC_RSTCAL) != 0) {
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}
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regs->CTLR2 |= ADC_CAL;
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while ((ADC1->CTLR2 & ADC_CAL) != 0) {
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}
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}
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/*
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* Build the sample sequence. The channel IDs are packed 5 bits at a time starting in RSQR3
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* and working down in memory to RSQR1.
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*/
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regs->RSQR1 = 0;
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regs->RSQR2 = 0;
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regs->RSQR3 = 0;
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for (i = 0; channels != 0; i++, channels >>= 1) {
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if ((channels & 1) != 0) {
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total_channels++;
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(&regs->RSQR1)[rsqr] |= i << sequence_id;
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sequence_id += ADC_SQ2_0;
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if (sequence_id >= 32) {
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/* Move on to the next RSQRn register, i.e. RSQR(n-1) */
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sequence_id = 0;
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rsqr--;
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}
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}
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}
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if (total_channels == 0) {
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return 0;
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}
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if (sequence->buffer_size < total_channels * sizeof(*samples)) {
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return -ENOMEM;
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}
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/* Set the number of channels to read. Note that '0' means 'one channel'. */
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regs->RSQR1 |= (total_channels - 1) * ADC_L_0;
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regs->CTLR2 |= ADC_SWSTART;
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for (i = 0; i < total_channels; i++) {
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while ((regs->STATR & ADC_EOC) == 0) {
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}
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*samples++ = regs->RDATAR;
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}
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return 0;
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}
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static int adc_ch32v00x_init(const struct device *dev)
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{
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const struct adc_ch32v00x_config *config = dev->config;
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ADC_TypeDef *regs = config->regs;
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int err;
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clock_control_on(config->clock_dev, (clock_control_subsys_t)(uintptr_t)config->clock_id);
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err = pinctrl_apply_state(config->pin_cfg, PINCTRL_STATE_DEFAULT);
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if (err != 0) {
129+
return err;
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}
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/*
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* The default sampling time is 3 cycles and shows coupling between channels. Use 15 cycles
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* instead. Arbitrary.
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*/
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regs->SAMPTR2 = ADC_SMP0_1 | ADC_SMP1_1 | ADC_SMP2_1 | ADC_SMP3_1 | ADC_SMP4_1 |
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ADC_SMP5_1 | ADC_SMP6_1 | ADC_SMP7_1 | ADC_SMP8_1 | ADC_SMP9_1;
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regs->CTLR2 = ADC_ADON | ADC_EXTSEL;
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return 0;
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}
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#define ADC_CH32V00X_DEVICE(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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\
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static const struct adc_driver_api adc_ch32v00x_api_##n = { \
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.channel_setup = adc_ch32v00x_channel_setup, \
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.read = adc_ch32v00x_read, \
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.ref_internal = DT_INST_PROP(n, vref_mv), \
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}; \
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\
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static const struct adc_ch32v00x_config adc_ch32v00x_config_##n = { \
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.regs = (ADC_TypeDef *)DT_INST_REG_ADDR(n), \
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.pin_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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.clock_id = DT_INST_CLOCKS_CELL(n, id), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, adc_ch32v00x_init, NULL, NULL, &adc_ch32v00x_config_##n, \
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POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, &adc_ch32v00x_api_##n);
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DT_INST_FOREACH_STATUS_OKAY(ADC_CH32V00X_DEVICE)

‎drivers/pinctrl/pinctrl_wch_afio.c

+8
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp
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GPIO_TypeDef *regs = wch_afio_pinctrl_regs[port];
2828
uint32_t pcfr1 = AFIO->PCFR1;
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uint8_t cfg = 0;
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bool is_adc = (bit0 == CH32V003_PINMUX_ADC1_RM);
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3132
if (remap != 0) {
3233
RCC->APB2PCENR |= RCC_AFIOEN;
@@ -41,7 +42,14 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp
4142
cfg |= BIT(3);
4243
} else {
4344
if (pins->bias_pull_up || pins->bias_pull_down) {
45+
/* "With pull up and pull down" mode */
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cfg |= BIT(3);
47+
} else if (is_adc) {
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/* Analog input mode */
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cfg = 0;
50+
} else {
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/* Floating input mode */
52+
cfg |= BIT(0);
4553
}
4654
}
4755
regs->CFGLR = (regs->CFGLR & ~(0x0F << (pin * 4))) | (cfg << (pin * 4));

‎dts/bindings/adc/wch,adc.yaml

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@@ -0,0 +1,36 @@
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# Copyright (c) 2025 Michael Hope <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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description: WCH CH32V00x ADC
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compatible: "wch,adc"
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include: [adc-controller.yaml, pinctrl-device.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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clocks:
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required: true
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vref-mv:
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type: int
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default: 3300
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description: |
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Reference voltage in mV. This is typically VDD.
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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"#io-channel-cells":
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const: 1
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io-channel-cells:
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- input

‎dts/riscv/wch/ch32v0/ch32v003.dtsi

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@@ -126,6 +126,16 @@
126126
interrupts = <22>, <23>, <24>, <25>, <26>, <27>, <28>;
127127
dma-channels = <7>;
128128
};
129+
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adc1: adc@40012400 {
131+
compatible = "wch,adc";
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reg = <0x40012400 16>;
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clocks = <&rcc CH32V00X_CLOCK_ADC1>;
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interrupt-parent = <&pfic>;
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interrupts = <29>;
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#io-channel-cells = <1>;
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status = "disabled";
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};
129139
};
130140
};
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‎include/zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h

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@@ -23,6 +23,11 @@
2323
#define CH32V003_PINMUX_TIM1_RM 6
2424
#define CH32V003_PINMUX_TIM1_RM1 23
2525
#define CH32V003_PINMUX_TIM2_RM 8
26+
/*
27+
* ADc1 is not remappable but re-uses the remap field to encode that the pin needs to use
28+
* analog input mode.
29+
*/
30+
#define CH32V003_PINMUX_ADC1_RM 3
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2732
/* Port number with 0-2 */
2833
#define CH32V003_PINCTRL_PORT_SHIFT 0
@@ -134,4 +139,13 @@
134139
#define I2C1_SDA_PD0_1 CH32V003_PINMUX_DEFINE(PD, 0, I2C1, 1)
135140
#define I2C1_SDA_PC6_2 CH32V003_PINMUX_DEFINE(PC, 6, I2C1, 2)
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142+
#define ADC1_A0_PA2_0 CH32V003_PINMUX_DEFINE(PA, 2, ADC1, 0)
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#define ADC1_A1_PA1_0 CH32V003_PINMUX_DEFINE(PA, 1, ADC1, 0)
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#define ADC1_A2_PC4_0 CH32V003_PINMUX_DEFINE(PC, 4, ADC1, 0)
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#define ADC1_A4_PD3_0 CH32V003_PINMUX_DEFINE(PD, 3, ADC1, 0)
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#define ADC1_A3_PD2_0 CH32V003_PINMUX_DEFINE(PD, 2, ADC1, 0)
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#define ADC1_A5_PD5_0 CH32V003_PINMUX_DEFINE(PD, 5, ADC1, 0)
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#define ADC1_A7_PD4_0 CH32V003_PINMUX_DEFINE(PD, 4, ADC1, 0)
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#define ADC1_A6_PD6_0 CH32V003_PINMUX_DEFINE(PD, 6, ADC1, 0)
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137151
#endif /* __CH32V003_PINCTRL_H__ */

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