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manuarguemmahadevan108
manuargue
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mmahadevan108
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boards: mr_canhubk3: enable LPUART serial driver
Reuse existing MCUX-based shim driver for LPUART that is compatible with the hardware block in S32K344. DMA is not yet supported. Use the board's debug connector (P6 / LPUART2) as default console. Signed-off-by: Manuel Argüelles <[email protected]>
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7 files changed

+259
-1
lines changed

7 files changed

+259
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lines changed

‎boards/arm/mr_canhubk3/Kconfig.defconfig

+7
Original file line numberDiff line numberDiff line change
@@ -6,4 +6,11 @@ if BOARD_MR_CANHUBK3
66
config BOARD
77
default "mr_canhubk3"
88

9+
if SERIAL
10+
11+
config UART_CONSOLE
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default y
13+
14+
endif # SERIAL
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916
endif # BOARD_MR_CANHUBK3

‎boards/arm/mr_canhubk3/mr_canhubk3-pinctrl.dtsi

+77-1
Original file line numberDiff line numberDiff line change
@@ -7,11 +7,87 @@
77
#include <nxp/s32/S32K344-172MQFP-pinctrl.h>
88

99
&pinctrl {
10-
1110
eirq0_default: eirq0_default {
1211
group1 {
1312
pinmux = <PTD15_EIRQ31>;
1413
input-enable;
1514
};
1615
};
16+
17+
lpuart0_default: lpuart0_default {
18+
group1 {
19+
pinmux = <PTA3_LPUART0_TX_O>, <PTA1_LPUART0_RTS>;
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output-enable;
21+
};
22+
group2 {
23+
pinmux = <PTA2_LPUART0_RX>, <PTA0_LPUART0_CTS>;
24+
input-enable;
25+
};
26+
};
27+
28+
lpuart1_default: lpuart1_default {
29+
group1 {
30+
pinmux = <PTC7_LPUART1_TX_O>, <PTE6_LPUART1_RTS>;
31+
output-enable;
32+
};
33+
group2 {
34+
pinmux = <PTC6_LPUART1_RX>, <PTE2_LPUART1_CTS>;
35+
input-enable;
36+
};
37+
};
38+
39+
lpuart2_default: lpuart2_default {
40+
group1 {
41+
pinmux = <PTA9_LPUART2_TX_O>;
42+
output-enable;
43+
};
44+
group2 {
45+
pinmux = <PTA8_LPUART2_RX>;
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input-enable;
47+
};
48+
};
49+
50+
lpuart9_default: lpuart9_default {
51+
group1 {
52+
pinmux = <PTB3_LPUART9_TX_O>;
53+
output-enable;
54+
};
55+
group2 {
56+
pinmux = <PTB2_LPUART9_RX>;
57+
input-enable;
58+
};
59+
};
60+
61+
lpuart10_default: lpuart10_default {
62+
group1 {
63+
pinmux = <PTC13_LPUART10_TX_O>;
64+
output-enable;
65+
};
66+
group2 {
67+
pinmux = <PTC12_LPUART10_RX>;
68+
input-enable;
69+
};
70+
};
71+
72+
lpuart13_default: lpuart13_default {
73+
group1 {
74+
pinmux = <PTB18_LPUART13_TX_O>;
75+
output-enable;
76+
};
77+
group2 {
78+
pinmux = <PTB19_LPUART13_RX>;
79+
input-enable;
80+
};
81+
};
82+
83+
lpuart14_default: lpuart14_default {
84+
group1 {
85+
pinmux = <PTB20_LPUART14_TX_O>;
86+
output-enable;
87+
};
88+
group2 {
89+
pinmux = <PTB21_LPUART14_RX>;
90+
input-enable;
91+
};
92+
};
1793
};

‎boards/arm/mr_canhubk3/mr_canhubk3.dts

+39
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,8 @@
1919
zephyr,itcm = &itcm;
2020
zephyr,dtcm = &dtcm;
2121
zephyr,code-partition = &code_partition;
22+
zephyr,console = &lpuart2;
23+
zephyr,shell-uart = &lpuart2;
2224
};
2325

2426
aliases {
@@ -93,3 +95,40 @@
9395
pinctrl-names = "default";
9496
status = "okay";
9597
};
98+
99+
&lpuart0 {
100+
pinctrl-0 = <&lpuart0_default>;
101+
pinctrl-names = "default";
102+
};
103+
104+
&lpuart1 {
105+
pinctrl-0 = <&lpuart1_default>;
106+
pinctrl-names = "default";
107+
};
108+
109+
&lpuart2 {
110+
pinctrl-0 = <&lpuart2_default>;
111+
pinctrl-names = "default";
112+
current-speed = <115200>;
113+
status = "okay";
114+
};
115+
116+
&lpuart9 {
117+
pinctrl-0 = <&lpuart9_default>;
118+
pinctrl-names = "default";
119+
};
120+
121+
&lpuart10 {
122+
pinctrl-0 = <&lpuart10_default>;
123+
pinctrl-names = "default";
124+
};
125+
126+
&lpuart13 {
127+
pinctrl-0 = <&lpuart13_default>;
128+
pinctrl-names = "default";
129+
};
130+
131+
&lpuart14 {
132+
pinctrl-0 = <&lpuart14_default>;
133+
pinctrl-names = "default";
134+
};

‎boards/arm/mr_canhubk3/mr_canhubk3.yaml

+1
Original file line numberDiff line numberDiff line change
@@ -11,3 +11,4 @@ toolchain:
1111
- zephyr
1212
supported:
1313
- gpio
14+
- uart

‎boards/arm/mr_canhubk3/mr_canhubk3_defconfig

+4
Original file line numberDiff line numberDiff line change
@@ -20,3 +20,7 @@ CONFIG_NOCACHE_MEMORY=y
2020

2121
# Drivers
2222
CONFIG_PINCTRL=y
23+
CONFIG_SERIAL=y
24+
25+
# Serial console
26+
CONFIG_CONSOLE=y

‎dts/arm/nxp/nxp_s32k344_m7.dtsi

+129
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66

77
#include <arm/armv7-m.dtsi>
88
#include <mem.h>
9+
#include <zephyr/dt-bindings/clock/nxp_s32k344_clock.h>
910

1011
/ {
1112
cpus {
@@ -286,6 +287,134 @@
286287
status = "disabled";
287288
};
288289
};
290+
291+
lpuart0: uart@40328000 {
292+
compatible = "nxp,kinetis-lpuart";
293+
reg = <0x40328000 0x4000>;
294+
interrupts = <141 0>;
295+
clocks = <&clock NXP_S32_LPUART0_CLK>;
296+
status = "disabled";
297+
};
298+
299+
lpuart1: uart@4032c000 {
300+
compatible = "nxp,kinetis-lpuart";
301+
reg = <0x4032c000 0x4000>;
302+
interrupts = <142 0>;
303+
clocks = <&clock NXP_S32_LPUART1_CLK>;
304+
status = "disabled";
305+
};
306+
307+
lpuart2: uart@40330000 {
308+
compatible = "nxp,kinetis-lpuart";
309+
reg = <0x40330000 0x4000>;
310+
interrupts = <143 0>;
311+
clocks = <&clock NXP_S32_LPUART2_CLK>;
312+
status = "disabled";
313+
};
314+
315+
lpuart3: uart@40334000 {
316+
compatible = "nxp,kinetis-lpuart";
317+
reg = <0x40334000 0x4000>;
318+
interrupts = <144 0>;
319+
clocks = <&clock NXP_S32_LPUART3_CLK>;
320+
status = "disabled";
321+
};
322+
323+
lpuart4: uart@40338000 {
324+
compatible = "nxp,kinetis-lpuart";
325+
reg = <0x40338000 0x4000>;
326+
interrupts = <145 0>;
327+
clocks = <&clock NXP_S32_LPUART4_CLK>;
328+
status = "disabled";
329+
};
330+
331+
lpuart5: uart@4033c000 {
332+
compatible = "nxp,kinetis-lpuart";
333+
reg = <0x4033c000 0x4000>;
334+
interrupts = <146 0>;
335+
clocks = <&clock NXP_S32_LPUART5_CLK>;
336+
status = "disabled";
337+
};
338+
339+
lpuart6: uart@40340000 {
340+
compatible = "nxp,kinetis-lpuart";
341+
reg = <0x40340000 0x4000>;
342+
interrupts = <147 0>;
343+
clocks = <&clock NXP_S32_LPUART6_CLK>;
344+
status = "disabled";
345+
};
346+
347+
lpuart7: uart@40344000 {
348+
compatible = "nxp,kinetis-lpuart";
349+
reg = <0x40344000 0x4000>;
350+
interrupts = <148 0>;
351+
clocks = <&clock NXP_S32_LPUART7_CLK>;
352+
status = "disabled";
353+
};
354+
355+
lpuart8: uart@4048c000 {
356+
compatible = "nxp,kinetis-lpuart";
357+
reg = <0x4048c000 0x4000>;
358+
interrupts = <149 0>;
359+
clocks = <&clock NXP_S32_LPUART8_CLK>;
360+
status = "disabled";
361+
};
362+
363+
lpuart9: uart@40490000 {
364+
compatible = "nxp,kinetis-lpuart";
365+
reg = <0x40490000 0x4000>;
366+
interrupts = <150 0>;
367+
clocks = <&clock NXP_S32_LPUART9_CLK>;
368+
status = "disabled";
369+
};
370+
371+
lpuart10: uart@40494000 {
372+
compatible = "nxp,kinetis-lpuart";
373+
reg = <0x40494000 0x4000>;
374+
interrupts = <151 0>;
375+
clocks = <&clock NXP_S32_LPUART10_CLK>;
376+
status = "disabled";
377+
};
378+
379+
lpuart11: uart@40498000 {
380+
compatible = "nxp,kinetis-lpuart";
381+
reg = <0x40498000 0x4000>;
382+
interrupts = <152 0>;
383+
clocks = <&clock NXP_S32_LPUART11_CLK>;
384+
status = "disabled";
385+
};
386+
387+
lpuart12: uart@4049c000 {
388+
compatible = "nxp,kinetis-lpuart";
389+
reg = <0x4049c000 0x4000>;
390+
interrupts = <153 0>;
391+
clocks = <&clock NXP_S32_LPUART12_CLK>;
392+
status = "disabled";
393+
};
394+
395+
lpuart13: uart@404a0000 {
396+
compatible = "nxp,kinetis-lpuart";
397+
reg = <0x404a0000 0x4000>;
398+
interrupts = <154 0>;
399+
clocks = <&clock NXP_S32_LPUART13_CLK>;
400+
status = "disabled";
401+
};
402+
403+
lpuart14: uart@404a4000 {
404+
compatible = "nxp,kinetis-lpuart";
405+
reg = <0x404a4000 0x4000>;
406+
interrupts = <155 0>;
407+
clocks = <&clock NXP_S32_LPUART14_CLK>;
408+
status = "disabled";
409+
};
410+
411+
lpuart15: uart@404a8000 {
412+
compatible = "nxp,kinetis-lpuart";
413+
reg = <0x404a8000 0x4000>;
414+
interrupts = <156 0>;
415+
clocks = <&clock NXP_S32_LPUART15_CLK>;
416+
status = "disabled";
417+
};
289418
};
290419
};
291420

‎soc/arm/nxp_s32/s32k/Kconfig.series

+2
Original file line numberDiff line numberDiff line change
@@ -14,5 +14,7 @@ config SOC_SERIES_S32K3_M7
1414
select PLATFORM_SPECIFIC_INIT if XIP
1515
select USE_DT_CODE_PARTITION if XIP
1616
select CLOCK_CONTROL
17+
select HAS_MCUX
18+
select HAS_MCUX_LPUART
1719
help
1820
Enable support for NXP S32K3 MCUs family on Cortex-M7 cores

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