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arch: arm: Add vectored interrupt support for Cortex-R.
This commit defines a new Cortex-R configuration 'VIC_IRQ_VECTOR' and implements IRQ initialisation routine to configure SCTLR.VE. Signed-off-by: Stephanos Ioannidis <[email protected]>
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-9
lines changed

4 files changed

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arch/arm/core/cortex_r/CMakeLists.txt

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@@ -6,6 +6,7 @@ zephyr_library_sources(
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vector_table.S
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reset.S
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fault.c
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irq_init.c
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irq_manage.c
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reboot.c
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stacks.c

arch/arm/core/cortex_r/Kconfig

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@@ -79,8 +79,6 @@ config ARMV7_SYS_STACK_SIZE
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help
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This option specifies the size of the stack used by the system mode.
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if CPU_CORTEX_R
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config RUNTIME_NMI
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default y
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@@ -90,6 +88,13 @@ config GEN_ISR_TABLES
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config GEN_IRQ_VECTOR_TABLE
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default n
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endif # CPU_CORTEX_R
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config VIC_IRQ_VECTOR
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bool "Enable VIC port hardware IRQ vector"
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depends on (CPU_CORTEX_R4 || CPU_CORTEX_R5)
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help
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Enable hardware IRQ vector using the handler address provided by the
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the system interrupt controller through VIC port. When this option is
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selected, the IRQ vector (offset 0x18) in the CPU exception vector table
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is not used.
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endif # CPU_CORTEX_R

arch/arm/core/cortex_r/irq_init.c

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/*
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* Copyright (c) 2019 Stephanos Ioannidis <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARM Cortex-R interrupt initialization
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*/
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#include <arch/cpu.h>
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/**
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* @brief Initialize interrupts
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*
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* @return N/A
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*/
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void z_arm_int_lib_init(void)
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{
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/* Configure hardware vectored interrupt mode.*/
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#if defined(CONFIG_VIC_IRQ_VECTOR)
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__asm__ volatile(
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"mrc p15, #0, r0, c1, c0, #0;"
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"orr r0, r0, #0x01000000;" /* [24] VE bit */
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"mcr p15, #0, r0, c1, c0, #0;"
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: : : "memory");
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#endif
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}

include/arch/arm/irq.h

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@@ -38,13 +38,7 @@ extern int z_arch_irq_is_enabled(unsigned int irq);
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extern void z_arm_int_exit(void);
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#if defined(CONFIG_CPU_CORTEX_R)
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static ALWAYS_INLINE void z_arm_int_lib_init(void)
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{
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}
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#else
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extern void z_arm_int_lib_init(void);
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#endif
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/* macros convert value of it's argument to a string */
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#define DO_TOSTR(s) #s

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