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Commit 4782670

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Henrik Lindblom
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soc: stm32: use cache peripheral driver
Use the Zephyr cache API in soc initialization code instead of calling the HAL directly. The change does not modify the pre-existing cache settings, just changes the path they are enabled. Signed-off-by: Henrik Lindblom <[email protected]>
1 parent 7f35f70 commit 4782670

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11 files changed

+64
-62
lines changed

11 files changed

+64
-62
lines changed

‎soc/st/stm32/Kconfig.defconfig

+3
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,9 @@ if SOC_FAMILY_STM32
1111
# can override the defaults given here
1212
rsource "*/Kconfig.defconfig"
1313

14+
config CACHE_STM32
15+
default y if EXTERNAL_CACHE
16+
1417
config CLOCK_CONTROL
1518
default y
1619

‎soc/st/stm32/stm32h5x/Kconfig.defconfig

+13
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,19 @@ if SOC_SERIES_STM32H5X
77

88
rsource "Kconfig.defconfig.stm32h5*"
99

10+
config ICACHE
11+
default y
12+
13+
config DCACHE
14+
default y if !SOC_STM32H503XX
15+
16+
config CACHE_MANAGEMENT
17+
default y
18+
19+
choice CACHE_TYPE
20+
default EXTERNAL_CACHE
21+
endchoice
22+
1023
config ROM_START_OFFSET
1124
default 0x400 if BOOTLOADER_MCUBOOT
1225

‎soc/st/stm32/stm32h5x/soc.c

+2-4
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,9 @@
1111

1212
#include <zephyr/device.h>
1313
#include <zephyr/init.h>
14+
#include <zephyr/cache.h>
1415
#include <stm32_ll_bus.h>
1516
#include <stm32_ll_pwr.h>
16-
#include <stm32_ll_icache.h>
1717
#include <zephyr/logging/log.h>
1818

1919
#include <cmsis_core.h>
@@ -29,9 +29,7 @@ extern void stm32_power_init(void);
2929
*/
3030
void soc_early_init_hook(void)
3131
{
32-
/* Enable instruction cache in 1-way (direct mapped cache) */
33-
LL_ICACHE_SetMode(LL_ICACHE_1WAY);
34-
LL_ICACHE_Enable();
32+
sys_cache_instr_enable();
3533

3634
/* Update CMSIS SystemCoreClock variable (HCLK) */
3735
/* At reset, system core clock is set to 32 MHz from HSI with a HSIDIV = 2 */

‎soc/st/stm32/stm32l5x/Kconfig.defconfig

+10
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,16 @@ if SOC_SERIES_STM32L5X
77

88
rsource "Kconfig.defconfig.stm32l5*"
99

10+
config ICACHE
11+
default y
12+
13+
config CACHE_MANAGEMENT
14+
default y
15+
16+
choice CACHE_TYPE
17+
default EXTERNAL_CACHE
18+
endchoice
19+
1020
config ROM_START_OFFSET
1121
default 0x400 if BOOTLOADER_MCUBOOT
1222

‎soc/st/stm32/stm32l5x/soc.c

+2-5
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,9 @@
1111

1212
#include <zephyr/device.h>
1313
#include <zephyr/init.h>
14+
#include <zephyr/cache.h>
1415
#include <stm32_ll_bus.h>
1516
#include <stm32_ll_pwr.h>
16-
#include <stm32l5xx_ll_icache.h>
1717
#include <zephyr/logging/log.h>
1818

1919
#include <cmsis_core.h>
@@ -29,10 +29,7 @@ extern void stm32_power_init(void);
2929
*/
3030
void soc_early_init_hook(void)
3131
{
32-
/* Enable ICACHE */
33-
while (LL_ICACHE_IsActiveFlag_BUSY()) {
34-
}
35-
LL_ICACHE_Enable();
32+
sys_cache_instr_enable();
3633

3734
/* Update CMSIS SystemCoreClock variable (HCLK) */
3835
/* At reset, system core clock is set to 4 MHz from MSI */

‎soc/st/stm32/stm32u5x/Kconfig.defconfig

+13
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,19 @@ rsource "Kconfig.defconfig.stm32u5*"
1010
config ROM_START_OFFSET
1111
default 0x400 if BOOTLOADER_MCUBOOT
1212

13+
config ICACHE
14+
default y
15+
16+
config DCACHE
17+
default y
18+
19+
config CACHE_MANAGEMENT
20+
default y
21+
22+
choice CACHE_TYPE
23+
default EXTERNAL_CACHE
24+
endchoice
25+
1326
if STM32_STOP3_LP_MODE
1427

1528
config COUNTER

‎soc/st/stm32/stm32u5x/power.c

+3-22
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66
#include <zephyr/kernel.h>
7+
#include <zephyr/cache.h>
78
#include <zephyr/pm/pm.h>
89
#include <soc.h>
910
#include <zephyr/init.h>
@@ -12,7 +13,6 @@
1213
#include <stm32u5xx_ll_bus.h>
1314
#include <stm32u5xx_ll_cortex.h>
1415
#include <stm32u5xx_ll_pwr.h>
15-
#include <stm32u5xx_ll_icache.h>
1616
#include <stm32u5xx_ll_rcc.h>
1717
#include <stm32u5xx_ll_system.h>
1818
#include <clock_control/clock_stm32_ll_common.h>
@@ -35,22 +35,6 @@ static void pwr_stop3_isr(const struct device *dev)
3535
/* Clear all wake-up flags */
3636
LL_PWR_ClearFlag_WU();
3737
}
38-
39-
static void disable_cache(void)
40-
{
41-
/* Disabling ICACHE */
42-
LL_ICACHE_Disable();
43-
while (LL_ICACHE_IsEnabled() == 1U) {
44-
}
45-
46-
/* Wait until ICACHE_SR.BUSYF is cleared */
47-
while (LL_ICACHE_IsActiveFlag_BUSY() == 1U) {
48-
}
49-
50-
/* Wait until ICACHE_SR.BSYENDF is set */
51-
while (LL_ICACHE_IsActiveFlag_BSYEND() == 0U) {
52-
}
53-
}
5438
#endif
5539

5640
void set_mode_stop(uint8_t substate_id)
@@ -82,7 +66,7 @@ void set_mode_stop(uint8_t substate_id)
8266
LL_PWR_ClearFlag_SB();
8367
LL_PWR_ClearFlag_WU();
8468

85-
disable_cache();
69+
sys_cache_instr_disable();
8670

8771
LL_PWR_SetPowerMode(LL_PWR_STOP3_MODE);
8872
break;
@@ -135,10 +119,7 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
135119
} else if (substate_id == 4) {
136120
stm32_clock_control_standby_exit();
137121

138-
LL_ICACHE_SetMode(LL_ICACHE_1WAY);
139-
LL_ICACHE_Enable();
140-
while (LL_ICACHE_IsEnabled() == 0U) {
141-
}
122+
sys_cache_instr_enable();
142123

143124
LL_LPM_DisableSleepOnExit();
144125
LL_LPM_EnableSleep();

‎soc/st/stm32/stm32u5x/soc.c

+2-4
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,10 @@
1010
*/
1111

1212
#include <zephyr/device.h>
13+
#include <zephyr/cache.h>
1314
#include <zephyr/init.h>
1415
#include <stm32_ll_bus.h>
1516
#include <stm32_ll_pwr.h>
16-
#include <stm32_ll_icache.h>
1717
#include <zephyr/logging/log.h>
1818

1919
#include <cmsis_core.h>
@@ -29,9 +29,7 @@ extern void stm32_power_init(void);
2929
*/
3030
void soc_early_init_hook(void)
3131
{
32-
/* Enable instruction cache in 1-way (direct mapped cache) */
33-
LL_ICACHE_SetMode(LL_ICACHE_1WAY);
34-
LL_ICACHE_Enable();
32+
sys_cache_instr_enable();
3533

3634
/* Update CMSIS SystemCoreClock variable (HCLK) */
3735
/* At reset, system core clock is set to 4 MHz from MSIS */

‎soc/st/stm32/stm32wbax/Kconfig.defconfig

+10
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,16 @@ if SOC_SERIES_STM32WBAX
77

88
rsource "Kconfig.defconfig.stm32wba*"
99

10+
config ICACHE
11+
default y
12+
13+
config CACHE_MANAGEMENT
14+
default y
15+
16+
choice CACHE_TYPE
17+
default EXTERNAL_CACHE
18+
endchoice
19+
1020
config STM32_LPTIM_TIMER
1121
default y if PM
1222

‎soc/st/stm32/stm32wbax/power.c

+4-23
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66
#include <zephyr/kernel.h>
7+
#include <zephyr/cache.h>
78
#include <zephyr/pm/pm.h>
89
#include <soc.h>
910
#include <zephyr/init.h>
@@ -13,7 +14,6 @@
1314
#include <stm32wbaxx_ll_bus.h>
1415
#include <stm32wbaxx_ll_cortex.h>
1516
#include <stm32wbaxx_ll_pwr.h>
16-
#include <stm32wbaxx_ll_icache.h>
1717
#include <stm32wbaxx_ll_rcc.h>
1818
#include <stm32wbaxx_ll_system.h>
1919
#include <clock_control/clock_stm32_ll_common.h>
@@ -28,22 +28,6 @@ LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
2828

2929
void stm32_power_init(void);
3030

31-
static void disable_cache(void)
32-
{
33-
/* Disabling ICACHE */
34-
LL_ICACHE_Disable();
35-
while (LL_ICACHE_IsEnabled() == 1U) {
36-
}
37-
38-
/* Wait until ICACHE_SR.BUSYF is cleared */
39-
while (LL_ICACHE_IsActiveFlag_BUSY() == 1U) {
40-
}
41-
42-
/* Wait until ICACHE_SR.BSYENDF is set */
43-
while (LL_ICACHE_IsActiveFlag_BSYEND() == 0U) {
44-
}
45-
}
46-
4731
static void set_mode_stop(uint8_t substate_id)
4832
{
4933

@@ -53,7 +37,7 @@ static void set_mode_stop(uint8_t substate_id)
5337
/* Erratum 2.2.15:
5438
* Disabling ICACHE is required before entering stop mode
5539
*/
56-
disable_cache();
40+
sys_cache_instr_disable();
5741

5842
#ifdef CONFIG_BT_STM32WBA
5943
scm_setwaitstates(LP);
@@ -108,7 +92,7 @@ static void set_mode_suspend_to_ram(void)
10892
LL_PWR_ClearFlag_WU();
10993
LL_RCC_ClearResetFlags();
11094

111-
disable_cache();
95+
sys_cache_instr_disable();
11296

11397
/* Select standby mode */
11498
LL_PWR_SetPowerMode(LL_PWR_MODE_STANDBY);
@@ -161,10 +145,7 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
161145
/* Erratum 2.2.15:
162146
* Enable ICACHE when exiting stop mode
163147
*/
164-
LL_ICACHE_SetMode(LL_ICACHE_1WAY);
165-
LL_ICACHE_Enable();
166-
while (LL_ICACHE_IsEnabled() == 0U) {
167-
}
148+
sys_cache_instr_enable();
168149

169150
LL_LPM_DisableSleepOnExit();
170151
LL_LPM_EnableSleep();

‎soc/st/stm32/stm32wbax/soc.c

+2-4
Original file line numberDiff line numberDiff line change
@@ -11,10 +11,10 @@
1111

1212
#include <zephyr/device.h>
1313
#include <zephyr/init.h>
14+
#include <zephyr/cache.h>
1415
#include <stm32_ll_bus.h>
1516
#include <stm32_ll_pwr.h>
1617
#include <stm32_ll_rcc.h>
17-
#include <stm32_ll_icache.h>
1818
#include <zephyr/arch/cpu.h>
1919
#include <zephyr/irq.h>
2020
#include <zephyr/logging/log.h>
@@ -31,9 +31,7 @@ LOG_MODULE_REGISTER(soc);
3131
*/
3232
void stm32wba_init(void)
3333
{
34-
/* Enable instruction cache in 1-way (direct mapped cache) */
35-
LL_ICACHE_SetMode(LL_ICACHE_1WAY);
36-
LL_ICACHE_Enable();
34+
sys_cache_instr_enable();
3735
#ifdef CONFIG_STM32_FLASH_PREFETCH
3836
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
3937
#endif

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