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5 files changed +75
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lines changed Original file line number Diff line number Diff line change @@ -61,3 +61,13 @@ zephyr_linker_sources(
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vt_pointer_section.ld
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)
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endif ()
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+
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+ if (CONFIG_CPU_CORTEX_M_HAS_VTOR)
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+ zephyr_linker_sources_ifdef(CONFIG_SRAM_VECTOR_TABLE
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+ RAM_SECTIONS
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+ # Maybe need to be changed in order to be placed at the beginning of RAM
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+ # (conflict with code relocation script)
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+ SORT_KEY 0
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+ ram_vector_table.ld
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+ )
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+ endif ()
Original file line number Diff line number Diff line change @@ -39,7 +39,11 @@ Z_GENERIC_SECTION(.vt_pointer_section) __attribute__((used)) void *_vector_table
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#ifdef CONFIG_CPU_CORTEX_M_HAS_VTOR
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+ #ifdef CONFIG_SRAM_VECTOR_TABLE
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+ #define VECTOR_ADDRESS ((uintptr_t)_sram_vector_start)
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+ #else
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#define VECTOR_ADDRESS ((uintptr_t)_vector_start)
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+ #endif
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/* In some Cortex-M3 implementations SCB_VTOR bit[29] is called the TBLBASE bit */
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#ifdef SCB_VTOR_TBLBASE_Msk
@@ -50,6 +54,12 @@ Z_GENERIC_SECTION(.vt_pointer_section) __attribute__((used)) void *_vector_table
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void __weak relocate_vector_table (void )
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{
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+ #ifdef CONFIG_SRAM_VECTOR_TABLE
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+ /* Copy vector table to its location in SRAM */
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+ size_t vector_size = (size_t )_vector_end - (size_t )_vector_start ;
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+
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+ z_early_memcpy (_sram_vector_start , _vector_start , vector_size );
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+ #endif
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SCB -> VTOR = VECTOR_ADDRESS & VTOR_MASK ;
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barrier_dsync_fence_full ();
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barrier_isync_fence_full ();
Original file line number Diff line number Diff line change
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+ /*
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+ * Copyright (c) 2025 Silicon Laboratories Inc.
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+ *
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+ * SPDX-License-Identifier : Apache-2.0
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+ */
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+
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+ /* Vector table is not necessarily at the start of the RAM region : in the case where Zephyr code
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+ * relocation is used, the vector table is placed after the relocated code.
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+ * Relocated code is always placed at the start of the RAM SECTION because of the hard-coded value
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+ * generated by "gen_relocate_app.py" in the file. It can create quite a big gap and lose about the
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+ * size of alignment in RAM space.
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+ */
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+
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+ SECTION_PROLOGUE(.sram_vt,,)
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+ {
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+ /* Heritage of vector table alignment in flash (see vector_table.ld in arch/arm/core/) */
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+ #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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+ . = ALIGN ( 1 << LOG2CEIL(4 * 64) );
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+ #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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+ . = ALIGN ( 1 << LOG2CEIL(4 * 32) );
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+ #else
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+ #error "Unsupported architecture variant"
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+ #endif
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+
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+ . = ALIGN ( 1 << LOG2CEIL(4 * (16 + CONFIG_NUM_IRQS)) );
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+
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+ _sram_vector_start = .;
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+ . += _vector_end - _vector_start;
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+ MPU_ALIGN(_sram_vector_size);
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+ _sram_vector_end = .;
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+ } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
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+ _sram_vector_size = _sram_vector_end - _sram_vector_start;
Original file line number Diff line number Diff line change @@ -63,6 +63,11 @@ extern char __ram_text_reloc_start[];
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extern char __ram_text_reloc_size [];
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#endif
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+ #if defined(CONFIG_SRAM_VECTOR_TABLE )
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+ extern char _sram_vector_start [];
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+ extern char _sram_vector_size [];
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+ #endif
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+
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static const struct z_arm_mpu_partition static_regions [] = {
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#if defined(CONFIG_COVERAGE_GCOV ) && defined (CONFIG_USERSPACE )
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{
@@ -106,6 +111,18 @@ static const struct z_arm_mpu_partition static_regions[] = {
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#endif
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},
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#endif /* CONFIG_CODE_DATA_RELOCATION_SRAM */
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+ #if defined(CONFIG_SRAM_VECTOR_TABLE )
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+ {
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+ /* Vector table in SRAM */
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+ .start = (uint32_t )& _sram_vector_start ,
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+ .size = (uint32_t )& _sram_vector_size ,
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+ #if defined(CONFIG_ARM_MPU_PXN ) && defined (CONFIG_USERSPACE )
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+ .attr = K_MEM_PARTITION_P_R_U_RX ,
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+ #else
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+ .attr = K_MEM_PARTITION_P_RO_U_RO ,
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+ #endif
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+ },
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+ #endif /* CONFIG_SRAM_VECTOR_TABLE */
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#if !defined (CONFIG_MULTITHREADING ) && defined (CONFIG_MPU_STACK_GUARD )
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/* Main stack MPU guard to detect overflow.
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* Note:
Original file line number Diff line number Diff line change @@ -154,6 +154,12 @@ extern char _vector_end[];
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extern char __vector_relay_table [];
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#endif
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+ #ifdef CONFIG_SRAM_VECTOR_TABLE
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+ extern char _sram_vector_start [];
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+ extern char _sram_vector_end [];
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+ extern char _sram_vector_size [];
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+ #endif
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+
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#ifdef CONFIG_COVERAGE_GCOV
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extern char __gcov_bss_start [];
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extern char __gcov_bss_end [];
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