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dylanHsieh4963dylanHsieh4963
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driver: adc: add adc driver for rts5912
Add adc driver for Realtek rts5912. Signed-off-by: Dylan Hsieh <[email protected]>
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‎boards/realtek/rts5912_evb/rts5912_evb.dts

+11
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,17 @@
2020
};
2121
};
2222

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&adc0 {
24+
status = "okay";
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pinctrl-0 = <&adc0_gpio074 &adc1_gpio075
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&adc2_gpio076 &adc3_gpio077
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&adc4_gpio078 &adc5_gpio079
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&adc6_gpio080 &adc7_gpio081
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&adc8_gpio082 &adc9_gpio054
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&adc10_gpio098 &adc11_gpio024>;
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pinctrl-names = "default";
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};
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2334
&uart0 {
2435
status = "okay";
2536
current-speed = <115200>;

‎boards/realtek/rts5912_evb/rts5912_evb_defconfig

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Original file line numberDiff line numberDiff line change
@@ -17,3 +17,6 @@ CONFIG_UART_CONSOLE=y
1717

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# Enable GPIO
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CONFIG_GPIO=y
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# Enable ADC
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CONFIG_ADC=y

‎drivers/adc/CMakeLists.txt

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Original file line numberDiff line numberDiff line change
@@ -60,3 +60,4 @@ zephyr_library_sources_ifdef(CONFIG_ADC_MAX32 adc_max32.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_AD4114 adc_ad4114.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_AD7124 adc_ad7124.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_AD405X adc_ad405x.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_REALTEK_RTS5912 adc_realtek_rts5912.c)

‎drivers/adc/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -144,4 +144,6 @@ source "drivers/adc/Kconfig.ad7124"
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source "drivers/adc/Kconfig.ad405x"
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source "drivers/adc/Kconfig.rts5912"
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endif # ADC

‎drivers/adc/Kconfig.rts5912

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@@ -0,0 +1,10 @@
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# Copyright (c) 2025, Realtek, SIBG-SD7
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# SPDX-License-Identifier: Apache-2.0
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config ADC_REALTEK_RTS5912
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bool "Realtek RTS5912 ADC drivers"
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default y
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depends on DT_HAS_REALTEK_RTS5912_ADC_ENABLED
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select PINCTRL
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help
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This option enables the ADC driver for Realtek RTS5912 of processors.

‎drivers/adc/adc_realtek_rts5912.c

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@@ -0,0 +1,303 @@
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/*
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* Copyright (c) 2025 Realtek, SIBG-SD7
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT realtek_rts5912_adc
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#include <zephyr/drivers/adc.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/clock_control_rts5912.h>
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#include <zephyr/drivers/pinctrl.h>
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#include "reg/reg_adc.h"
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(adc_rts5912, CONFIG_ADC_LOG_LEVEL);
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#define RTS5912_ADC_MAX_CHAN 12
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#define RTS5912_ADC_POLLING_TIME_MS 1
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#define RTS5912_ADC_ENABLE_TIMEOUT 100
25+
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struct adc_rts5912_config {
27+
volatile struct adc_regs *regs;
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const struct pinctrl_dev_config *pcfg;
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#ifdef CONFIG_CLOCK_CONTROL
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const struct device *clk_dev;
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struct rts5912_sccon_subsys sccon_cfg;
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#endif
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};
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struct adc_rts5912_data {
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struct adc_context ctx;
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const struct device *adc_dev;
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volatile uint16_t *buffer;
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volatile uint16_t *repeat_buffer;
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uint32_t channels;
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};
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct adc_rts5912_data *data = CONTAINER_OF(ctx, struct adc_rts5912_data, ctx);
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const struct device *adc_dev = data->adc_dev;
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const struct adc_rts5912_config *const cfg = adc_dev->config;
48+
volatile struct adc_regs *regs = cfg->regs;
49+
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data->repeat_buffer = data->buffer;
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regs->CTRL |= ADC_CTRL_SGLDNINTEN;
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regs->CTRL |= ADC_CTRL_START;
54+
}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
57+
{
58+
struct adc_rts5912_data *data = CONTAINER_OF(ctx, struct adc_rts5912_data, ctx);
59+
60+
if (repeat_sampling) {
61+
data->buffer = data->repeat_buffer;
62+
}
63+
}
64+
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static int adc_rts5912_channel_setup(const struct device *dev,
66+
const struct adc_channel_cfg *channel_cfg)
67+
{
68+
const struct adc_rts5912_config *const cfg = dev->config;
69+
volatile struct adc_regs *regs = cfg->regs;
70+
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
72+
LOG_ERR("Conversion time not supported!");
73+
return -EINVAL;
74+
}
75+
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if (channel_cfg->channel_id >= RTS5912_ADC_MAX_CHAN) {
77+
LOG_ERR("Channel %d not supported!", channel_cfg->channel_id);
78+
return -EINVAL;
79+
}
80+
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if (channel_cfg->gain != ADC_GAIN_1) {
82+
LOG_ERR("ADC gain not supported!");
83+
return -EINVAL;
84+
}
85+
86+
uint8_t channel_id = channel_cfg->channel_id;
87+
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regs->CHCTRL |= ((0x01ul << channel_id) | (ADC_CHCTRL_LPFBP << channel_id));
89+
LOG_DBG("CHCTRL = 0x%08x", regs->CHCTRL);
90+
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return 0;
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}
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static bool adc_rts5912_validate_buffer_size(const struct adc_sequence *sequence)
95+
{
96+
int chan_count = 0;
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size_t buff_need;
98+
uint32_t chan_mask;
99+
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for (chan_mask = 0x80; chan_mask != 0; chan_mask >>= 1) {
101+
if (chan_mask & sequence->channels) {
102+
chan_count++;
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}
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}
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buff_need = chan_count * sizeof(uint16_t);
107+
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if (sequence->options) {
109+
buff_need *= 1 + sequence->options->extra_samplings;
110+
}
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if (buff_need > sequence->buffer_size) {
113+
return false;
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}
115+
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return true;
117+
}
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static int adc_rts5912_enable(const struct device *dev)
120+
{
121+
const struct adc_rts5912_config *const cfg = dev->config;
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volatile struct adc_regs *regs = cfg->regs;
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int64_t st = k_uptime_get();
124+
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regs->CTRL |= ADC_CTRL_EN;
126+
while ((k_uptime_get() - st) < RTS5912_ADC_ENABLE_TIMEOUT) {
127+
if (regs->STS & ADC_STS_RDY) {
128+
return 0;
129+
}
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k_msleep(RTS5912_ADC_POLLING_TIME_MS);
131+
}
132+
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LOG_ERR("ADC enable timeout");
134+
regs->CTRL &= ~ADC_CTRL_EN;
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return -EIO;
137+
}
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static int adc_rts5912_start_read(const struct device *dev, const struct adc_sequence *sequence)
140+
{
141+
struct adc_rts5912_data *const data = dev->data;
142+
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if (sequence->channels & ~BIT_MASK(RTS5912_ADC_MAX_CHAN)) {
144+
LOG_ERR("Incorrect channels, bitmask 0x%x", sequence->channels);
145+
return -EINVAL;
146+
}
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if (sequence->channels == 0UL) {
149+
LOG_ERR("No channel selected");
150+
return -EINVAL;
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}
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if (!adc_rts5912_validate_buffer_size(sequence)) {
154+
LOG_ERR("Incorrect buffer size");
155+
return -ENOMEM;
156+
}
157+
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data->channels = sequence->channels;
159+
data->buffer = sequence->buffer;
160+
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if (adc_rts5912_enable(dev) < 0) {
162+
return -EIO;
163+
}
164+
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adc_context_start_read(&data->ctx, sequence);
166+
167+
return adc_context_wait_for_completion(&data->ctx);
168+
}
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static int adc_rts5912_read(const struct device *dev, const struct adc_sequence *sequence)
171+
{
172+
struct adc_rts5912_data *const data = dev->data;
173+
int error;
174+
175+
adc_context_lock(&data->ctx, false, NULL);
176+
error = adc_rts5912_start_read(dev, sequence);
177+
adc_context_release(&data->ctx, error);
178+
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return error;
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}
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static void rts5912_adc_get_sample(const struct device *dev)
183+
{
184+
const struct adc_rts5912_config *const cfg = dev->config;
185+
volatile struct adc_regs *regs = cfg->regs;
186+
struct adc_rts5912_data *const data = dev->data;
187+
uint32_t idx;
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uint32_t channels = data->channels;
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uint32_t bit;
190+
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/*
192+
* Using the enabled channel bit set, from
193+
* lowest channel number to highest, find out
194+
* which channel is enabled and copy the ADC
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* values from hardware registers to the data
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* buffer.
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*/
198+
bit = find_lsb_set(channels);
199+
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while (bit != 0) {
201+
idx = bit - 1;
202+
203+
*data->buffer = ((uint16_t)regs->CHDATA[idx] & ADC_CHDATA_RESULT_Msk);
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data->buffer++;
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LOG_DBG("idx=%d, data=%x", idx, regs->CHDATA[idx]);
207+
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channels &= ~BIT(idx);
209+
bit = find_lsb_set(channels);
210+
}
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}
212+
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static void adc_rts5912_single_isr(const struct device *dev)
214+
{
215+
const struct adc_rts5912_config *const cfg = dev->config;
216+
volatile struct adc_regs *regs = cfg->regs;
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struct adc_rts5912_data *const data = dev->data;
218+
219+
if (regs->STS & ADC_STS_SGLDN) {
220+
LOG_DBG("single done interrupt triggered.");
221+
222+
regs->CTRL &= ~(ADC_CTRL_SGLDNINTEN);
223+
regs->STS &= regs->STS;
224+
225+
rts5912_adc_get_sample(dev);
226+
227+
regs->CTRL &= ~ADC_CTRL_EN;
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adc_context_on_sampling_done(&data->ctx, dev);
229+
}
230+
}
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static int adc_rts5912_init(const struct device *dev)
233+
{
234+
const struct adc_rts5912_config *const cfg = dev->config;
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struct adc_rts5912_data *const data = dev->data;
236+
volatile struct adc_regs *regs = cfg->regs;
237+
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int ret;
239+
240+
data->adc_dev = dev;
241+
242+
ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
243+
if (ret != 0) {
244+
LOG_ERR("rts5912 ADC pinctrl setup failed (%d)", ret);
245+
return ret;
246+
}
247+
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#ifdef CONFIG_CLOCK_CONTROL
249+
if (!device_is_ready(cfg->clk_dev)) {
250+
LOG_ERR("clock \"%s\" device not ready", cfg->clk_dev->name);
251+
return -ENODEV;
252+
}
253+
254+
ret = clock_control_on(cfg->clk_dev, (clock_control_subsys_t)&cfg->sccon_cfg);
255+
if (ret != 0) {
256+
LOG_ERR("clock power on fail");
257+
return ret;
258+
}
259+
#endif
260+
261+
regs->CTRL = ADC_CTRL_RST;
262+
263+
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), adc_rts5912_single_isr,
264+
DEVICE_DT_INST_GET(0), 0);
265+
irq_enable(DT_INST_IRQN(0));
266+
267+
adc_context_unlock_unconditionally(&data->ctx);
268+
269+
return 0;
270+
}
271+
272+
#define DEV_CONFIG_CLK_DEV_INIT(n) \
273+
.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
274+
.sccon_cfg = { \
275+
.clk_grp = DT_INST_CLOCKS_CELL(n, clk_grp), \
276+
.clk_idx = DT_INST_CLOCKS_CELL(n, clk_idx), \
277+
}
278+
279+
#define ADC_RTS5912_INIT(n) \
280+
PINCTRL_DT_INST_DEFINE(n); \
281+
\
282+
static DEVICE_API(adc, adc_rts5912_api_##n) = { \
283+
.channel_setup = adc_rts5912_channel_setup, \
284+
.read = adc_rts5912_read, \
285+
.ref_internal = DT_INST_PROP(n, vref_mv), \
286+
}; \
287+
\
288+
static struct adc_rts5912_config adc_rts5912_dev_cfg_##n = { \
289+
.regs = (struct adc_regs *)(DT_INST_REG_ADDR(n)), \
290+
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
291+
DEV_CONFIG_CLK_DEV_INIT(n)}; \
292+
\
293+
static struct adc_rts5912_data adc_rts5912_dev_data_##n = { \
294+
ADC_CONTEXT_INIT_TIMER(adc_rts5912_dev_data_##n, ctx), \
295+
ADC_CONTEXT_INIT_LOCK(adc_rts5912_dev_data_##n, ctx), \
296+
ADC_CONTEXT_INIT_SYNC(adc_rts5912_dev_data_##n, ctx), \
297+
}; \
298+
\
299+
DEVICE_DT_INST_DEFINE(n, adc_rts5912_init, NULL, &adc_rts5912_dev_data_##n, \
300+
&adc_rts5912_dev_cfg_##n, PRE_KERNEL_1, CONFIG_ADC_INIT_PRIORITY, \
301+
&adc_rts5912_api_##n);
302+
303+
DT_INST_FOREACH_STATUS_OKAY(ADC_RTS5912_INIT)

‎dts/arm/realtek/ec/rts5912.dtsi

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@@ -98,6 +98,16 @@
9898
status = "okay";
9999
};
100100

101+
adc0: adc@4000fe00 {
102+
compatible = "realtek,rts5912-adc";
103+
reg = <0x4000fe00 0x38>;
104+
clocks = <&sccon RTS5912_SCCON_ADC ADC0_CLKPWR>;
105+
clock-names = "adc";
106+
interrupts = <221 0>;
107+
#io-channel-cells = <1>;
108+
status = "disabled";
109+
};
110+
101111
uart0: uart@40010100 {
102112
compatible = "ns16550";
103113
reg = <0x40010100 0x100>;

‎dts/bindings/adc/realtek,rts5912-adc.yaml

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@@ -0,0 +1,23 @@
1+
description: Realtek rts5912 ADC
2+
3+
compatible: "realtek,rts5912-adc"
4+
5+
include: [adc-controller.yaml, pinctrl-device.yaml]
6+
7+
properties:
8+
interrupts:
9+
required: true
10+
11+
pinctrl-0:
12+
required: true
13+
14+
pinctrl-names:
15+
required: true
16+
17+
vref-mv:
18+
type: int
19+
default: 3300
20+
description: The reference voltage of the ADC in mV.
21+
22+
io-channel-cells:
23+
- input

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