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boards: phytec: add support for phyBOARD-Nash (imx93)
Add basic support for the phyBOARD-Nash, a SBC based on the phyCORE-i.MX93. Both CPU types (Cortex-A55, Cortex-M33) are supported. Signed-off-by: Jonas Remmert <[email protected]>
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‎boards/phytec/phyboard_nash/Kconfig.phyboard_nash

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# Copyright 2024 PHYTEC Messtechnik GmbH
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_PHYBOARD_NASH
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select SOC_MIMX9352_A55 if BOARD_PHYBOARD_NASH_MIMX9352_A55
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select SOC_MIMX9352_M33 if BOARD_PHYBOARD_NASH_MIMX9352_M33
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select SOC_PART_NUMBER_MIMX9352CVVXM

‎boards/phytec/phyboard_nash/board.cmake

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# Copyright (c) 2024, PHYTEC Messtechnik GmbH
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# SPDX-License-Identifier: Apache-2.0
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board_set_debugger_ifnset(jlink)
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board_set_flasher_ifnset(jlink)
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board_runner_args(jlink "--device=MIMX9352_M33")
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

‎boards/phytec/phyboard_nash/board.yml

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board:
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name: phyboard_nash
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full_name: phyBOARD-Nash i.MX93
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vendor: phytec
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socs:
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- name: mimx9352

‎boards/phytec/phyboard_nash/doc/img/phyboard_nash.webp

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‎boards/phytec/phyboard_nash/doc/index.rst

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.. _phyboard_nash:
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phyBOARD-Nash i.MX93
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####################
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Overview
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********
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The phyBOARD-Nash is based on the phyCORE-i.MX93 SoM is based on the NXP i.MX93
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SoC. It features common industrial interfaces and can be used as a reference for
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development or in the final product. It is an entry-level development board,
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which helps developers to get familiar with the module before investing a large
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amount of resources in more specific designs.
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i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single
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Cortex-M33 core. Zephyr OS is ported to run on one of the Cortex-A55 core as
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well as the Cortex-M33 core.
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- Memory:
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- RAM: 512 MB - 2GB LPDDR4
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- EEPROM: 4 kB - 32 kB
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- eMMC: 8 GB - 256 GB
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- Interfaces:
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- Ethernet: 2x 10/100BASE-T (1x TSN Support)
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- USB: 2x 2.0 Host / OTG
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- Serial: 1x RS232 / RS485 Full Duplex / Half Duplex
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- CAN: 1x CAN FD
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- Digital I/O: via Expansion Connector
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- MMX/SD/SDIO: microSD slot
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- Display: LVDS(1x4 or 1x8), MIPI DSI(1x4), HDMI
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- Audio: SAI
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- Camera: 1x MIPI CSI-2 (phyCAM-M), 1x Parallel
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- Expansion Bus: I2C, SPI, SDIO, UART, USB
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- Debug:
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- JTAG 10-pin connector
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- USB-C for UART debug, 2x serial ports for A55 and M33
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.. image:: img/phyboard_nash.webp
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:width: 720px
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:align: center
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:height: 405px
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:alt: phyBOARD-Nash
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More information about the board can be found at the `PHYTEC website`_.
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Supported Features
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==================
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The ``phyboard_nash/mimx9352/a55`` board target supports the following hardware
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features:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| GIC-v4 | on-chip | interrupt controller |
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+-----------+------------+-------------------------------------+
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| ARM TIMER | on-chip | system clock |
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+-----------+------------+-------------------------------------+
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| CLOCK | on-chip | clock_control |
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+-----------+------------+-------------------------------------+
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| PINMUX | on-chip | pinmux |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial port |
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+-----------+------------+-------------------------------------+
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| TPM | on-chip | TPM Counter |
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+-----------+------------+-------------------------------------+
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The ``phyboard_nash/mimx9352/m33`` board target supports the following hardware
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features:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| NVIC | on-chip | interrupt controller |
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+-----------+------------+-------------------------------------+
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| SYSTICK | on-chip | systick |
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+-----------+------------+-------------------------------------+
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| CLOCK | on-chip | clock_control |
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+-----------+------------+-------------------------------------+
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| PINMUX | on-chip | pinmux |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial port |
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+-----------+------------+-------------------------------------+
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Devices
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========
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System Clock
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------------
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This board configuration uses a system clock frequency of 24 MHz. Cortex-A55
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Core runs up to 1.7 GHz. Cortex-M33 Core runs up to 200MHz in which SYSTICK runs
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on same frequency.
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Serial Port
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-----------
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This board configuration uses a single serial communication channel with the
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CPU's UART2 for A55 core and M33 core. The u-boot bootloader or Linux use the
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second serial port for debug output.
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Programming and Debugging (A55)
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*******************************
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Copy the compiled ``zephyr.bin`` to the ``BOOT`` partition of the SD card and
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plug the SD card into the board. Power it up and stop the u-boot execution at
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prompt.
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Use U-Boot to load and execute zephyr.bin on Cortex-A55 Core0:
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.. code-block:: console
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fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xd0000000
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Use this configuration to run basic Zephyr applications and kernel tests,
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for example:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: phyboard_nash/mimx9352/a55
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:goals: build
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Use this configuration to run basic Zephyr applications, for example:
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.. code-block:: console
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*** Booting Zephyr OS build v3.7.0-848-gb4d99b124c6d ***
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Hello World! phyboard_nash/mimx9352/a55
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Programming and Debugging (M33)
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*******************************
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Copy the compiled ``zephyr.bin`` to the ``BOOT`` partition of the SD card and
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plug the SD card into the board. Power it up and stop the u-boot execution at
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prompt.
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Use U-Boot to load and kick zephyr.bin to Cortex-M33 Core:
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.. code-block:: console
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load mmc 1:1 0x80000000 zephyr.bin;cp.b 0x80000000 0x201e0000 0x30000;bootaux 0x1ffe0000 0
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Use this configuration to run basic Zephyr applications, for example:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: phyboard_nash/mimx9352/m33
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:goals: build
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This will build an image with the synchronization sample app, boot it and
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display the following console output:
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.. code-block:: console
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*** Booting Zephyr OS build v3.7.0-848-gb4d99b124c6d ***
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Hello World! phyboard_nash/mimx9352/m33
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Starting the M7-Core from U-Boot and Linux
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==========================================
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Loading binaries and starting the M33-Core is supported from Linux via
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remoteproc. Please check the `phyCORE-i.MX93 BSP Manual`_ for more information.
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References
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==========
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For more information refer to the `PHYTEC website`_.
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.. _PHYTEC website:
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https://www.phytec.eu/en/produkte/development-kits/phyboard-nash/
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.. _phyCORE-i.MX93 BSP Manual:
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https://phytec.github.io/doc-bsp-yocto/bsp/imx9/imx93/imx93.html

‎boards/phytec/phyboard_nash/phyboard_nash-pinctrl.dtsi

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/*
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* Copyright 2024 PHYTEC Messtechnik GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/nxp_imx/mimx9352cvuxk-pinctrl.dtsi>
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&pinctrl {
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uart2_default: uart2_default {
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group0 {
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pinmux = <&iomuxc1_uart2_rxd_lpuart_rx_lpuart2_rx>,
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<&iomuxc1_uart2_txd_lpuart_tx_lpuart2_tx>;
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bias-pull-up;
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slew-rate = "slightly_fast";
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drive-strength = "x5";
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};
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};
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};

‎boards/phytec/phyboard_nash/phyboard_nash_a55.dts

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/*
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* Copyright 2022,2024 NXP
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* Copyright 2024 PHYTEC Messtechnik GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nxp/nxp_mimx93_a55.dtsi>
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#include "phyboard_nash-pinctrl.dtsi"
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/ {
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model = "PHYTEC phyBOARD-Nash i.MX93";
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compatible = "phytec,phyboard_nash";
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chosen {
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zephyr,console = &lpuart2;
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zephyr,shell-uart = &lpuart2;
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zephyr,sram = &sram0;
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};
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cpus {
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cpu@0 {
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status = "disabled";
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};
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};
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sram0: memory@d0000000 {
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reg = <0xd0000000 DT_SIZE_M(1)>;
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};
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};
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&lpuart2 {
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status = "okay";
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current-speed = <115200>;
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/* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */
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pinctrl-0 = <&uart2_default>;
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pinctrl-names = "default";
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};

‎boards/phytec/phyboard_nash/phyboard_nash_a55.yaml

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# Copyright 2024 PHYTEC Messtechnik GmbH
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# SPDX-License-Identifier: Apache-2.0
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identifier: phyboard_nash/mimx9352/a55
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name: PHYTEC phyBOARD-Nash i.MX93 A55
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type: mcu
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arch: arm64
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toolchain:
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- zephyr
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- cross-compile
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ram: 1024
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supported:
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- uart
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testing:
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ignore_tags:
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- net
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- bluetooth
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vendor: phytec

‎boards/phytec/phyboard_nash/phyboard_nash_a55_defconfig

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# Copyright 2024 PHYTEC Messtechnik GmbH
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_CLOCK_CONTROL=y
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_CONSOLE=y
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# ARM Options
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CONFIG_AARCH64_IMAGE_HEADER=y
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CONFIG_ARMV8_A_NS=y
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# MMU Options
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CONFIG_MAX_XLAT_TABLES=64
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# Cache Options
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CONFIG_CACHE_MANAGEMENT=y
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CONFIG_DCACHE_LINE_SIZE_DETECT=y
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CONFIG_ICACHE_LINE_SIZE_DETECT=y
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# Zephyr Kernel Configuration
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CONFIG_XIP=n
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CONFIG_KERNEL_DIRECT_MAP=y

‎boards/phytec/phyboard_nash/phyboard_nash_m33.dts

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/*
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* Copyright 2024 PHYTEC Messtechnik GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nxp/nxp_imx93_m33.dtsi>
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#include "phyboard_nash-pinctrl.dtsi"
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/ {
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model = "PHYTEC phyBOARD-Nash i.MX93";
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compatible = "phytec,phyboard_nash";
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chosen {
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/* TCM */
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zephyr,flash = &itcm;
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zephyr,sram = &dtcm;
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zephyr,console = &lpuart2;
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zephyr,shell-uart = &lpuart2;
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};
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};
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&lpuart2 {
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status = "okay";
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current-speed = <115200>;
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pinctrl-0 = <&uart2_default>;
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pinctrl-names = "default";
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};

‎boards/phytec/phyboard_nash/phyboard_nash_m33.yaml

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# Copyright 2024 PHYTEC Messtechnik GmbH
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# SPDX-License-Identifier: Apache-2.0
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identifier: phyboard_nash/mimx9352/m33
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name: PHYTEC phyBOARD Nash (i.MX93) M33
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type: mcu
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arch: arm
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toolchain:
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- zephyr
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- cross-compile
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ram: 128
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flash: 128
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supported:
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- uart
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vendor: phytec

‎boards/phytec/phyboard_nash/phyboard_nash_m33_defconfig

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# Copyright 2024 PHYTEC Messtechnik GmbH
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_CLOCK_CONTROL=y
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_CONSOLE=y
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CONFIG_XIP=y

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