drivers: spi: nxp: flexiospi spi_loopback test failed on flexio spi

Several reason cause loopback test failed:
a) FlexIO input frequency is not correct, on RT11xx, input freq is 24M,
while max bandrate can reach 1/4 of input freq, so it can only support
6Mbps.
b) Flexio shift register depend on correct timer output to triggger TX
and TX, if timer comparison value is not accurate, RX error happens on
high band rate. This is the reason why test fails on RT1060.

also fix a error on FlexIO clock ID calculation.

Signed-off-by: Raymond Lei <[email protected]>

Author: Raymond0225

drivers/clock_control/clock_control_mcux_ccm_rev2.c

@@ -225,11 +225,8 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
 #endif
 
 #ifdef CONFIG_MCUX_FLEXIO
-	case IMX_CCM_FLEXIO1_CLK:
-		clock_root = kCLOCK_Root_Flexio1;
-		break;
-	case IMX_CCM_FLEXIO2_CLK:
-		clock_root = kCLOCK_Root_Flexio2;
+	case IMX_CCM_FLEXIO_CLK:
+		clock_root = kCLOCK_Root_Flexio1 + instance;
 		break;
 #endif
 

drivers/spi/spi_mcux_flexio.c

@@ -206,6 +206,24 @@ static void spi_flexio_master_init(FLEXIO_SPI_Type *base, flexio_spi_master_conf
 	timerConfig.timerStart      = kFLEXIO_TimerStartBitEnabled;
 	/* Low 8-bits are used to configure baudrate. */
 	timerDiv = (uint16_t)(srcClock_Hz / masterConfig->baudRate_Bps);
+
+	/* Add protection if bandrate required is overflow.
+	 * FLEXIO input freq can not meet required bandrate. Max bandrate can
+	 * not exceed 1/4 of input freq. You can raise input freq or lower
+	 * bandrate required to remove this warning.
+	 */
+	if (timerDiv < 4) {
+		timerDiv = 4;
+	}
+	/* If timeDiv is odd, get it to even. */
+	timerDiv += timerDiv & 1UL;
+
+	if (masterConfig->baudRate_Bps != (srcClock_Hz / timerDiv)) {
+		LOG_WRN("Bandrate req:%uKbps, got:%uKbps",
+			(uint32_t)(masterConfig->baudRate_Bps / 1000),
+			(uint32_t)(srcClock_Hz / (timerDiv*1000)));
+	}
+
 	timerDiv = timerDiv / 2U - 1U;
 	/* High 8-bits are used to configure shift clock edges(transfer width). */
 	timerCmp = ((uint16_t)masterConfig->dataMode * 2U - 1U) << 8U;

soc/nxp/imxrt/imxrt10xx/soc.c

@@ -215,6 +215,18 @@ __weak void clock_init(void)
 	CLOCK_SetDiv(kCLOCK_LpspiDiv, 0); /* Set SPI divider to 1 */
 #endif
 
+#ifdef CONFIG_MCUX_FLEXIO
+	/* Configure input clock to be able to reach the datasheet specified band rate.
+	 * FLEXIO can reach to 120MHz. Select USB pll(480M) as source and divide by 2.
+	 * pre divider by default is 1 which means divide by 2.
+	 */
+	CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+	CLOCK_SetDiv(kCLOCK_Flexio1Div, 1);
+
+	CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+	CLOCK_SetDiv(kCLOCK_Flexio2Div, 1);
+#endif
+
 #ifdef CONFIG_DISPLAY_MCUX_ELCDIF
 	/* MUX selects video PLL, which is initialized to 93MHz */
 	CLOCK_SetMux(kCLOCK_LcdifPreMux, 2);

soc/nxp/imxrt/imxrt11xx/soc.c

@@ -391,6 +391,18 @@ __weak void clock_init(void)
 	CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
 #endif
 
+#ifdef CONFIG_MCUX_FLEXIO
+	/* Configure flexio1 with oscRC400M */
+	rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M;
+	rootCfg.div = 2;
+	CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
+
+	/* Configure flexio2 using oscRC400M */
+	rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M;
+	rootCfg.div = 2;
+	CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
+#endif
+
 #ifdef CONFIG_I2C_MCUX_LPI2C
 	/* Configure Lpi2c1 using Osc48MDiv2 */
 	rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;