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boards: arm: mr_canhubk3: add support for GPIO
Add GPIO support for mr_canhubk3 board and enable GPIO tests. Signed-off-by: Manuel Argüelles <[email protected]>
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‎boards/arm/mr_canhubk3/mr_canhubk3-pinctrl.dtsi

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/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/s32/S32K344-172MQFP-pinctrl.h>
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&pinctrl {
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eirq0_default: eirq0_default {
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group1 {
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pinmux = <PTD15_EIRQ31>;
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input-enable;
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};
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};
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};

‎boards/arm/mr_canhubk3/mr_canhubk3.dts

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@@ -6,6 +6,8 @@
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/dts-v1/;
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#include <arm/nxp/nxp_s32k344_m7.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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#include "mr_canhubk3-pinctrl.dtsi"
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/ {
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model = "NXP MR-CANHUBK3";
@@ -18,6 +20,42 @@
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zephyr,dtcm = &dtcm;
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zephyr,code-partition = &code_partition;
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};
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aliases {
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led0 = &user_led1_red;
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led1 = &user_led1_green;
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led2 = &user_led1_blue;
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sw0 = &user_button_1;
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sw1 = &user_button_2;
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};
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leds {
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compatible = "gpio-leds";
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user_led1_green: user_led1_green {
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gpios = <&gpioa_h 11 GPIO_ACTIVE_LOW>;
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label = "User RGB LED1 GREEN";
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};
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user_led1_blue: user_led1_blue {
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gpios = <&gpioe_l 12 GPIO_ACTIVE_LOW>;
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label = "User RGB LED1 BLUE";
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};
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user_led1_red: user_led1_red {
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gpios = <&gpioe_l 14 GPIO_ACTIVE_LOW>;
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label = "User RGB LED1 RED";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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user_button_1: button_0 {
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label = "User SW1";
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gpios = <&gpiod_l 15 GPIO_ACTIVE_HIGH>;
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};
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user_button_2: button_1 {
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label = "User SW2";
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gpios = <&gpioa_h 9 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&flash0 {
@@ -37,3 +75,21 @@
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};
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};
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};
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&gpioa_h {
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status = "okay";
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};
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&gpioe_l {
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status = "okay";
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};
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&gpiod_l {
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status = "okay";
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};
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&eirq0 {
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pinctrl-0 = <&eirq0_default>;
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pinctrl-names = "default";
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status = "okay";
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};

‎boards/arm/mr_canhubk3/mr_canhubk3.yaml

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@@ -9,3 +9,5 @@ ram: 1024
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flash: 1024
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toolchain:
1111
- zephyr
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supported:
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- gpio

‎dts/arm/nxp/nxp_s32k344_m7.dtsi

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@@ -80,6 +80,212 @@
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#clock-cells = <1>;
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status = "okay";
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};
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siul2: siul2@40290000 {
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reg = <0x40290000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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eirq0: eirq@40290010 {
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compatible = "nxp,s32-siul2-eirq";
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reg = <0x40290010 0x04>, <0x40290018 0x04>;
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reg-names = "disr0", "direr0";
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interrupts = <53 0>, <54 0>, <55 0>, <56 0>;
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interrupt-names = "0_7", "8_15", "16_23", "24_31";
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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gpioa_l: gpio@40291702 {
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compatible = "nxp,s32-gpio";
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reg = <0x40291702 0x02>, <0x40290240 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq0>;
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interrupts = <0 0>, <1 1>, <2 2>, <3 3>, <4 4>,
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<5 5>, <6 6>, <7 7>, <8 16>, <9 17>,
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<10 18>, <11 19>, <12 20>, <13 21>,
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<14 22>, <15 23>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpioa_h: gpio@40291700 {
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compatible = "nxp,s32-gpio";
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reg = <0x40291700 0x02>, <0x40290280 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq0>;
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interrupts = <0 4>, <2 0>, <3 1>, <4 2>,
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<5 3>, <9 5>, <12 6>, <14 7>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiob_l: gpio@40291706 {
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compatible = "nxp,s32-gpio";
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reg = <0x40291706 0x02>, <0x402902c0 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq0>;
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interrupts = <0 8>, <1 9>, <2 10>, <3 11>, <4 12>,
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<5 13>, <8 14>, <9 15>, <10 24>, <11 25>,
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<12 26>, <13 27>, <14 28>, <15 29>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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gpio-reserved-ranges = <6 2>;
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status = "disabled";
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};
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gpiob_h: gpio@40291704 {
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compatible = "nxp,s32-gpio";
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reg = <0x40291704 0x02>, <0x40290300 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq0>;
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interrupts = <0 30>, <1 31>, <5 8>, <6 9>, <7 10>,
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<8 11>, <9 12>, <10 13>, <12 14>, <15 15>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpioc_l: gpio@4029170a {
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compatible = "nxp,s32-gpio";
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reg = <0x4029170a 0x02>, <0x40290340 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq0>;
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interrupts = <0 1>, <1 1>, <2 2>, <3 3>, <4 4>,
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<5 5>, <6 6>, <7 7>, <8 16>, <9 17>,
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<10 18>, <11 19>, <12 20>, <13 21>,
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<14 22>, <15 23>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpioc_h: gpio@40291708 {
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compatible = "nxp,s32-gpio";
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reg = <0x40291708 0x02>, <0x40290380 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq0>;
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interrupts = <4 16>, <5 17>, <7 18>, <8 19>,
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<9 20>, <10 21>, <11 22>, <13 23>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiod_l: gpio@4029170e {
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compatible = "nxp,s32-gpio";
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reg = <0x4029170e 0x02>, <0x402903c0 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq0>;
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interrupts = <0 8>, <1 9>, <2 10>, <3 11>, <4 12>,
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<5 13>, <6 14>, <7 15>, <8 24>,
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<9 25>, <10 26>, <11 27>, <12 28>,
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<13 29>, <14 30>, <15 31>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiod_h: gpio@4029170c {
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compatible = "nxp,s32-gpio";
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reg = <0x4029170c 0x02>, <0x40290400 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq0>;
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interrupts = <1 24>, <4 25>, <5 26>, <6 27>,
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<7 28>, <8 29>, <11 30>, <12 31>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpioe_l: gpio@40291712 {
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compatible = "nxp,s32-gpio";
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reg = <0x40291712 0x02>, <0x40290440 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq0>;
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interrupts = <0 0>, <1 1>, <2 2>, <3 3>,
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<4 4>, <5 5>, <6 6>, <8 7>,
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<9 8>, <10 9>, <11 10>, <12 11>,
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<13 12>, <14 13>, <15 14>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpioe_h: gpio@40291710 {
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compatible = "nxp,s32-gpio";
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reg = <0x40291710 0x02>, <0x40290480 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq0>;
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interrupts = <0 15>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiof_l: gpio@40291716 {
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compatible = "nxp,s32-gpio";
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reg = <0x40291716 0x02>, <0x402904c0 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq0>;
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interrupts = <0 0>, <1 1>, <2 2>, <3 3>,
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<4 4>, <5 5>, <6 6>, <7 7>,
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<8 16>, <9 17>, <10 18>, <11 19>,
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<12 20>, <13 21>, <14 22>, <15 23>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiof_h: gpio@40291714 {
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compatible = "nxp,s32-gpio";
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reg = <0x40291714 0x02>, <0x40290500 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiog_l: gpio@4029171a {
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compatible = "nxp,s32-gpio";
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reg = <0x4029171a 0x02>, <0x40290540 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq0>;
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interrupts = <0 8>, <1 9>, <2 10>, <3 11>,
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<4 12>, <5 13>, <6 14>, <7 15>,
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<8 24>, <9 25>, <10 26>, <11 27>,
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<12 28>, <13 29>, <14 30>, <15 31>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiog_h: gpio@40291718 {
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compatible = "nxp,s32-gpio";
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reg = <0x40291718 0x02>, <0x40290580 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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};
83289
};
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};
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‎tests/drivers/gpio/gpio_api_1pin/boards/mr_canhubk3.overlay

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/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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aliases {
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/* Use the blue LED pin for this test because it supports interrupts */
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led0 = &user_led1_blue;
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};
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};
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&eirq0_default {
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group2 {
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pinmux = <PTE12_EIRQ11>;
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input-enable;
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};
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};

‎tests/drivers/gpio/gpio_basic_api/boards/mr_canhubk3.overlay

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/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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resources {
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compatible = "test-gpio-basic-api";
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/* Use LPSPI1 MISO/MOSI pins which are also used for spi_loopback test */
11+
out-gpios = <&gpioa_h 13 0>;
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in-gpios = <&gpioa_h 14 0>;
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};
14+
};
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&eirq0_default {
17+
group2 {
18+
pinmux = <PTA30_EIRQ7>;
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input-enable;
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};
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};

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