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dts: spi: Added DTS support for NRF52 master
Added DTS support for NRF52 master SPI driver Signed-off-by: Jan Van Winkel <[email protected]>
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5 files changed

+197
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‎arch/arm/soc/nordic_nrf5/nrf52/dts.fixup

Lines changed: 38 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,43 @@
11
/* SoC level DTS fixup file */
22

3-
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
4-
#define CONFIG_UART_NRF5_IRQ_PRI NORDIC_NRF_UART_40002000_IRQ_0_PRIORITY
5-
#define CONFIG_UART_NRF5_BAUD_RATE NORDIC_NRF_UART_40002000_CURRENT_SPEED
6-
#define CONFIG_UART_NRF5_NAME NORDIC_NRF_UART_40002000_LABEL
3+
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
4+
#define CONFIG_UART_NRF5_IRQ_PRI NORDIC_NRF_UART_40002000_IRQ_0_PRIORITY
5+
#define CONFIG_UART_NRF5_BAUD_RATE NORDIC_NRF_UART_40002000_CURRENT_SPEED
6+
#define CONFIG_UART_NRF5_NAME NORDIC_NRF_UART_40002000_LABEL
77

8-
#define FLASH_DEV_NAME NRF_NRF52_FLASH_CONTROLLER_4001E000_LABEL
8+
#define CONFIG_SPI_0_BASE_ADDRESS NRF_NRF52_SPI_MASTER_40003000_BASE_ADDRESS
9+
#define CONFIG_SPI_0_IRQ NRF_NRF52_SPI_MASTER_40003000_IRQ_0
10+
#define CONFIG_SPI_0_IRQ_PRI NRF_NRF52_SPI_MASTER_40003000_IRQ_0_PRIORITY
11+
#define CONFIG_SPI_0_NAME NRF_NRF52_SPI_MASTER_40003000_LABEL
12+
#define CONFIG_SPI0_NRF52_SCK_PIN NRF_NRF52_SPI_MASTER_40003000_CLK_PIN
13+
#define CONFIG_SPI0_NRF52_MOSI_PIN NRF_NRF52_SPI_MASTER_40003000_MOSI_PIN
14+
#define CONFIG_SPI0_NRF52_MISO_PIN NRF_NRF52_SPI_MASTER_40003000_MISO_PIN
15+
16+
#define CONFIG_SPI_1_BASE_ADDRESS NRF_NRF52_SPI_MASTER_40004000_BASE_ADDRESS
17+
#define CONFIG_SPI_1_IRQ NRF_NRF52_SPI_MASTER_40004000_IRQ_0
18+
#define CONFIG_SPI_1_IRQ_PRI NRF_NRF52_SPI_MASTER_40004000_IRQ_0_PRIORITY
19+
#define CONFIG_SPI_1_NAME NRF_NRF52_SPI_MASTER_40004000_LABEL
20+
#define CONFIG_SPI1_NRF52_SCK_PIN NRF_NRF52_SPI_MASTER_40004000_CLK_PIN
21+
#define CONFIG_SPI1_NRF52_MOSI_PIN NRF_NRF52_SPI_MASTER_40004000_MOSI_PIN
22+
#define CONFIG_SPI1_NRF52_MISO_PIN NRF_NRF52_SPI_MASTER_40004000_MISO_PIN
23+
24+
#define CONFIG_SPI_2_BASE_ADDRESS NRF_NRF52_SPI_MASTER_40023000_BASE_ADDRESS
25+
#define CONFIG_SPI_2_IRQ NRF_NRF52_SPI_MASTER_40023000_IRQ_0
26+
#define CONFIG_SPI_2_IRQ_PRI NRF_NRF52_SPI_MASTER_40023000_IRQ_0_PRIORITY
27+
#define CONFIG_SPI_2_NAME NRF_NRF52_SPI_MASTER_40023000_LABEL
28+
#define CONFIG_SPI2_NRF52_SCK_PIN NRF_NRF52_SPI_MASTER_40023000_CLK_PIN
29+
#define CONFIG_SPI2_NRF52_MOSI_PIN NRF_NRF52_SPI_MASTER_40023000_MOSI_PIN
30+
#define CONFIG_SPI2_NRF52_MISO_PIN NRF_NRF52_SPI_MASTER_40023000_MISO_PIN
31+
32+
#define CONFIG_SPI_3_BASE_ADDRESS NRF_NRF52_SPI_MASTER_4002F000_BASE_ADDRESS
33+
#define CONFIG_SPI_3_IRQ NRF_NRF52_SPI_MASTER_4002F000_IRQ_0
34+
#define CONFIG_SPI_3_IRQ_PRI NRF_NRF52_SPI_MASTER_4002F000_IRQ_0_PRIORITY
35+
#define CONFIG_SPI_3_NAME NRF_NRF52_SPI_MASTER_4002F000_LABEL
36+
#define CONFIG_SPI3_NRF52_SCK_PIN NRF_NRF52_SPI_MASTER_4002F000_CLK_PIN
37+
#define CONFIG_SPI3_NRF52_MOSI_PIN NRF_NRF52_SPI_MASTER_4002F000_MOSI_PIN
38+
#define CONFIG_SPI3_NRF52_MISO_PIN NRF_NRF52_SPI_MASTER_4002F000_MISO_PIN
39+
#define CONFIG_SPI3_NRF52_CS_PIN NRF_NRF52_SPI_MASTER_4002F000_CS_PIM
40+
41+
#define FLASH_DEV_NAME NRF_NRF52_FLASH_CONTROLLER_4001E000_LABEL
942

1043
/* End of SoC Level DTS fixup file */

‎drivers/spi/Kconfig.nrf5

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
menuconfig SPI_NRF5
1414
bool "nRF5 SPI drivers"
1515
depends on SPI && SOC_FAMILY_NRF5 && GPIO_NRF5_P0
16+
select HAS_DTS_SPI
1617
default n
1718
help
1819
Enable support for nRF5 MCU series SPI drivers. Peripherals
@@ -34,6 +35,8 @@ config SPI0_NRF52_MASTER
3435

3536
endchoice
3637

38+
if !HAS_DTS_SPI
39+
3740
config SPI0_NRF52_SCK_PIN
3841
int "SPI0 SCK pin number"
3942
range 0 31
@@ -52,6 +55,8 @@ config SPI0_NRF52_MISO_PIN
5255
help
5356
GPIO pin number for MISO
5457

58+
endif
59+
5560
config SPI0_NRF52_ORC
5661
hex "SPI0 Over Read Character"
5762
default 0x00
@@ -75,6 +80,8 @@ config SPI1_NRF52_MASTER
7580

7681
endchoice
7782

83+
if !HAS_DTS_SPI
84+
7885
config SPI1_NRF52_SCK_PIN
7986
int "SPI1 SCK pin number"
8087
range 0 31
@@ -92,6 +99,7 @@ config SPI1_NRF52_MISO_PIN
9299
range 0 31
93100
help
94101
Pin number for MISO
102+
endif
95103

96104
config SPI1_NRF52_ORC
97105
hex "SPI1 Over Read Character"
@@ -116,6 +124,8 @@ config SPI2_NRF52_MASTER
116124

117125
endchoice
118126

127+
if !HAS_DTS_SPI
128+
119129
config SPI2_NRF52_SCK_PIN
120130
int "SPI2 SCK pin number"
121131
range 0 31
@@ -133,6 +143,7 @@ config SPI2_NRF52_MISO_PIN
133143
range 0 31
134144
help
135145
Pin number for MISO
146+
endif
136147

137148
config SPI2_NRF52_ORC
138149
hex "SPI2 Over Read Character"
@@ -157,6 +168,8 @@ config SPI3_NRF52_MASTER
157168

158169
endchoice
159170

171+
if !HAS_DTS_SPI
172+
160173
config SPI3_NRF52_SCK_PIN
161174
int "SPI3 SCK pin number"
162175
range 0 31
@@ -183,6 +196,8 @@ config SPI3_NRF52_CS_PIN
183196
HW Chip Select pin number.
184197
Not used value is 255 (0xff).
185198

199+
endif
200+
186201
config SPI3_NRF52_ORC
187202
hex "SPI3 Over Read Character"
188203
default 0x00

‎dts/arm/nordic/nrf52832.dtsi

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,45 @@
4444
status = "disabled";
4545
label = "UART_0";
4646
};
47+
48+
spi0: spi@40003000 {
49+
compatible = "nrf,nrf52-spi-master";
50+
#address-cells = <1>;
51+
#size-cells = <0>;
52+
reg = <0x40003000 0x1000>;
53+
interrupts = <3 5>;
54+
status = "disabled";
55+
label = "SPI_0";
56+
clk-pin = <0>;
57+
miso-pin = <0>;
58+
mosi-pin = <0>;
59+
};
60+
61+
spi1: spi@40004000 {
62+
compatible = "nrf,nrf52-spi-master";
63+
#address-cells = <1>;
64+
#size-cells = <0>;
65+
reg = <0x40004000 0x1000>;
66+
interrupts = <4 5>;
67+
status = "disabled";
68+
label = "SPI_1";
69+
clk-pin = <0>;
70+
miso-pin = <0>;
71+
mosi-pin = <0>;
72+
};
73+
74+
spi2: spi@40023000 {
75+
compatible = "nrf,nrf52-spi-master";
76+
#address-cells = <1>;
77+
#size-cells = <0>;
78+
reg = <0x40023000 0x1000>;
79+
interrupts = <35 5>;
80+
status = "disabled";
81+
label = "SPI_2";
82+
clk-pin = <0>;
83+
miso-pin = <0>;
84+
mosi-pin = <0>;
85+
};
4786
};
4887
};
4988

‎dts/arm/nordic/nrf52840.dtsi

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,45 @@
5252
status = "disabled";
5353
label = "UART_1";
5454
};
55+
56+
spi0: spi@40003000 {
57+
compatible = "nrf,nrf52-spi-master";
58+
#address-cells = <1>;
59+
#size-cells = <0>;
60+
reg = <0x40003000 0x1000>;
61+
interrupts = <3 5>;
62+
status = "disabled";
63+
label = "SPI_0";
64+
clk-pin = <0>;
65+
miso-pin = <0>;
66+
mosi-pin = <0>;
67+
};
68+
69+
spi1: spi@40004000 {
70+
compatible = "nrf,nrf52-spi-master";
71+
#address-cells = <1>;
72+
#size-cells = <0>;
73+
reg = <0x40004000 0x1000>;
74+
interrupts = <4 5>;
75+
status = "disabled";
76+
label = "SPI_1";
77+
clk-pin = <0>;
78+
miso-pin = <0>;
79+
mosi-pin = <0>;
80+
};
81+
82+
spi2: spi@40023000 {
83+
compatible = "nrf,nrf52-spi-master";
84+
#address-cells = <1>;
85+
#size-cells = <0>;
86+
reg = <0x40023000 0x1000>;
87+
interrupts = <35 5>;
88+
status = "disabled";
89+
label = "SPI_2";
90+
clk-pin = <0>;
91+
miso-pin = <0>;
92+
mosi-pin = <0>;
93+
};
5594
};
5695
};
5796

‎dts/bindings/spi/nrf,nrf52-spi-master.yaml

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,66 @@
1+
#
2+
# Copyright (c) 2018, dXplore
3+
#
4+
# SPDX-License-Identifier: Apache-2.0
5+
#
6+
---
7+
title: NRF52 SPI Master
8+
id: nrf52-spi-master
9+
version: 0.1
10+
11+
description: >
12+
This binding gives a base representation of the NRF52 SPI master controller
13+
14+
inherits:
15+
!include spi.yaml
16+
17+
properties:
18+
compatible:
19+
type: string
20+
category: required
21+
description: compatible strings
22+
constraint: "nrf,nrf52-spi-master"
23+
24+
reg:
25+
type: array
26+
description: mmio register space
27+
generation: define
28+
category: required
29+
30+
interrupts:
31+
type: array
32+
category: required
33+
description: required interrupts
34+
generation: define
35+
36+
interrupt-names:
37+
type: stringlist
38+
category: optional
39+
description: readable string describing the interrupts
40+
generation: define
41+
42+
clk-pin:
43+
type: int
44+
category: required
45+
description: GPIO pin used for SPI clock
46+
generation: define
47+
48+
miso-pin:
49+
type: int
50+
category: required
51+
description: GPIO pin used for MISO
52+
generation: define
53+
54+
mosi-pin:
55+
type: int
56+
category: required
57+
description: GPIO pin used for MOSI
58+
generation: define
59+
60+
cs-pin:
61+
type: int
62+
category: optional
63+
description: GPIO pin used for HW based CS
64+
generation: define
65+
66+
...

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