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soc: Add support for the WCH CH32V303
Adds support for building an image for the ch32v303. Signed-off-by: Miguel Gazquez <[email protected]>
1 parent 791e44c commit 7f6b519

16 files changed

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‎drivers/timer/Kconfig.wch_ch32v00x

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config CH32V00X_SYSTICK
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bool "CH32V00X systick timer"
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depends on SOC_CH32V003 || SOC_SERIES_QINGKE_V4C
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depends on SOC_CH32V003 || SOC_SERIES_QINGKE_V4C || SOC_SERIES_QINGKE_V4F
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default y
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depends on DT_HAS_WCH_SYSTICK_ENABLED

‎dts/bindings/cpu/wch,qingke-v4f.yaml

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# Copyright (c) 2025 Bootlin
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# SPDX-License-Identifier: Apache-2.0
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description: WCH QingKe V4F RISC-V MCU
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compatible: "wch,qingke-v4f"
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include: riscv,cpus.yaml

‎dts/riscv/wch/ch32v303/ch32v303.dtsi

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/*
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* Copyright (c) 2025 Bootlin
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <freq.h>
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#include <mem.h>
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#include <wch/qingke-v4f.dtsi>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/clock/ch32v20x_30x-clocks.h>
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/ {
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "wch,ch32v00x-hse-clock";
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clock-frequency = <DT_FREQ_M(32)>;
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "wch,ch32v00x-hsi-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(32)>;
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status = "disabled";
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};
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pll: pll {
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#clock-cells = <0>;
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compatible = "wch,ch32v20x_30x-pll-clock";
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mul = <18>;
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status = "disabled";
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};
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};
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(32)>;
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};
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flash: flash-controller@40022000 {
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compatible = "wch,ch32v20x_30x-flash-controller";
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reg = <0x40022000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@08000000 {
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compatible = "soc-nv-flash";
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reg = <0x08000000 DT_SIZE_K(480)>;
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};
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};
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pwr: pwr@40007000 {
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compatible = "wch,pwr";
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reg = <0x40007000 16>;
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};
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pinctrl: pin-controller@40010000 {
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compatible = "wch,20x_30x-afio";
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reg = <0x40010000 16>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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gpioa: gpio@40010800 {
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compatible = "wch,gpio";
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reg = <0x40010800 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_IOPA>;
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};
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gpiob: gpio@40010C00 {
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compatible = "wch,gpio";
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reg = <0x40010C00 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_IOPB>;
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};
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gpioc: gpio@40011000 {
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compatible = "wch,gpio";
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reg = <0x40011000 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_IOPC>;
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};
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gpiod: gpio@40011400 {
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compatible = "wch,gpio";
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reg = <0x40011400 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_IOPD>;
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};
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};
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usart1: uart@40013800 {
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compatible = "wch,usart";
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reg = <0x40013800 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART1>;
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interrupt-parent = <&pfic>;
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interrupts = <53>;
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status = "disabled";
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};
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usart2: uart@40004400 {
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compatible = "wch,usart";
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reg = <0x40004400 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART2>;
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interrupt-parent = <&pfic>;
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interrupts = <54>;
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status = "disabled";
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};
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usart3: uart@40004800 {
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compatible = "wch,usart";
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reg = <0x40004800 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART3>;
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interrupt-parent = <&pfic>;
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interrupts = <55>;
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status = "disabled";
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};
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usart4: uart@40004c00 {
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compatible = "wch,usart";
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reg = <0x40004C00 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART4>;
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interrupt-parent = <&pfic>;
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interrupts = <68>;
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status = "disabled";
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};
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usart5: uart@40005000 {
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compatible = "wch,usart";
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reg = <0x40005000 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART5>;
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interrupt-parent = <&pfic>;
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interrupts = <69>;
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status = "disabled";
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};
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usart6: uart@40001800 {
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compatible = "wch,usart";
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reg = <0x40001800 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART6>;
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interrupt-parent = <&pfic>;
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interrupts = <87>;
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status = "disabled";
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};
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usart7: uart@40001c00 {
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compatible = "wch,usart";
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reg = <0x40001c00 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART7>;
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interrupt-parent = <&pfic>;
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interrupts = <88>;
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status = "disabled";
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};
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usart8: uart@40002000 {
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compatible = "wch,usart";
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reg = <0x40002000 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART8>;
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interrupt-parent = <&pfic>;
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interrupts = <89>;
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status = "disabled";
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};
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rcc: rcc@40021000 {
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compatible = "wch,rcc";
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reg = <0x40021000 16>;
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#clock-cells = <1>;
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status = "okay";
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};
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dma1: dma@40020000 {
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compatible = "wch,wch-dma";
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reg = <0x40020000 0x90>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_DMA1>;
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#dma-cells = <1>;
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interrupt-parent = <&pfic>;
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interrupts = <27>, <28>, <29>, <30>, <31>, <32>, <33>;
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dma-channels = <7>;
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};
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dma2: dma@40020400 {
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compatible = "wch,wch-dma";
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reg = <0x40020400 0x90>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_DMA2>;
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#dma-cells = <1>;
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interrupt-parent = <&pfic>;
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interrupts = <72>, <73>, <74>, <75>, <76>, <98>, <99>, <100>,
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<101>, <102>, <103>;
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dma-channels = <11>;
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};
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};
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};
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&cpu0 {
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clock-frequency = <DT_FREQ_M(144)>;
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};

‎dts/riscv/wch/qingke-v4f.dtsi

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/*
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* Copyright (c) 2025 Bootlin
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "wch,qingke-v4f";
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reg = <0>;
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riscv,isa = "rv32imacf_zicsr_zifencei";
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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pfic: interrupt-controller@e000e000 {
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compatible = "wch,pfic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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reg = <0xe000e000 0x10>;
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status = "okay";
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};
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systick: systimer@e000f000 {
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compatible = "wch,systick";
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reg = <0xe000f000 0x10>;
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status = "okay";
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interrupt-parent = <&pfic>;
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interrupts = <12>;
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};
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};
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};

‎modules/hal_wch/CMakeLists.txt

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if(CONFIG_SOC_CH32V003 OR CONFIG_SOC_SERIES_QINGKE_V4C)
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if(CONFIG_SOC_FAMILY_CH32V)
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zephyr_include_directories(${ZEPHYR_HAL_WCH_MODULE_DIR}/ch32fun .)
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endif()

‎modules/hal_wch/hal_ch32fun.h

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#include <ch32fun.h>
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#endif
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#if defined(CONFIG_SOC_SERIES_QINGKE_V4F)
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#define CH32V30x 1
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#if defined(CONFIG_SOC_CH32V303)
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#define CH32V30x_D8 1
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#endif
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#include <ch32fun.h>
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#endif
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#endif

‎soc/wch/ch32v/qingke_v4f/CMakeLists.txt

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# Copyright (c) 2024 Michael Hope
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# Copyright (c) 2024 Jianxiong Gu
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(
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soc_irq.S
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vector.S
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)
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zephyr_include_directories(.)

‎soc/wch/ch32v/qingke_v4f/Kconfig

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# Copyright (c) 2025 Bootlin
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_QINGKE_V4F
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_F
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI

‎soc/wch/ch32v/qingke_v4f/Kconfig.defconfig

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# Copyright (c) 2025 Bootlin
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_QINGKE_V4F
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
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config MAIN_STACK_SIZE
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default 512
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config IDLE_STACK_SIZE
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default 256
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config ISR_STACK_SIZE
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default 256
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config CLOCK_CONTROL
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default y
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rsource "Kconfig.defconfig.*"
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endif # SOC_SERIES_QINGKE_V4F

‎soc/wch/ch32v/qingke_v4f/Kconfig.defconfig.ch32v303

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# Copyright (c) 2025 Bootlin
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# SPDX-License-Identifier: Apache-2.0
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if SOC_CH32V303
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config VECTOR_TABLE_SIZE
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default 103
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config NUM_IRQS
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default 128
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endif # SOC_CH32V303

‎soc/wch/ch32v/qingke_v4f/Kconfig.soc

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# Copyright (c) 2025 Bootlin
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_QINGKE_V4F
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bool
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select SOC_FAMILY_CH32V
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config SOC_SERIES
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default "qingke_v4f" if SOC_SERIES_QINGKE_V4F
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rsource "Kconfig.soc.*"

‎soc/wch/ch32v/qingke_v4f/Kconfig.soc.ch32v303

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# Copyright (c) 2025 Bootlin
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# SPDX-License-Identifier: Apache-2.0
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config SOC_CH32V303
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bool
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select SOC_SERIES_QINGKE_V4F
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config SOC
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default "ch32v303" if SOC_CH32V303

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