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Henrik Lindblom
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drivers: stm32: use cache peripheral driver
Use cache API for disabling and enabling ICACHE. The driver handles waiting for ongoing cache invalidation. Signed-off-by: Henrik Lindblom <[email protected]>
1 parent 6c63cab commit 81bde83

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5 files changed

+52
-274
lines changed

5 files changed

+52
-274
lines changed

‎drivers/flash/flash_stm32l5x.c

+23-133
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
1111

1212
#include <zephyr/kernel.h>
1313
#include <zephyr/device.h>
14+
#include <zephyr/cache.h>
1415
#include <string.h>
1516
#include <zephyr/drivers/flash.h>
1617
#include <zephyr/init.h>
@@ -34,89 +35,6 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
3435

3536
#define BANK2_OFFSET (KB(STM32_SERIES_MAX_FLASH) / 2)
3637

37-
#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */
38-
#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */
39-
40-
static int stm32_icache_disable(void)
41-
{
42-
int status = 0;
43-
uint32_t tickstart;
44-
45-
LOG_DBG("I-cache Disable");
46-
/* Clear BSYENDF flag first and then disable the instruction cache
47-
* that starts a cache invalidation procedure
48-
*/
49-
CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
50-
51-
LL_ICACHE_Disable();
52-
53-
/* Get tick */
54-
tickstart = k_uptime_get_32();
55-
56-
/* Wait for instruction cache to get disabled */
57-
while (LL_ICACHE_IsEnabled()) {
58-
if ((k_uptime_get_32() - tickstart) >
59-
ICACHE_DISABLE_TIMEOUT_VALUE) {
60-
/* New check to avoid false timeout detection in case
61-
* of preemption.
62-
*/
63-
if (LL_ICACHE_IsEnabled()) {
64-
status = -ETIMEDOUT;
65-
break;
66-
}
67-
}
68-
}
69-
70-
return status;
71-
}
72-
73-
static void stm32_icache_enable(void)
74-
{
75-
LOG_DBG("I-cache Enable");
76-
LL_ICACHE_Enable();
77-
}
78-
79-
static int icache_wait_for_invalidate_complete(void)
80-
{
81-
int status = -EIO;
82-
uint32_t tickstart;
83-
84-
/* Check if ongoing invalidation operation */
85-
if (LL_ICACHE_IsActiveFlag_BUSY()) {
86-
/* Get tick */
87-
tickstart = k_uptime_get_32();
88-
89-
/* Wait for end of cache invalidation */
90-
while (!LL_ICACHE_IsActiveFlag_BSYEND()) {
91-
if ((k_uptime_get_32() - tickstart) >
92-
ICACHE_INVALIDATE_TIMEOUT_VALUE) {
93-
break;
94-
}
95-
}
96-
}
97-
98-
/* Clear any pending flags */
99-
if (LL_ICACHE_IsActiveFlag_BSYEND()) {
100-
LOG_DBG("I-cache Invalidation complete");
101-
102-
LL_ICACHE_ClearFlag_BSYEND();
103-
status = 0;
104-
} else {
105-
LOG_ERR("I-cache Invalidation timeout");
106-
107-
status = -ETIMEDOUT;
108-
}
109-
110-
if (LL_ICACHE_IsActiveFlag_ERR()) {
111-
LOG_ERR("I-cache error");
112-
113-
LL_ICACHE_ClearFlag_ERR();
114-
status = -EIO;
115-
}
116-
117-
return status;
118-
}
119-
12038
/* Macro to check if the flash is Dual bank or not */
12139
#if defined(CONFIG_SOC_SERIES_STM32H5X)
12240
#define stm32_flash_has_2_banks(flash_device) true
@@ -302,19 +220,16 @@ int flash_stm32_block_erase_loop(const struct device *dev,
302220
{
303221
unsigned int address = offset;
304222
int rc = 0;
305-
bool icache_enabled = LL_ICACHE_IsEnabled();
306223

307-
if (icache_enabled) {
308-
/* Disable icache, this will start the invalidation procedure.
309-
* All changes(erase/write) to flash memory should happen when
310-
* i-cache is disabled. A write to flash performed without
311-
* disabling i-cache will set ERRF error flag in SR register.
312-
*/
313-
rc = stm32_icache_disable();
314-
if (rc != 0) {
315-
return rc;
316-
}
317-
}
224+
/* Disable icache, this will start the invalidation procedure.
225+
* All changes(erase/write) to flash memory should happen when
226+
* i-cache is disabled. A write to flash performed without
227+
* disabling i-cache will set ERRF error flag in SR register.
228+
*/
229+
230+
bool cache_enabled = LL_ICACHE_IsEnabled();
231+
232+
sys_cache_instr_disable();
318233

319234
for (; address <= offset + len - 1 ; address += FLASH_PAGE_SIZE) {
320235
rc = erase_page(dev, address);
@@ -323,16 +238,8 @@ int flash_stm32_block_erase_loop(const struct device *dev,
323238
}
324239
}
325240

326-
if (icache_enabled) {
327-
/* Since i-cache was disabled, this would start the
328-
* invalidation procedure, so wait for completion.
329-
*/
330-
rc = icache_wait_for_invalidate_complete();
331-
332-
/* I-cache should be enabled only after the
333-
* invalidation is complete.
334-
*/
335-
stm32_icache_enable();
241+
if (cache_enabled) {
242+
sys_cache_instr_enable();
336243
}
337244

338245
return rc;
@@ -342,19 +249,16 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
342249
const void *data, unsigned int len)
343250
{
344251
int i, rc = 0;
345-
bool icache_enabled = LL_ICACHE_IsEnabled();
346252

347-
if (icache_enabled) {
348-
/* Disable icache, this will start the invalidation procedure.
349-
* All changes(erase/write) to flash memory should happen when
350-
* i-cache is disabled. A write to flash performed without
351-
* disabling i-cache will set ERRF error flag in SR register.
352-
*/
353-
rc = stm32_icache_disable();
354-
if (rc != 0) {
355-
return rc;
356-
}
357-
}
253+
/* Disable icache, this will start the invalidation procedure.
254+
* All changes(erase/write) to flash memory should happen when
255+
* i-cache is disabled. A write to flash performed without
256+
* disabling i-cache will set ERRF error flag in SR register.
257+
*/
258+
259+
bool cache_enabled = LL_ICACHE_IsEnabled();
260+
261+
sys_cache_instr_disable();
358262

359263
for (i = 0; i < len; i += FLASH_STM32_WRITE_BLOCK_SIZE) {
360264
rc = write_nwords(dev, offset + i, ((const uint32_t *) data + (i>>2)),
@@ -364,22 +268,8 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
364268
}
365269
}
366270

367-
if (icache_enabled) {
368-
int rc2;
369-
370-
/* Since i-cache was disabled, this would start the
371-
* invalidation procedure, so wait for completion.
372-
*/
373-
rc2 = icache_wait_for_invalidate_complete();
374-
375-
if (!rc) {
376-
rc = rc2;
377-
}
378-
379-
/* I-cache should be enabled only after the
380-
* invalidation is complete.
381-
*/
382-
stm32_icache_enable();
271+
if (cache_enabled) {
272+
sys_cache_instr_enable();
383273
}
384274

385275
return rc;

‎drivers/flash/flash_stm32wbax.c

+21-133
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
1111

1212
#include <zephyr/kernel.h>
1313
#include <zephyr/device.h>
14+
#include <zephyr/cache.h>
1415
#include <string.h>
1516
#include <zephyr/drivers/flash.h>
1617
#include <zephyr/init.h>
@@ -35,89 +36,6 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
3536

3637
#define BANK2_OFFSET (KB(STM32_SERIES_MAX_FLASH) / 2)
3738

38-
#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */
39-
#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */
40-
41-
static int stm32_icache_disable(void)
42-
{
43-
int status = 0;
44-
uint32_t tickstart;
45-
46-
LOG_DBG("I-cache Disable");
47-
/* Clear BSYENDF flag first and then disable the instruction cache
48-
* that starts a cache invalidation procedure
49-
*/
50-
CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
51-
52-
LL_ICACHE_Disable();
53-
54-
/* Get tick */
55-
tickstart = k_uptime_get_32();
56-
57-
/* Wait for instruction cache to get disabled */
58-
while (LL_ICACHE_IsEnabled()) {
59-
if ((k_uptime_get_32() - tickstart) >
60-
ICACHE_DISABLE_TIMEOUT_VALUE) {
61-
/* New check to avoid false timeout detection in case
62-
* of preemption.
63-
*/
64-
if (LL_ICACHE_IsEnabled()) {
65-
status = -ETIMEDOUT;
66-
break;
67-
}
68-
}
69-
}
70-
71-
return status;
72-
}
73-
74-
static void stm32_icache_enable(void)
75-
{
76-
LOG_DBG("I-cache Enable");
77-
LL_ICACHE_Enable();
78-
}
79-
80-
static int icache_wait_for_invalidate_complete(void)
81-
{
82-
int status = -EIO;
83-
uint32_t tickstart;
84-
85-
/* Check if ongoing invalidation operation */
86-
if (LL_ICACHE_IsActiveFlag_BUSY()) {
87-
/* Get tick */
88-
tickstart = k_uptime_get_32();
89-
90-
/* Wait for end of cache invalidation */
91-
while (!LL_ICACHE_IsActiveFlag_BSYEND()) {
92-
if ((k_uptime_get_32() - tickstart) >
93-
ICACHE_INVALIDATE_TIMEOUT_VALUE) {
94-
break;
95-
}
96-
}
97-
}
98-
99-
/* Clear any pending flags */
100-
if (LL_ICACHE_IsActiveFlag_BSYEND()) {
101-
LOG_DBG("I-cache Invalidation complete");
102-
103-
LL_ICACHE_ClearFlag_BSYEND();
104-
status = 0;
105-
} else {
106-
LOG_ERR("I-cache Invalidation timeout");
107-
108-
status = -ETIMEDOUT;
109-
}
110-
111-
if (LL_ICACHE_IsActiveFlag_ERR()) {
112-
LOG_ERR("I-cache error");
113-
114-
LL_ICACHE_ClearFlag_ERR();
115-
status = -EIO;
116-
}
117-
118-
return status;
119-
}
120-
12139
/*
12240
* offset and len must be aligned on write-block-size for write,
12341
* positive and not beyond end of flash
@@ -272,19 +190,15 @@ int flash_stm32_block_erase_loop(const struct device *dev,
272190
{
273191
unsigned int address = offset;
274192
int rc = 0;
275-
bool icache_enabled = LL_ICACHE_IsEnabled();
276193

277-
if (icache_enabled) {
278-
/* Disable icache, this will start the invalidation procedure.
279-
* All changes(erase/write) to flash memory should happen when
280-
* i-cache is disabled. A write to flash performed without
281-
* disabling i-cache will set ERRF error flag in SR register.
282-
*/
283-
rc = stm32_icache_disable();
284-
if (rc != 0) {
285-
return rc;
286-
}
287-
}
194+
/* Disable icache, this will start the invalidation procedure.
195+
* All changes(erase/write) to flash memory should happen when
196+
* i-cache is disabled. A write to flash performed without
197+
* disabling i-cache will set ERRF error flag in SR register.
198+
*/
199+
bool cache_enabled = LL_ICACHE_IsEnabled();
200+
201+
sys_cache_instr_disable();
288202

289203
for (; address <= offset + len - 1 ; address += FLASH_PAGE_SIZE) {
290204
rc = erase_page(dev, address);
@@ -293,16 +207,8 @@ int flash_stm32_block_erase_loop(const struct device *dev,
293207
}
294208
}
295209

296-
if (icache_enabled) {
297-
/* Since i-cache was disabled, this would start the
298-
* invalidation procedure, so wait for completion.
299-
*/
300-
rc = icache_wait_for_invalidate_complete();
301-
302-
/* I-cache should be enabled only after the
303-
* invalidation is complete.
304-
*/
305-
stm32_icache_enable();
210+
if (cache_enabled) {
211+
sys_cache_instr_enable();
306212
}
307213

308214
return rc;
@@ -312,19 +218,15 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
312218
const void *data, unsigned int len)
313219
{
314220
int i, rc = 0;
315-
bool icache_enabled = LL_ICACHE_IsEnabled();
316221

317-
if (icache_enabled) {
318-
/* Disable icache, this will start the invalidation procedure.
319-
* All changes(erase/write) to flash memory should happen when
320-
* i-cache is disabled. A write to flash performed without
321-
* disabling i-cache will set ERRF error flag in SR register.
322-
*/
323-
rc = stm32_icache_disable();
324-
if (rc != 0) {
325-
return rc;
326-
}
327-
}
222+
/* Disable icache, this will start the invalidation procedure.
223+
* All changes(erase/write) to flash memory should happen when
224+
* i-cache is disabled. A write to flash performed without
225+
* disabling i-cache will set ERRF error flag in SR register.
226+
*/
227+
bool cache_enabled = LL_ICACHE_IsEnabled();
228+
229+
sys_cache_instr_disable();
328230

329231
for (i = 0; i < len; i += 16) {
330232
rc = write_qword(dev, offset + i, ((const uint32_t *) data + (i>>2)));
@@ -333,22 +235,8 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
333235
}
334236
}
335237

336-
if (icache_enabled) {
337-
int rc2;
338-
339-
/* Since i-cache was disabled, this would start the
340-
* invalidation procedure, so wait for completion.
341-
*/
342-
rc2 = icache_wait_for_invalidate_complete();
343-
344-
if (!rc) {
345-
rc = rc2;
346-
}
347-
348-
/* I-cache should be enabled only after the
349-
* invalidation is complete.
350-
*/
351-
stm32_icache_enable();
238+
if (cache_enabled) {
239+
sys_cache_instr_enable();
352240
}
353241

354242
return rc;

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