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Appana Durga Kedareswara rao
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boards: amd: Add board support for RPU on Versal Gen 2 SOC
Add generic board support for the RPU, real-time processing unit on Versal Gen 2 SoC. It is based on Cortext-R52 processor. Signed-off-by: Appana Durga Kedareswara rao <[email protected]>
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‎boards/amd/versal2_rpu/CMakeLists.txt

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#
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# SPDX-License-Identifier: Apache-2.0
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#
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# Copyright (c) 2025 Advanced Micro Devices, Inc.
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#
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if (EXISTS "${BOARD_DIR}/${BOARD}-qemu.dts")
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set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
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COMMAND dtc -I dts -O dtb -q ${BOARD_DIR}/${BOARD}-qemu.dts -o ${PROJECT_BINARY_DIR}/${BOARD}-qemu.dtb
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)
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endif()

‎boards/amd/versal2_rpu/Kconfig.versal2_rpu

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#
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# Copyright (c) 2025 Advanced Micro Devices, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config BOARD_VERSAL2_RPU
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select SOC_AMD_VERSAL2_RPU

‎boards/amd/versal2_rpu/board.cmake

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#
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# Copyright (c) 2025 Advanced Micro Devices, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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include(${ZEPHYR_BASE}/boards/common/xsdb.board.cmake)
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set(SUPPORTED_EMU_PLATFORMS qemu)
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set(QEMU_ARCH xilinx-aarch64)
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set(QEMU_CPU_TYPE_${ARCH} cortex-a78ae)
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set(QEMU_FLAGS_${ARCH}
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-machine arm-generic-fdt
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-hw-dtb ${PROJECT_BINARY_DIR}/${BOARD}-qemu.dtb
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-device loader,addr=0xEB5E0310,data=0x2,data-len=4
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-nographic
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-net nic,netdev=eth0 -netdev user,id=eth0 -net nic,netdev=eth1 -netdev user,id=eth1
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-m 2g
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)
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set(QEMU_KERNEL_OPTION
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-device loader,cpu-num=8,file=\$<TARGET_FILE:\${logical_target_for_zephyr_elf}>
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)

‎boards/amd/versal2_rpu/board.yml

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board:
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name: versal2_rpu
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vendor: amd
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socs:
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- name: amd_versal2_rpu

‎boards/amd/versal2_rpu/doc/index.rst

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.. zephyr:board:: versal2_rpu
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Overview
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********
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This configuration provides support for the RPU(R52), real-time processing unit on Xilinx
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Versal2 SOC, it can operate as following:
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* Two independent R52 cores with their own TCMs (tightly coupled memories)
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* Or as a single dual lock step unit with the TCM.
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This processing unit is based on an ARM Cortex-R52 CPU, it also enables the following devices:
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* ARM GIC v3 Interrupt Controller
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* Global Timer Counter
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* SBSA UART
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Hardware
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********
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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Devices
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========
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System Timer
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------------
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This board configuration uses a system timer tick frequency of 100 MHz.
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Serial Port
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-----------
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This board configuration uses a single serial communication channel with the
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on-chip UART0.
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Memories
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--------
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Although Flash, DDR and OCM memory regions are defined in the DTS file,
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all the code plus data of the application will be loaded in the sram0 region,
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which points to the DDR memory. The ocm0 memory area is currently available
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for usage, although nothing is placed there by default.
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Known Problems or Limitations
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==============================
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The following platform features are unsupported:
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* Only the first core of the R52 subsystem is supported.
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Programming and Debugging
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*************************
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Build and flash in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: versal2_rpu
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:goals: build flash
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You should see the following message on the console:
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.. code-block:: console
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Hello World!
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References
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**********
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1. ARMv8-R Architecture Reference Manual (ARM DDI 0568A.c ID110520)
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2. Cortex-R52 and Cortex-R52F Technical Reference Manual (ARM DDI r1p4 100026_0104_01_en)

‎boards/amd/versal2_rpu/support/xsdb.cfg

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# Copyright (c) 2025 Advanced Micro Devices, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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proc rpu0_core0_rst { {mem "default"} } {
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targets -set -filter {name =~ "DAP*"}
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#CRL write protect
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mwr -force 0xeb5e001c 0x0
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mwr -force 0xEB580000 1
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mwr -force 0xbbf20000 0xeafffffe
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# write BASE_HI and BASE_LO
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if {$mem eq "ddr"} {
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set addr 0x100000
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} elseif {$mem eq "tcm"} {
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set addr 0x0
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} elseif {$mem eq "default"} {
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set addr 0xbbf20000
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}
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mwr -force 0xEB588008 $addr
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# write TCMBOOT as one
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mask_write 0xEB588000 0x10 0x10
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# reset CORE0A_RESET out of reset A_TOPRESET and CORE0A_POR
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mask_write 0xEB5E0310 0x10101 0x1
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# out of reset CORE0A_RESET
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mask_write 0xEB5E0310 0x1 0x0
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targets -set -filter {name =~ "Cortex-R52*0" && parent =~ "*0x00100000"}
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after 300
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stop
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after 1000
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ta
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}
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proc load_image args {
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set elf_file [lindex $args 0]
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if { [info exists ::env(HW_SERVER_URL)] } {
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connect -url $::env(HW_SERVER_URL)
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} else {
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connect
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}
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if { [info exists ::env(PDI_FILE_PATH)] } {
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device program $::env(PDI_FILE_PATH)
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} else {
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puts "Error: env variable PDI_FILE_PATH is not set"
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exit
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}
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if { [info exists ::env(HW_SERVER_URL)] } {
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set hw_server_url [split $::env(HW_SERVER_URL) ":"]
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set host [lindex $hw_server_url 0]
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set port [lindex $hw_server_url 1]
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disconnect
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after 2000
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connect -host $host -port $port
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after 3000
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ta
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}
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after 1000
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targets -set -nocase -filter {name =~ "DAP*"}
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after 100
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# Configure timestamp generator to run global timer gracefully
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# Ideally these registers should be set from bootloader (cdo)
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mwr -force 0xea470020 100000000
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mwr -force 0xea470000 0x1
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after 100
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rpu0_core0_rst
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after 100
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dow -force $elf_file
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con
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exit
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}
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load_image {*}$argv

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