cache: stm32: add cortex-m33 peripheral driver

STM32 Cortex-M33, such as the U5xxx series, have a cache peripheral for
instruction and data caches, which are not present in the C-M33
architecture spec.

The driver defaults to direct mapped cache as it uses less power than the
alternative set associative mapping [1]. This has also been the default in
stm32u5x soc initialization code which makes it the safest choice.

Issue #71268

[1]: https://en.wikipedia.org/wiki/Cache_placement_policies

Signed-off-by: Henrik Lindblom <[email protected]>

Author: Henrik Lindblom

drivers/cache/CMakeLists.txt

@@ -10,3 +10,4 @@ zephyr_library_sources_ifdef(CONFIG_CACHE_ANDES 	cache_andes.c)
 zephyr_library_sources_ifdef(CONFIG_USERSPACE		cache_handlers.c)
 zephyr_library_sources_ifdef(CONFIG_CACHE_NRF_CACHE	cache_nrf.c)
 zephyr_library_sources_ifdef(CONFIG_CACHE_NXP_XCACHE	cache_nxp_xcache.c)
+zephyr_library_sources_ifdef(CONFIG_CACHE_STM32	cache_stm32.c)

drivers/cache/Kconfig

@@ -22,5 +22,6 @@ source "drivers/cache/Kconfig.aspeed"
 source "drivers/cache/Kconfig.nrf"
 source "drivers/cache/Kconfig.andes"
 source "drivers/cache/Kconfig.nxp_xcache"
+source "drivers/cache/Kconfig.stm32"
 
 endif # CACHE

drivers/cache/Kconfig.stm32

@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Henrik Lindblom <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+config CACHE_STM32
+	bool "STM32 cache driver"
+	select CACHE_HAS_DRIVER
+	depends on CACHE_MANAGEMENT
+	help
+	  Enable support for the STM32 ICACHE / DCACHE peripheral present in some Cortex-M33 chips.

drivers/cache/cache_stm32.c

@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2025 Henrik Lindblom <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/cache.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/math_extras.h>
+#include <stm32_ll_dcache.h>
+#include <stm32_ll_icache.h>
+
+LOG_MODULE_REGISTER(cache_stm32, CONFIG_CACHE_LOG_LEVEL);
+
+static inline void wait_for_icache(void)
+{
+	while (LL_ICACHE_IsActiveFlag_BUSY()) {
+	}
+}
+
+void cache_data_enable(void)
+{
+	LL_DCACHE_Enable(DCACHE1);
+#if defined(DCACHE2)
+	LL_DCACHE_Enable(DCACHE2);
+#endif
+}
+
+void cache_data_disable(void)
+{
+	LL_DCACHE_Disable(DCACHE1);
+#if defined(DCACHE2)
+	LL_DCACHE_Disable(DCACHE2);
+#endif
+}
+
+int cache_data_flush_all(void)
+{
+	return -ENOTSUP;
+}
+
+int cache_data_invd_all(void)
+{
+	LL_DCACHE_Invalidate(DCACHE1);
+#if defined(DCACHE2)
+	LL_DCACHE_Invalidate(DCACHE2);
+#endif
+	return 0;
+}
+
+int cache_data_flush_and_invd_all(void)
+{
+	int rc = cache_data_flush_all();
+
+	if (rc) {
+		return rc;
+	}
+
+	return cache_data_invd_all();
+}
+
+static int cache_data_manage_range(void *addr, size_t size, uint32_t command)
+{
+	/*
+	 * This is a simple approach to invalidate the range. The address might be in either DCACHE1
+	 * or DCACHE2 (if present). The cache invalidation algorithm checks the TAG memory for the
+	 * specified address range so there's little harm in just checking both caches.
+	 */
+	uint32_t start = (uint32_t)addr;
+	uint32_t end = start;
+
+	if (u32_add_overflow(start, size, &end)) {
+		return -EOVERFLOW;
+	}
+
+	LL_DCACHE_SetStartAddress(DCACHE1, start);
+	LL_DCACHE_SetEndAddress(DCACHE1, end);
+	LL_DCACHE_SetCommand(DCACHE1, command);
+	LL_DCACHE_StartCommand(DCACHE1);
+#if defined(DCACHE2)
+	LL_DCACHE_SetStartAddress(DCACHE2, start);
+	LL_DCACHE_SetEndAddress(DCACHE2, end);
+	LL_DCACHE_SetCommand(DCACHE2, command);
+	LL_DCACHE_StartCommand(DCACHE2);
+#endif
+	return 0;
+}
+
+int cache_data_flush_range(void *addr, size_t size)
+{
+	return cache_data_manage_range(addr, size, LL_DCACHE_COMMAND_CLEAN_BY_ADDR);
+}
+
+int cache_data_invd_range(void *addr, size_t size)
+{
+	return cache_data_manage_range(addr, size, LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR);
+}
+
+int cache_data_flush_and_invd_range(void *addr, size_t size)
+{
+	return cache_data_manage_range(addr, size, LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR);
+}
+
+void cache_instr_enable(void)
+{
+	LL_ICACHE_SetMode(LL_ICACHE_1WAY);
+	/*
+	 * Need to wait until any pending cache invalidation operations finish. This is recommended
+	 * in the datasheet to ensure execution timing determinism.
+	 */
+	wait_for_icache();
+	LL_ICACHE_Enable();
+}
+
+void cache_instr_disable(void)
+{
+	LL_ICACHE_Disable();
+}
+
+int cache_instr_flush_all(void)
+{
+	return -ENOTSUP;
+}
+
+int cache_instr_invd_all(void)
+{
+	LL_ICACHE_Invalidate();
+	return 0;
+}
+
+int cache_instr_flush_and_invd_all(void)
+{
+	int rc = cache_instr_flush_all();
+
+	if (rc) {
+		return rc;
+	}
+	return cache_instr_invd_all();
+}
+
+int cache_instr_flush_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+	return -ENOTSUP;
+}
+
+int cache_instr_invd_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+	return -ENOTSUP;
+}
+
+int cache_instr_flush_and_invd_range(void *addr, size_t size)
+{
+	int rc = cache_instr_flush_range(addr, size);
+
+	if (rc) {
+		return rc;
+	}
+
+	return cache_instr_invd_range(addr, size);
+}