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dts: mimxrt685s/hifi4: Rework linker file, move data
Rework linker file for mimxrt685s/hifi4 - clarify region names, fix nonsensical text region size. Move hifi4 data and text regions from ITCM/DTCM to the main SRAM (partitions 28 and 29). Modify load regions and cut memory allocation for mimxrt685s/cm33 to prevent overlaps. This change was motivated by the DSP's ITCM and DTCM not being big enough for Zephyr audio applications. Signed-off-by: Vit Stanicek <[email protected]>
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4 files changed

+63
-41
lines changed

4 files changed

+63
-41
lines changed

‎dts/arm/nxp/nxp_rt6xx_common.dtsi

+8-8
Original file line numberDiff line numberDiff line change
@@ -60,20 +60,20 @@
6060

6161
status = "disabled";
6262

63-
region@24000000 {
64-
reg = <0x24000000 DT_SIZE_K(64)>;
65-
type = <NXP_RTXXX_ADSP_REGION_DATA>;
66-
};
67-
6863
region@24020000 {
6964
reg = <0x24020000 DT_SIZE_K(1)>;
7065
type = <NXP_RTXXX_ADSP_REGION_RESET>;
7166
};
7267

73-
region@24020400 {
74-
reg = <0x24020400 DT_SIZE_K(63)>;
68+
region@20400000 {
69+
reg = <0x20400000 DT_SIZE_K(256)>;
7570
type = <NXP_RTXXX_ADSP_REGION_TEXT>;
7671
};
72+
73+
region@20440000 {
74+
reg = <0x20440000 DT_SIZE_K(256)>;
75+
type = <NXP_RTXXX_ADSP_REGION_DATA>;
76+
};
7777
};
7878
};
7979
};
@@ -98,7 +98,7 @@
9898

9999
sram0: memory@180000 {
100100
compatible = "mmio-sram";
101-
reg = <0x180000 DT_SIZE_K(3072)>;
101+
reg = <0x180000 DT_SIZE_K(2560)>;
102102
};
103103

104104
sram1: memory@40140000 {

‎dts/xtensa/nxp/nxp_rt685_hifi4.dtsi

+26-4
Original file line numberDiff line numberDiff line change
@@ -50,9 +50,9 @@
5050
reg = <0x24020000 DT_SIZE_K(1)>;
5151
};
5252

53-
adsp_text: memory@24020400 {
53+
/*adsp_text: memory@24020400 {
5454
reg = <0x24020400 DT_SIZE_K(63)>;
55-
};
55+
};*/
5656
};
5757

5858
dtcm: memory@24000000 {
@@ -62,9 +62,31 @@
6262
compatible = "mmio-sram";
6363

6464
reg = <0x24000000 DT_SIZE_K(64)>;
65+
};
66+
67+
ram0_cached: memory@200000 {
68+
#address-cells = <1>;
69+
#size-cells = <1>;
70+
device_type = "memory";
71+
compatible = "mmio-sram";
72+
73+
reg = <0x00200000 DT_SIZE_K(512)>;
74+
};
75+
76+
ram0_noncached: memory@20400000 {
77+
#address-cells = <1>;
78+
#size-cells = <1>;
79+
device_type = "memory";
80+
compatible = "mmio-sram";
81+
82+
reg = <0x20400000 DT_SIZE_K(512)>;
83+
84+
adsp_text: memory@20400000 {
85+
reg = <0x20400000 DT_SIZE_K(256)>;
86+
};
6587

66-
adsp_data: memory@24000000 {
67-
reg = <0x24000000 DT_SIZE_K(64)>;
88+
adsp_data: memory@20440000 {
89+
reg = <0x20440000 DT_SIZE_K(256)>;
6890
};
6991
};
7092

‎soc/nxp/imxrt/imxrt6xx/hifi4/include/soc/memory.h

+7-7
Original file line numberDiff line numberDiff line change
@@ -10,19 +10,19 @@
1010

1111
#include <autoconf.h>
1212

13-
#define IRAM_BASE (CONFIG_RT685_ADSP_TEXT_MEM_ADDR)
14-
#define IRAM_SIZE (CONFIG_RT685_ADSP_TEXT_MEM_SIZE)
13+
#define TEXT_BASE (CONFIG_RT685_ADSP_TEXT_MEM_ADDR)
14+
#define TEXT_SIZE (CONFIG_RT685_ADSP_TEXT_MEM_SIZE)
1515

16-
#define SDRAM0_BASE (CONFIG_RT685_ADSP_DATA_MEM_ADDR)
17-
#define SDRAM0_SIZE (CONFIG_RT685_ADSP_DATA_MEM_SIZE - CONFIG_RT685_ADSP_STACK_SIZE)
16+
#define DATA_BASE (CONFIG_RT685_ADSP_DATA_MEM_ADDR)
17+
#define DATA_SIZE (CONFIG_RT685_ADSP_DATA_MEM_SIZE - CONFIG_RT685_ADSP_STACK_SIZE)
1818

1919
/* The reset vector address in SRAM and its size. */
2020
#define XCHAL_RESET_VECTOR0_PADDR_IRAM (CONFIG_RT685_ADSP_RESET_MEM_ADDR)
2121
#define MEM_RESET_TEXT_SIZE (0x2e0)
2222
#define MEM_RESET_LIT_SIZE (0x120)
2323

2424
/* Base address of all interrupt vectors in IRAM. */
25-
#define XCHAL_VECBASE_RESET_PADDR_IRAM (IRAM_BASE)
25+
#define XCHAL_VECBASE_RESET_PADDR_IRAM (TEXT_BASE)
2626
#define MEM_VECBASE_LIT_SIZE (0x178)
2727

2828
/* Vector and literal sizes. */
@@ -43,8 +43,8 @@
4343
* Interrupt Descriptor Table (IDT). This is a bogus address as this
4444
* section will be stripped off in the final image.
4545
*/
46-
#define IDT_BASE (IRAM_BASE + IRAM_SIZE)
47-
46+
//#define IDT_BASE (IRAM_BASE + IRAM_SIZE)
47+
#define IDT_BASE (0xDEADBEEF)
4848
/* Size of the Interrupt Descriptor Table (IDT). */
4949
#define IDT_SIZE (0x2000)
5050

‎soc/nxp/imxrt/imxrt6xx/hifi4/linker.ld

+22-22
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright 2024 NXP
2+
* Copyright 2025 NXP
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -13,8 +13,8 @@ OUTPUT_ARCH(xtensa)
1313
#include <zephyr/linker/linker-tool.h>
1414
#include <zephyr/linker/sections.h>
1515

16-
#define RAMABLE_REGION sdram0 :sdram0_phdr
17-
#define ROMABLE_REGION sdram0 :sdram0_phdr
16+
#define RAMABLE_REGION adsp_data :adsp_data_phdr
17+
#define ROMABLE_REGION adsp_data :adsp_data_phdr
1818

1919
MEMORY
2020
{
@@ -69,12 +69,12 @@ MEMORY
6969
vector_double_text :
7070
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM,
7171
len = MEM_VECT_TEXT_SIZE
72-
iram_text_start :
72+
adsp_text :
7373
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE,
74-
len = (IRAM_BASE + IRAM_SIZE) - (XCHAL_DOUBLEEXC_VECTOR_PADDR + MEM_VECT_TEXT_SIZE)
75-
sdram0 :
76-
org = SDRAM0_BASE,
77-
len = SDRAM0_SIZE
74+
len = TEXT_SIZE - MEM_VECT_TEXT_SIZE
75+
adsp_data :
76+
org = DATA_BASE,
77+
len = DATA_SIZE
7878
#ifdef CONFIG_GEN_ISR_TABLES
7979
IDT_LIST :
8080
org = IDT_BASE,
@@ -102,8 +102,8 @@ PHDRS
102102
vector_user_lit_phdr PT_LOAD;
103103
vector_double_text_phdr PT_LOAD;
104104
vector_double_lit_phdr PT_LOAD;
105-
iram_text_start_phdr PT_LOAD;
106-
sdram0_phdr PT_LOAD;
105+
adsp_text_phdr PT_LOAD;
106+
adsp_data_phdr PT_LOAD;
107107
}
108108

109109
PROVIDE(_memmap_reset_vector = XCHAL_RESET_VECTOR0_PADDR_IRAM);
@@ -259,7 +259,7 @@ SECTIONS
259259
_iram_text_start = ABSOLUTE(.);
260260
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
261261
_iram_text_end = ABSOLUTE(.);
262-
} >iram_text_start :iram_text_start_phdr
262+
} >adsp_text :adsp_text_phdr
263263

264264
.rodata : ALIGN(4)
265265
{
@@ -295,14 +295,14 @@ SECTIONS
295295
LONG(_bss_end)
296296
_bss_table_end = ABSOLUTE(.);
297297
__rodata_region_end = ABSOLUTE(.);
298-
} >sdram0 :sdram0_phdr
298+
} >adsp_data :adsp_data_phdr
299299

300300
.module_init : ALIGN(4)
301301
{
302302
_module_init_start = ABSOLUTE(.);
303303
*(*.initcall)
304304
_module_init_end = ABSOLUTE(.);
305-
} >sdram0 :sdram0_phdr
305+
} >adsp_data :adsp_data_phdr
306306

307307
.text : ALIGN(4)
308308
{
@@ -319,21 +319,21 @@ SECTIONS
319319
*(.gnu.version)
320320
_text_end = ABSOLUTE(.);
321321
_etext = .;
322-
} >iram_text_start :iram_text_start_phdr
322+
} >adsp_text :adsp_text_phdr
323323

324324
#include <zephyr/linker/common-rom.ld>
325325

326326
.fw_ready : ALIGN(4)
327327
{
328328
KEEP(*(".fw_ready"));
329329
KEEP (*(.fw_ready_metadata))
330-
} >sdram0 :sdram0_phdr
330+
} >adsp_data :adsp_data_phdr
331331

332332
.noinit : ALIGN(4)
333333
{
334334
*(.noinit)
335335
*(.noinit.*)
336-
} >sdram0 :sdram0_phdr
336+
} >adsp_data :adsp_data_phdr
337337

338338
.data : ALIGN(4)
339339
{
@@ -357,7 +357,7 @@ SECTIONS
357357
*(.gna_model)
358358
__data_end = ABSOLUTE(.);
359359
. = ALIGN(4096);
360-
} >sdram0 :sdram0_phdr
360+
} >adsp_data :adsp_data_phdr
361361

362362
.lit4 : ALIGN(4)
363363
{
@@ -366,7 +366,7 @@ SECTIONS
366366
*(.lit4.*)
367367
*(.gnu.linkonce.lit4.*)
368368
_lit4_end = ABSOLUTE(.);
369-
} >sdram0 :sdram0_phdr
369+
} >adsp_data :adsp_data_phdr
370370

371371
#include <zephyr/linker/common-ram.ld>
372372

@@ -389,7 +389,7 @@ SECTIONS
389389
*(COMMON)
390390
. = ALIGN (8);
391391
_bss_end = ABSOLUTE(.);
392-
} >sdram0 :sdram0_phdr
392+
} >adsp_data :adsp_data_phdr
393393

394394
.heap_mem (NOLOAD) : ALIGN(8)
395395
{
@@ -398,14 +398,14 @@ SECTIONS
398398
*(*.heap_mem)
399399
_heap_mem_end = ABSOLUTE(.);
400400

401-
} >sdram0 :sdram0_phdr
401+
} >adsp_data :adsp_data_phdr
402402

403403
/* stack */
404404
_end = ALIGN (8);
405405

406406
/DISCARD/ : { *(.note.GNU-stack) }
407-
_heap_sentry = SDRAM0_BASE + SDRAM0_SIZE;
408-
__stack = SDRAM0_BASE + SDRAM0_SIZE;
407+
_heap_sentry = DATA_BASE + DATA_SIZE;
408+
__stack = DATA_BASE + DATA_SIZE;
409409
.comment 0 : { *(.comment) }
410410
.debug 0 : { *(.debug) }
411411
.line 0 : { *(.line) }

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