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boards: openhwgroup: add CVA6 on Genesys 2 board
Adds support for the CVA6 CPU on a Genesys 2 FPGA board (https://github.com/openhwgroup/cva6). The SoC currently contains the CVA6 CPU with the SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, and I2C controller for on-board audio, a GPIO and the lowRISC ethernet subsystem. Two slightly different versions of the board are added, with a 64-bit and a 64-bit configuration of CVA6, respectively. Signed-off-by: Eric Ackermann <[email protected]>
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‎boards/openhwgroup/cv32a6_genesys_2/Kconfig.cv32a6_genesys_2

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_CV32A6_GENESYS_2
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select SOC_CV32A6

‎boards/openhwgroup/cv32a6_genesys_2/board.cmake

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg")
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board_runner_args(openocd "--use-elf")
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board_runner_args(openocd "--verify")
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board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x90000000 -work-area-size 16780000")
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

‎boards/openhwgroup/cv32a6_genesys_2/board.yml

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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board:
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name: cv32a6_genesys_2
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full_name: Genesys 2 with CV32A6 SoC
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vendor: openhwgroup
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socs:
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- name: cv32a6

‎boards/openhwgroup/cv32a6_genesys_2/cv32a6_genesys_2.dts

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/*
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* Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <openhwgroup/cv32a6.dtsi>
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/ {
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model = "Openhardwaregroup CV32A6 on Genesys 2";
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compatible = "openhwgroup,cv32a6_genesys_2";
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &memory0;
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};
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};
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&uart0 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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};
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&clint {
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status = "okay";
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};
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&eth {
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local-mac-address = [00 18 3e 02 e3 7f];
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status = "okay";
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};
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&xlnx_gpio {
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status = "okay";
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};

‎boards/openhwgroup/cv32a6_genesys_2/cv32a6_genesys_2_defconfig

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_INCLUDE_RESET_VECTOR=y
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CONFIG_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y
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CONFIG_CONSOLE_HANDLER=y
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CONFIG_XIP=n

‎boards/openhwgroup/cv32a6_genesys_2/doc/cv32a6_genesys_2.webp

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‎boards/openhwgroup/cv32a6_genesys_2/doc/index.rst

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.. zephyr:board:: cv32a6_genesys_2
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Overview
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********
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The Digilent Genesys 2 board features a Xilinx Kintex-7 FPGA which can run various softcore CPUs.
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In this configuration, the Genesys 2 is configured with a 32-bit version of the CVA6 RISC-V CPU.
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The SoC is configured with a memory controller interfacing with the Genesys' DRAM, PLIC and CLINT
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interrupt controllers, a UART device interfacing with the Genesys' USB UART, a RISC-V compatible
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debug module that interfaces with the Genesys' FTDI (USB JTAG) chip, a Xilinx SPI interface
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interfacing with the Genesys' SD card slot and a Xilinx GPIO interfacing with the Genesys' LEDs
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and switches.
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The complete hardware sources (see first reference) in conjunction with
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instructions for compiling and loading the configuration onto the Genesys 2 are available.
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See the following references for more information:
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- `CVA6 documentation`_
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- `Genesys 2 Reference Manual`_
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- `Genesys 2 Schematic`_
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Hardware
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********
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- CVA6 CPU with RV32imac instruction sets with PLIC, CLINT interrupt controllers.
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- 1 GB DDR3 DRAM
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- 10/100/1000 Ethernet with copper interface, lowRISC Ethernet MAC
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- ns16550a-compatible USB UART, 115200 baud
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- RISCV debug module, connected via on-board FTDI (USB JTAG)
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- Xilinx SPI controller, connected to microSD slot
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- Xilinx GPIO, connected to 7 switches and LEDs
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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Programming and Debugging
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*************************
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Loading the FPGA configuration
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==============================
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You need to build a bitstream with Xilinx Vivado and load it into the FPGA
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before you can load zephyr onto the board.
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Please refer to the CVA6 documentation for the required steps.
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This configuration is compatible with the following build targets:
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cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32, cv32a6_ima_sv32_fpga.
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Flashing
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========
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west flash is supported via the openocd runner.
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Here is an example for the :zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: cv32a6_genesys_2
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:goals: build flash
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Debugging
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=========
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west debug, attach and debugserver commands are supported via the openocd runner.
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Here is an example for the :zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: cv32a6_genesys_2
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:goals: build debug
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References
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**********
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.. _CVA6 documentation:
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https://github.com/openhwgroup/cva6
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.. _Genesys 2 Reference Manual:
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https://digilent.com/reference/programmable-logic/genesys-2/reference-manual
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.. _Genesys 2 Schematic:
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https://digilent.com/reference/_media/reference/programmable-logic/genesys-2/genesys-2_sch.pdf

‎boards/openhwgroup/cv32a6_genesys_2/support/ariane.cfg

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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# Based on the ariane.cfg from the cva6 project:
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# https://github.com/openhwgroup/cva6/blob/master/corev_apu/fpga/ariane.cfg
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adapter_khz 1000
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interface ftdi
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ftdi_vid_pid 0x0403 0x6010
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# Channel 1 is taken by Xilinx JTAG
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ftdi_channel 0
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# links:
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# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
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#
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# Bit MPSSE FT2232 JTAG Type Description
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# Bit0 TCK ADBUS0 TCK Out Clock Signal Output
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# Bit1 TDI ADBUS1 TDI Out Serial Data Out
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# Bit2 TDO ADBUS2 TDO In Serial Data In
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# Bit3 TMS ADBUS3 TMS Out Select Signal Out
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# Bit4 GPIOL0 ADBUS4 nTRST In/Out General Purpose I/O
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# this corresponds to the following in/out layout, with TMS initially set to 1
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ftdi_layout_init 0x0018 0x001b
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# we only have to specify nTRST, the others are assigned correctly by default
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ftdi_layout_signal nTRST -ndata 0x0010
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set _CHIPNAME riscv
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jtag newtap $_CHIPNAME cpu -irlen 5
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
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gdb_report_data_abort enable
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gdb_report_register_access_error enable
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riscv set_reset_timeout_sec 120
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riscv set_command_timeout_sec 120
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# prefer to use sba for system bus access
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riscv set_prefer_sba off
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# Try enabling address translation (only works for newer versions)
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if { [catch {riscv set_enable_virtual on} ] } {
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echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." }
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init
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halt
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echo "Ready for Remote Connections"

‎boards/openhwgroup/cv64a6_genesys_2/Kconfig.cv64a6_genesys_2

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_CV64A6_GENESYS_2
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select SOC_CV64A6_IMAFDC

‎boards/openhwgroup/cv64a6_genesys_2/board.cmake

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg")
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board_runner_args(openocd "--use-elf")
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board_runner_args(openocd "--verify")
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board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x90000000 -work-area-size 16780000")
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

‎boards/openhwgroup/cv64a6_genesys_2/board.yml

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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board:
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name: cv64a6_genesys_2
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full_name: Digilent Genesys 2 with CV64A6 SoC
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vendor: openhwgroup
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socs:
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- name: cv64a6_imafdc

‎boards/openhwgroup/cv64a6_genesys_2/cv64a6_genesys_2.dts

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/*
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* Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <openhwgroup/cv64a6.dtsi>
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/ {
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model = "Openhardwaregroup CV64A6 on Genesys 2";
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compatible = "openhwgroup,cv64a6_genesys_2";
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &memory0;
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};
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};
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&uart0 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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};
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&clint{
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status = "okay";
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};
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&dma0 {
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status = "disabled";
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};
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&eth {
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local-mac-address = [00 18 3e 02 e3 7f];
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status = "okay";
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};
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&xlnx_gpio {
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status = "okay";
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};

‎boards/openhwgroup/cv64a6_genesys_2/cv64a6_genesys_2_defconfig

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_INCLUDE_RESET_VECTOR=y
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CONFIG_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y
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CONFIG_CONSOLE_HANDLER=y
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CONFIG_XIP=n

‎boards/openhwgroup/cv64a6_genesys_2/doc/cv64a6_genesys_2.webp

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Binary file not shown.

‎boards/openhwgroup/cv64a6_genesys_2/doc/index.rst

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.. zephyr:board:: cv64a6_genesys_2
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Overview
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********
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The Digilent Genesys 2 board features a Xilinx Kintex-7 FPGA which can run various softcore CPUs.
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In this configuration, the Genesys 2 is configured with a 64-bit version of the CVA6 RISC-V CPU.
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The SoC is configured with a memory controller interfacing with the Genesys' DRAM, PLIC and CLINT
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interrupt controllers, a UART device interfacing with the Genesys' USB UART, a RISC-V compatible
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debug module that interfaces with the Genesys' FTDI (USB JTAG) chip, a Xilinx SPI interface
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interfacing with the Genesys' SD card slot and a Xilinx GPIO interfacing with the Genesys' LEDs
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and switches.
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The complete hardware sources (see first reference) in conjunction with
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instructions for compiling and loading the configuration onto the Genesys 2 are available.
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See the following references for more information:
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- `CVA6 documentation`_
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- `Genesys 2 Reference Manual`_
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- `Genesys 2 Schematic`_
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Hardware
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********
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- CVA6 CPU with RV64imafdc instruction sets and an SV39 MMU
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- 1 GB DDR3 DRAM
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- 10/100/1000 Ethernet with copper interface, lowRISC Ethernet MAC
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- ns16550a-compatible USB UART, 115200 baud
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- RISCV debug module, connected via on-board FTDI (USB JTAG)
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- Xilinx SPI controller, connected to microSD slot
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- Xilinx GPIO, connected to 7 switches and LEDs
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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Programming and Debugging
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*************************
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Loading the FPGA configuration
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==============================
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You need to build a bitstream with Xilinx Vivado and load it into the FPGA
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before you can load zephyr onto the board.
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Please refer to the CVA6 documentation for the required steps.
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This configuration is compatible with the following build target: cv64a6_imafdc_sv39
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Flashing
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========
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west flash is supported via the openocd runner.
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Here is an example for the :zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: cv64a6_genesys_2
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:goals: build flash
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Debugging
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=========
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west debug, attach and debugserver commands are supported via the openocd runner.
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Here is an example for the :zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: cv64a6_genesys_2
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:goals: build debug
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References
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**********
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.. _CVA6 documentation:
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https://github.com/openhwgroup/cva6
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.. _Genesys 2 Reference Manual:
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https://digilent.com/reference/programmable-logic/genesys-2/reference-manual
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.. _Genesys 2 Schematic:
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https://digilent.com/reference/_media/reference/programmable-logic/genesys-2/genesys-2_sch.pdf

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