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Bradley Bolen
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arch: arm: Add Cortex-R support
This adds initial Cortex-R support for interrupts and context switching. Signed-off-by: Bradley Bolen <[email protected]>
1 parent 688196d commit a97a908

34 files changed

+1247
-75
lines changed

‎arch/arm/core/CMakeLists.txt

+2
Original file line numberDiff line numberDiff line change
@@ -25,3 +25,5 @@ zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
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add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M cortex_m)
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add_subdirectory_ifdef(CONFIG_ARM_CORE_MPU cortex_m/mpu)
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add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M_HAS_CMSE cortex_m/cmse)
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add_subdirectory_ifdef(CONFIG_CPU_CORTEX_R cortex_r)

‎arch/arm/core/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -26,6 +26,66 @@ config CPU_CORTEX_M
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help
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This option signifies the use of a CPU of the Cortex-M family.
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config CPU_CORTEX_R
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bool
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select CPU_CORTEX
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select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
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select HAS_FLASH_LOAD_OFFSET
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select HAS_DTS
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select ARCH_HAS_STACK_PROTECTION if ARM_CORE_MPU
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select ARCH_HAS_USERSPACE if ARM_CORE_MPU
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help
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This option signifies the use of a CPU of the Cortex-R family.
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config ISA_THUMB2
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bool
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help
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From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
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Thumb-2 technology is the instruction set underlying the ARM Cortex
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architecture which provides enhanced levels of performance, energy
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efficiency, and code density for a wide range of embedded
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applications.
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Thumb-2 technology builds on the success of Thumb, the innovative
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high code density instruction set for ARM microprocessor cores, to
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increase the power of the ARM microprocessor core available to
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developers of low cost, high performance systems.
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The technology is backwards compatible with existing ARM and Thumb
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solutions, while significantly extending the features available to
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the Thumb instructions set. This allows more of the application to
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benefit from the best in class code density of Thumb.
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60+
For performance optimized code Thumb-2 technology uses 31 percent
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less memory to reduce system cost, while providing up to 38 percent
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higher performance than existing high density code, which can be used
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to prolong battery-life or to enrich the product feature set. Thumb-2
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technology is featured in the processor, and in all ARMv7
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architecture-based processors.
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config ISA_ARM
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bool
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help
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From: https://developer.arm.com/products/architecture/instruction-sets/a32-and-t32-instruction-sets
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A32 instructions, known as Arm instructions in pre-Armv8 architectures,
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are 32 bits wide, and are aligned on 4-byte boundaries. A32 instructions
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are supported by both A-profile and R-profile architectures.
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A32 was traditionally used in applications requiring the highest
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performance, or for handling hardware exceptions such as interrupts and
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processor start-up. Much of its functionality was subsumed into T32 with
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the introduction of Thumb-2 technology.
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config DATA_ENDIANNESS_LITTLE
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bool
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default y if CPU_CORTEX
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help
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This is driven by the processor implementation, since it is fixed in
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hardware. The board should set this value to 'n' if the data is
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implemented as big endian.
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config CPU_HAS_SYSTICK
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bool
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# Omit prompt to signify "hidden" option
@@ -94,6 +154,38 @@ config ARM_NONSECURE_FIRMWARE
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resources of the Cortex-M MCU, and, therefore, it shall avoid
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accessing them.
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config STACK_ALIGN_DOUBLE_WORD
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bool "Align stacks on double-words (8 octets)"
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default y
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help
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This is needed to conform to AAPCS, the procedure call standard for
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the ARM. It wastes stack space.
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config RUNTIME_NMI
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bool
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prompt "Attach an NMI handler at runtime"
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select REBOOT
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help
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The kernel provides a simple NMI handler that simply hangs in a tight
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loop if triggered. This fills the requirement that there must be an
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NMI handler installed when the CPU boots. If a custom handler is
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needed, enable this option and attach it via _NmiHandlerSet().
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config FAULT_DUMP
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int "Fault dump level"
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default 2
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range 0 2
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help
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Different levels for display information when a fault occurs.
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2: The default. Display specific and verbose information. Consumes
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the most memory (long strings).
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1: Display general and short information. Consumes less memory
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(short strings).
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0: Off.
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menu "Architecture Floating Point Options"
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depends on CPU_HAS_FPU
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@@ -122,6 +214,7 @@ endchoice
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endmenu
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source "arch/arm/core/cortex_m/Kconfig"
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source "arch/arm/core/cortex_r/Kconfig"
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if CPU_HAS_MPU
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source "arch/arm/core/cortex_m/mpu/Kconfig"

‎arch/arm/core/cortex_m/Kconfig

+1-70
Original file line numberDiff line numberDiff line change
@@ -73,34 +73,6 @@ config CPU_CORTEX_M7
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if CPU_CORTEX_M
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config ISA_THUMB2
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bool
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# Omit prompt to signify "hidden" option
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help
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From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
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82-
Thumb-2 technology is the instruction set underlying the ARM Cortex
83-
architecture which provides enhanced levels of performance, energy
84-
efficiency, and code density for a wide range of embedded
85-
applications.
86-
87-
Thumb-2 technology builds on the success of Thumb, the innovative
88-
high code density instruction set for ARM microprocessor cores, to
89-
increase the power of the ARM microprocessor core available to
90-
developers of low cost, high performance systems.
91-
92-
The technology is backwards compatible with existing ARM and Thumb
93-
solutions, while significantly extending the features available to
94-
the Thumb instructions set. This allows more of the application to
95-
benefit from the best in class code density of Thumb.
96-
97-
For performance optimized code Thumb-2 technology uses 31 percent
98-
less memory to reduce system cost, while providing up to 38 percent
99-
higher performance than existing high density code, which can be used
100-
to prolong battery-life or to enrich the product feature set. Thumb-2
101-
technology is featured in the processor, and in all ARMv7
102-
architecture-based processors.
103-
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config CPU_CORTEX_M_HAS_BASEPRI
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bool
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# Omit prompt to signify "hidden" option
@@ -267,50 +239,9 @@ config LDREX_STREX_AVAILABLE
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bool
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default y
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config DATA_ENDIANNESS_LITTLE
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bool
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default y
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help
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This is driven by the processor implementation, since it is fixed in
275-
hardware. The board should set this value to 'n' if the data is
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implemented as big endian.
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config STACK_ALIGN_DOUBLE_WORD
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bool
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prompt "Align stacks on double-words (8 octets)"
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default y
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help
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This is needed to conform to AAPCS, the procedure call standard for
284-
the ARM. It wastes stack space.
285-
286-
config RUNTIME_NMI
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bool
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prompt "Attach an NMI handler at runtime"
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select REBOOT
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help
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The kernel provides a simple NMI handler that simply hangs in a tight
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loop if triggered. This fills the requirement that there must be an
293-
NMI handler installed when the CPU boots. If a custom handler is
294-
needed, enable this option and attach it via _NmiHandlerSet().
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config FAULT_DUMP
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int
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prompt "Fault dump level"
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default 2
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range 0 2
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help
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Different levels for display information when a fault occurs.
303-
304-
2: The default. Display specific and verbose information. Consumes
305-
the most memory (long strings).
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307-
1: Display general and short information. Consumes less memory
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(short strings).
309-
310-
0: Off.
311-
312242
config XIP
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default y
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314245
endmenu
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menu "ARM Cortex-M0/M0+/M3/M4/M7/M23/M33 options"

‎arch/arm/core/cortex_r/CMakeLists.txt

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@@ -0,0 +1,8 @@
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zephyr_library()
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zephyr_library_sources(
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vector_table.S
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reset.S
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fault.c
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exceptions.c
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)

‎arch/arm/core/cortex_r/Kconfig

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@@ -0,0 +1,98 @@
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# Kconfig - ARM Cortex-R platform configuration options
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#
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# Copyright (c) 2018 Marvell
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# Copyright (c) 2018 Lexmark International, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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# NOTE: We have the specific core implementations first and outside of the
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# if CPU_CORTEX_R block so that SoCs can select which core they are using
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# without having to select all the options related to that core. Everything
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# else is captured inside the if CPU_CORTEX_R block so they are not exposed
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# if one selects a different ARM Cortex Family (Cortex-A or Cortex-M)
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config CPU_CORTEX_R4
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bool
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select CPU_CORTEX_R
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select ARMV7_R
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select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU
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help
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This option signifies the use of a Cortex-R4 CPU
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if CPU_CORTEX_R
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config ARMV7_R
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bool
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select ATOMIC_OPERATIONS_BUILTIN
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select ISA_ARM
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help
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This option signifies the use of an ARMv7-R processor
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implementation, or the use of an ARMv8-R processor
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implementation supporting the Main Extension.
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Notes:
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- A Processing Element (PE) with the Main Extension is also
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referred to as a Mainline Implementation.
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- ARMv7-R compatibility requires the Main Extension.
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From https://developer.arm.com/products/architecture/m-profile:
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The Main Extension provides backwards compatibility
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with ARMv7-R.
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config ARMV7_R_FP
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bool
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depends on ARMV7_R
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help
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This option signifies the use of an ARMv7-R processor
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implementation, or the use of an ARMv8-R processor
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implementation supporting the Floating-Point Extension.
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config ARMV7_EXCEPTION_STACK_SIZE
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int "Undefined Instruction and Abort stack size (in bytes)"
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default 256
56+
help
57+
This option specifies the size of the stack used by the undefined
58+
instruction and data abort exception handlers.
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config ARMV7_FIQ_STACK_SIZE
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int "FIQ stack size (in bytes)"
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default 256
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help
64+
This option specifies the size of the stack used by the FIQ handler.
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config ARMV7_SVC_STACK_SIZE
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int "SVC stack size (in bytes)"
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default 512
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help
70+
This option specifies the size of the stack used by the SVC handler.
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config ARMV7_SYS_STACK_SIZE
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int "SYS stack size (in bytes)"
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default 1024
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help
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This option specifies the size of the stack used by the system mode.
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menu "ARM Cortex-R options"
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depends on CPU_CORTEX_R
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config RUNTIME_NMI
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def_bool y
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config LDREX_STREX_AVAILABLE
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def_bool y
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config GEN_ISR_TABLES
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default y
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90+
config GEN_IRQ_VECTOR_TABLE
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default n
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config XIP
94+
default y
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endmenu
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endif # CPU_CORTEX_R

‎arch/arm/core/cortex_r/exceptions.c

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@@ -0,0 +1,13 @@
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/*
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* Copyright (c) 2018 Lexmark International, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
5+
*/
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#include <kernel.h>
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9+
K_THREAD_STACK_DEFINE(_fiq_stack, CONFIG_ARMV7_FIQ_STACK_SIZE);
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K_THREAD_STACK_DEFINE(_abort_stack, CONFIG_ARMV7_EXCEPTION_STACK_SIZE);
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K_THREAD_STACK_DEFINE(_undef_stack, CONFIG_ARMV7_EXCEPTION_STACK_SIZE);
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K_THREAD_STACK_DEFINE(_svc_stack, CONFIG_ARMV7_SVC_STACK_SIZE);
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K_THREAD_STACK_DEFINE(_sys_stack, CONFIG_ARMV7_SYS_STACK_SIZE);

‎arch/arm/core/cortex_r/fault.c

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@@ -0,0 +1,27 @@
1+
/*
2+
* Copyright (c) 2018 Lexmark International, Inc.
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include <kernel.h>
8+
9+
/**
10+
*
11+
* @brief Fault handler
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*
13+
* This routine is called when fatal error conditions are detected by hardware
14+
* and is responsible only for reporting the error. Once reported, it then
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* invokes the user provided routine _SysFatalErrorHandler() which is
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* responsible for implementing the error handling policy.
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*
18+
* This is a stub for more exception handling code to be added later.
19+
*/
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void _Fault(const NANO_ESF *esf)
21+
{
22+
_SysFatalErrorHandler(_NANO_ERR_HW_EXCEPTION, esf);
23+
}
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25+
void _FaultInit(void)
26+
{
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}

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