Skip to content

Commit c3e9879

Browse files
FRASTMcarlescufi
FRASTM
authored and
carlescufi
committed
tests: drivers: clock control for the stm32H5 serie core
Adds the configurations for testing the clock controller driver of the stm32H5 serie coreon stm32h573i disco kit Signed-off-by: Francois Ramu <[email protected]>
1 parent 951c9e3 commit c3e9879

20 files changed

+705
-0
lines changed

‎tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/CMakeLists.txt

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
# SPDX-License-Identifier: Apache-2.0
2+
3+
cmake_minimum_required(VERSION 3.20.0)
4+
5+
find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
6+
project(stm32_clock_configuration_h5)
7+
8+
FILE(GLOB app_sources src/*.c)
9+
target_sources(app PRIVATE ${app_sources})

‎tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/clear_clocks.overlay

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
/*
2+
* Copyright (c) 2021 Linaro Limited
3+
* Copyright (c) 2023 STMicroelectronics
4+
*
5+
* SPDX-License-Identifier: Apache-2.0
6+
*/
7+
8+
/*
9+
* Warning: This overlay clears clocks back to a state equivalent to what could
10+
* be found in stm32h5.dtsi
11+
*/
12+
13+
&clk_hse {
14+
status = "disabled";
15+
/delete-property/ clock-frequency;
16+
/delete-property/ hse-bypass;
17+
};
18+
19+
&clk_hsi {
20+
status = "disabled";
21+
/delete-property/ hsi-div;
22+
};
23+
24+
&clk_lse {
25+
status = "disabled";
26+
};
27+
28+
&clk_csi {
29+
status = "disabled";
30+
};
31+
32+
&pll {
33+
/delete-property/ div-m;
34+
/delete-property/ mul-n;
35+
/delete-property/ div-p;
36+
/delete-property/ div-q;
37+
/delete-property/ div-r;
38+
/delete-property/ clocks;
39+
status = "disabled";
40+
};
41+
42+
43+
&pll2 {
44+
/delete-property/ div-m;
45+
/delete-property/ mul-n;
46+
/delete-property/ div-p;
47+
/delete-property/ div-q;
48+
/delete-property/ div-r;
49+
/delete-property/ clocks;
50+
status = "disabled";
51+
};
52+
53+
&rcc {
54+
/delete-property/ clocks;
55+
/delete-property/ clock-frequency;
56+
/delete-property/ ahb-prescaler;
57+
/delete-property/ apb1-prescaler;
58+
/delete-property/ apb2-prescaler;
59+
/delete-property/ apb3-prescaler;
60+
};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/csi4.overlay

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
/*
2+
* Copyright (c) 2021 Linaro Limited
3+
* Copyright (c) 2023 STMicroelectronics
4+
*
5+
* SPDX-License-Identifier: Apache-2.0
6+
*/
7+
8+
/*
9+
* Warning: This overlay performs configuration from clean sheet.
10+
* It is assumed that it is applied after clear_clocks.overlay file.
11+
*/
12+
13+
&clk_csi {
14+
status = "okay";
15+
};
16+
17+
&rcc {
18+
clocks = <&clk_csi>;
19+
clock-frequency = <DT_FREQ_M(4)>;
20+
ahb-prescaler = <1>;
21+
apb1-prescaler = <1>;
22+
apb2-prescaler = <1>;
23+
apb3-prescaler = <1>;
24+
};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/hse24.overlay

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
/*
2+
* Copyright (c) 2021 Linaro Limited
3+
* Copyright (c) 2023 STMicroelectronics
4+
*
5+
* SPDX-License-Identifier: Apache-2.0
6+
*/
7+
8+
/*
9+
* Warning: This overlay performs configuration from clean sheet.
10+
* It is assumed that it is applied after clear_clocks.overlay file.
11+
*/
12+
13+
/*
14+
* Warning: HSE frequency differs on available boards, hence:
15+
* This configuration is only available nucleo_h503rb
16+
*/
17+
18+
&clk_hse {
19+
status = "okay";
20+
clock-frequency = <DT_FREQ_M(24)>;
21+
};
22+
23+
&rcc {
24+
clocks = <&clk_hse>;
25+
clock-frequency = <DT_FREQ_M(24)>;
26+
ahb-prescaler = <1>;
27+
apb1-prescaler = <1>;
28+
apb2-prescaler = <1>;
29+
apb3-prescaler = <1>;
30+
};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/hse25.overlay

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,31 @@
1+
/*
2+
* Copyright (c) 2021 Linaro Limited
3+
* Copyright (c) 2023 STMicroelectronics
4+
*
5+
* SPDX-License-Identifier: Apache-2.0
6+
*/
7+
8+
/*
9+
* Warning: This overlay performs configuration from clean sheet.
10+
* It is assumed that it is applied after clear_clocks.overlay file.
11+
*/
12+
13+
/*
14+
* Warning: HSE frequency differs on available boards, hence:
15+
* This configuration is only available stm32h573 disco kit
16+
*/
17+
18+
&clk_hse {
19+
clock-frequency = <DT_FREQ_M(25)>;
20+
hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
21+
status = "okay";
22+
};
23+
24+
&rcc {
25+
clocks = <&clk_hse>;
26+
clock-frequency = <DT_FREQ_M(25)>;
27+
ahb-prescaler = <1>;
28+
apb1-prescaler = <1>;
29+
apb2-prescaler = <1>;
30+
apb3-prescaler = <1>;
31+
};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/hsi_32.overlay

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
/*
2+
* Copyright (c) 2021 Linaro Limited
3+
* Copyright (c) 2023 STMicroelectronics
4+
*
5+
* SPDX-License-Identifier: Apache-2.0
6+
*/
7+
8+
/*
9+
* Warning: This overlay performs configuration from clean sheet.
10+
* It is assumed that it is applied after clear_clocks.overlay file.
11+
*/
12+
13+
&clk_hsi {
14+
hsi-div = <2>; /* HSI RC: 64MHz, hsi_clk = 32MHz */
15+
status = "okay";
16+
};
17+
18+
&rcc {
19+
clocks = <&clk_hsi>;
20+
clock-frequency = <DT_FREQ_M(32)>;
21+
ahb-prescaler = <1>;
22+
apb1-prescaler = <1>;
23+
apb2-prescaler = <1>;
24+
apb3-prescaler = <1>;
25+
};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_csi_100.overlay

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,35 @@
1+
/*
2+
* Copyright (c) 2021 Linaro Limited
3+
* Copyright (c) 2023 STMicroelectronics
4+
*
5+
* SPDX-License-Identifier: Apache-2.0
6+
*/
7+
8+
/*
9+
* Warning: This overlay performs configuration from clean sheet.
10+
* It is assumed that it is applied after clear_clocks.overlay file.
11+
*/
12+
13+
&clk_csi {
14+
status = "okay";
15+
};
16+
17+
/* Test another couple of M-div N-mul to obtain 100MHz from the CSI */
18+
&pll {
19+
div-m = <1>;
20+
mul-n = <50>;
21+
div-p = <2>;
22+
div-q = <2>;
23+
div-r = <2>;
24+
clocks = <&clk_csi>;
25+
status = "okay";
26+
};
27+
28+
&rcc {
29+
clocks = <&pll>;
30+
clock-frequency = <DT_FREQ_M(100)>;
31+
ahb-prescaler = <1>;
32+
apb1-prescaler = <1>;
33+
apb2-prescaler = <1>;
34+
apb3-prescaler = <1>;
35+
};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_csi_240.overlay

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,35 @@
1+
/*
2+
* Copyright (c) 2021 Linaro Limited
3+
* Copyright (c) 2023 STMicroelectronics
4+
*
5+
* SPDX-License-Identifier: Apache-2.0
6+
*/
7+
8+
/*
9+
* Warning: This overlay performs configuration from clean sheet.
10+
* It is assumed that it is applied after clear_clocks.overlay file.
11+
*/
12+
13+
&clk_csi {
14+
status = "okay";
15+
};
16+
17+
/* Test another couple of M-div N-mul to obtain 240MHz from the CSI */
18+
&pll {
19+
div-m = <1>;
20+
mul-n = <120>;
21+
div-p = <2>;
22+
div-q = <2>;
23+
div-r = <2>;
24+
clocks = <&clk_csi>;
25+
status = "okay";
26+
};
27+
28+
&rcc {
29+
clocks = <&pll>;
30+
clock-frequency = <DT_FREQ_M(240)>;
31+
ahb-prescaler = <1>;
32+
apb1-prescaler = <1>;
33+
apb2-prescaler = <1>;
34+
apb3-prescaler = <1>;
35+
};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_csi_ahb_2_100.overlay

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
/*
2+
* Copyright (c) 2021 Linaro Limited
3+
* Copyright (c) 2023 STMicroelectronics
4+
*
5+
* SPDX-License-Identifier: Apache-2.0
6+
*/
7+
8+
/*
9+
* Warning: This overlay performs configuration from clean sheet.
10+
* It is assumed that it is applied after clear_clocks.overlay file.
11+
*/
12+
13+
&clk_csi {
14+
status = "okay";
15+
};
16+
17+
&pll {
18+
div-m = <1>;
19+
mul-n = <100>;
20+
div-p = <2>;
21+
div-q = <2>;
22+
div-r = <2>;
23+
clocks = <&clk_csi>;
24+
status = "okay";
25+
};
26+
27+
&rcc {
28+
clocks = <&pll>;
29+
ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
30+
clock-frequency = <DT_FREQ_M(100)>;
31+
apb1-prescaler = <1>;
32+
apb2-prescaler = <1>;
33+
apb3-prescaler = <1>;
34+
};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_hse24_100.overlay

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
/*
2+
* Copyright (c) 2021 Linaro Limited
3+
* Copyright (c) 2023 STMicroelectronics
4+
*
5+
* SPDX-License-Identifier: Apache-2.0
6+
*/
7+
8+
/*
9+
* Warning: This overlay performs configuration from clean sheet.
10+
* It is assumed that it is applied after clear_clocks.overlay file.
11+
*/
12+
13+
/*
14+
* Warning: HSE frequency differs on available boards, hence:
15+
* This configuration is only available nucleo_h503rb
16+
*/
17+
18+
&clk_hse {
19+
status = "okay";
20+
clock-frequency = <DT_FREQ_M(24)>;
21+
};
22+
23+
&pll {
24+
div-m = <6>;
25+
mul-n = <50>;
26+
div-p = <2>;
27+
div-q = <2>;
28+
div-r = <2>;
29+
clocks = <&clk_hse>;
30+
status = "okay";
31+
};
32+
33+
&rcc {
34+
clocks = <&pll>;
35+
clock-frequency = <DT_FREQ_M(100)>;
36+
ahb-prescaler = <1>;
37+
apb1-prescaler = <1>;
38+
apb2-prescaler = <1>;
39+
apb3-prescaler = <1>;
40+
};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_hse24_240.overlay

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
/*
2+
* Copyright (c) 2021 Linaro Limited
3+
* Copyright (c) 2023 STMicroelectronics
4+
*
5+
* SPDX-License-Identifier: Apache-2.0
6+
*/
7+
8+
/*
9+
* Warning: This overlay performs configuration from clean sheet.
10+
* It is assumed that it is applied after clear_clocks.overlay file.
11+
*/
12+
13+
/*
14+
* Warning: HSE frequency differs on available boards, hence:
15+
* This configuration is only available nucleo_h503rb
16+
*/
17+
18+
&clk_hse {
19+
status = "okay";
20+
clock-frequency = <DT_FREQ_M(24)>;
21+
};
22+
23+
&pll {
24+
div-m = <2>;
25+
mul-n = <40>;
26+
div-p = <2>;
27+
div-q = <2>;
28+
div-r = <2>;
29+
clocks = <&clk_hse>;
30+
status = "okay";
31+
};
32+
33+
&rcc {
34+
clocks = <&pll>;
35+
clock-frequency = <DT_FREQ_M(240)>;
36+
ahb-prescaler = <1>;
37+
apb1-prescaler = <1>;
38+
apb2-prescaler = <1>;
39+
apb3-prescaler = <1>;
40+
};

0 commit comments

Comments
 (0)