board: Add PWM support for colibri_imx7d_m4

Adds configurations and pinmux to support PWM on colibri_imx7d_m4

Signed-off-by: Diego Sueiro <[email protected]>

Author: diegosueiro

boards/arm/colibri_imx7d_m4/Kconfig.defconfig

@@ -58,5 +58,12 @@ config I2C_4
 
 endif # I2C_IMX
 
+if PWM_IMX
+
+config PWM_1
+	def_bool y
+
+endif # PWM_IMX
+
 
 endif # BOARD_COLIBRI_IMX7D_M4

boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.dts

@@ -19,6 +19,7 @@
 		led0   = &green_led;
 		sw0    = &user_switch_1;
 		i2c-4  = &i2c4;
+		pwm-1  = &pwm1;
 	};
 
 	chosen {
@@ -63,3 +64,7 @@
 &i2c4 {
 	status = "ok";
 };
+
+&pwm1 {
+	status = "ok";
+};

boards/arm/colibri_imx7d_m4/doc/colibri_imx7d_m4.rst

@@ -84,6 +84,8 @@ supports the following hardware features on the Cortex M4 Core:
 +-----------+------------+-------------------------------------+
 | I2C       | on-chip    | i2c                                 |
 +-----------+------------+-------------------------------------+
+| PWM       | on-chip    | pwm                                 |
++-----------+------------+-------------------------------------+
 | UART      | on-chip    | serial port-polling;                |
 |           |            | serial port-interrupt               |
 +-----------+------------+-------------------------------------+
@@ -115,6 +117,8 @@ was tested with the following pinmux controller configuration.
 +---------------+-----------------+---------------------------+
 | SODIMM_196    | I2C4_SCL        | I2C_SCL                   |
 +---------------+-----------------+---------------------------+
+| SODIMM_59     | PWM1/GPIO1_IO08 | PWM                       |
++---------------+-----------------+---------------------------+
 
 System Clock
 ============

boards/arm/colibri_imx7d_m4/pinmux.c

@@ -144,6 +144,46 @@ static int colibri_imx7d_m4_pinmux_init(struct device *dev)
 		IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_HYS_MASK;
 #endif  /* CONFIG_I2C_4 */
 
+#ifdef CONFIG_PWM_1
+	IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 =
+		IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE(7);
+	IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 =
+		IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PE_MASK |
+		IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PS(3)   |
+		IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE(0)  |
+		IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_HYS_MASK;
+#endif /* CONFIG_PWM_1 */
+
+#ifdef CONFIG_PWM_2
+	IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 =
+		IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE(7);
+	IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 =
+		IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PE_MASK |
+		IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PS(3)   |
+		IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE(0)  |
+		IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_HYS_MASK;
+#endif /* CONFIG_PWM_2 */
+
+#ifdef CONFIG_PWM_3
+	IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 =
+		IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE(7);
+	IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 =
+		IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PE_MASK |
+		IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PS(3)   |
+		IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE(0)  |
+		IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_HYS_MASK;
+#endif /* CONFIG_PWM_3 */
+
+#ifdef CONFIG_PWM_4
+	IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 =
+		IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE(7);
+	IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 =
+		IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PE_MASK |
+		IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PS(3)   |
+		IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE(0)  |
+		IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_HYS_MASK;
+#endif /* CONFIG_PWM_4 */
+
 	return 0;
 
 }