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soc: add OpenHW Group CVA6 SoC
Adds support for the CVA6 family of RISC-V CPUs. CVA6 is commonly found as a soft core CPU on FPGA designs. Different configurations and instruction set extensions can be configured, and different SoCs targeting various FPGA boards are available. This commit adds support for the 32-bit and 64-bit configurations of CVA6, as well as three slightly different SoCs (a minimal 32-bit configuration, a 64-bit configuration without FPU, a 64-bit configuration with FPU). Signed-off-by: Eric Ackermann <[email protected]>
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‎dts/bindings/cpu/openhwgroup,cva6.yaml

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# Copyright (c) 2025 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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description: OpenHW Group CVA6 CPU
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compatible: "openhwgroup,cva6"
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include: riscv,cpus.yaml
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properties:
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timebase-frequency:
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required: true
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type: int
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description: Clock speed at which the core-local machine timer operates.

‎dts/riscv/openhwgroup/cv32a6.dtsi

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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright 2024 CISPA Helmholtz Center for Information Security
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*/
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#include <freq.h>
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#include "cva6.dtsi"
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/*
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* Least common denominator of CVA6 32-bit CPUs: no FPU, no compressed instructions,
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* no MMU, no PMP.
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* Boards can overwrite the node if additional configurations are available.
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*/
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/ {
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cpus_0: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu_0: cpu@0 {
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clock-frequency = <DT_FREQ_M(50)>;
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timebase-frequency = <DT_FREQ_M(25)>;
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device_type = "cpu";
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compatible = "openhwgroup,cva6";
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riscv,isa = "rv32ima";
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/* overwrite in board configuration if sv32 MMU is enabled */
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mmu-type = "riscv,none";
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reg = <0>;
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status = "okay";
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hlic: interrupt-controller {
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#interrupt-cells = <0x01>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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status = "okay";
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};
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};
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};
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};

‎dts/riscv/openhwgroup/cv64a6.dtsi

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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright 2024 CISPA Helmholtz Center for Information Security
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*/
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#include <freq.h>
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#include "cva6.dtsi"
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/*
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* Application-class configuration of CVA6 64-bit CPUs:
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* FPU for 32-bit and 64-bit floats, SV39 MMU.
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*
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*/
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/ {
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cpus_0: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu_0: cpu@0 {
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clock-frequency = <DT_FREQ_M(50)>;
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timebase-frequency = <DT_FREQ_M(25)>;
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device_type = "cpu";
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compatible = "openhwgroup,cva6";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv39";
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reg = <0>;
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status = "okay";
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hlic: interrupt-controller {
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#interrupt-cells = <0x01>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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status = "okay";
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};
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};
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};
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};

‎dts/riscv/openhwgroup/cva6.dtsi

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/*
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* SPDX-License-Identifier: Apache-2.0
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* Copyright 2024 CISPA Helmholtz Center for Information Security
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*/
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#include <freq.h>
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/*
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* CVA6 SoC without CPU, which comes in 32 and 64 bit variants
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*/
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/ {
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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clocks {
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clk_cpu {
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#clock-cells = <0x00>;
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clock-frequency = <DT_FREQ_M(50)>;
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compatible = "fixed-clock";
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};
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clk_bus: clk_bus_0 {
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#clock-cells = <0x00>;
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clock-frequency = <DT_FREQ_M(50)>;
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compatible = "fixed-clock";
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};
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};
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soc {
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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/* Xilinx MIG memory controller */
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memory0: memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x40000000>;
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status = "okay";
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};
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/* RISC-V Platform-level interrupt controller */
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plic: interrupt-controller@c000000 {
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compatible = "sifive,plic-1.0.0";
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupts-extended = <&hlic 11 &hlic 9>;
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reg = <0x0c000000 0x4000000>;
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riscv,max-priority = <7>;
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riscv,ndev = <30>;
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status = "okay";
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};
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/* USB UART */
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uart0: serial@10000000 {
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clock-frequency = <50000000>;
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clocks = <&clk_bus>;
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compatible = "ns16550";
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current-speed = <115200>;
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device_type = "serial";
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reg = <0x10000000 0x10000>;
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reg-shift = <0x02>;
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parity = "none";
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stop-bits = "1";
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data-bits = <8>;
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interrupt-parent = <&plic>;
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interrupts = <1 0x04>;
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status = "disabled";
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};
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/* SPI controller, connected to SD card */
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spi0: axi_quad_spi@20000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "xlnx,xps-spi-2.00.a";
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reg = <0x20000000 0x10000>;
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xlnx,num-ss-bits = <0x01>;
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xlnx,num-transfer-bits = <0x8>;
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interrupts=<2 0x2>;
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interrupt-parent=<&plic>;
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clocks=<&clk_bus>;
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status = "disabled";
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};
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/*
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* Core-local interrupt controller according to RISC-V spec
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*/
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clint: clint@2000000 {
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compatible = "sifive,clint0";
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reg = <0x2000000 0x40000>;
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interrupts-extended = <&hlic 3 &hlic 7>;
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status = "disabled";
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};
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/*
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* Xilinx AXI DMA.
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* Part of the Xilinx AXI Ethernet Subsystem.
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* Only on CISPA board.
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*/
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dma0: dma@41e00000 {
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#dma-cells = <0x01>;
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clock-frequency = <DT_FREQ_M(50)>;
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clock-names = "s_axi_lite_aclk";
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clocks = <&clk_bus>;
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compatible = "xlnx,eth-dma";
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reg = <0x41e00000 0x10000>;
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xlnx,addrwidth = <0x40>;
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xlnx,include-dre;
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xlnx,num-queues = <0x1>;
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interrupt-parent = <&plic>;
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// TX - RX
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// active-high level-triggered
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interrupts = <8 4>, <9 4>;
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// TX and RX
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dma-channels = <2>;
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status = "disabled";
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};
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/*
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* LowRISC ethernet subsystem.
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* Only on OpenHW Group board.
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*/
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eth: lowrisc-eth@30000000 {
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compatible = "lowrisc-eth";
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device_type = "network";
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interrupt-parent = <&plic>;
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interrupts = <3 0>;
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reg = <0x0 0x30000000 0x0 0x8000>;
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status = "disabled";
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};
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/* Xilinx GPIO, connected to LEDs */
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xlnx_gpio: gpio@40000000 {
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#gpio-cells = <2>;
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compatible = "xlnx,xps-gpio-1.00.a";
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gpio-controller ;
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reg = <0x0 0x40000000 0x0 0x10000 >;
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xlnx,all-inputs = <0x0>;
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xlnx,all-inputs-2 = <0x0>;
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xlnx,dout-default = <0x0>;
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xlnx,dout-default-2 = <0x0>;
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xlnx,gpio-width = <0x8>;
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xlnx,gpio2-width = <0x8>;
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xlnx,is-dual = <0x1>;
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xlnx,tri-default = <0xffffffff>;
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xlnx,tri-default-2 = <0xffffffff>;
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status = "disabled";
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};
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};
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};

‎soc/openhwgroup/cva6/CMakeLists.txt

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# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(${SOC_SERIES})
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zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_CVA6_PROVIDE_NONSTANDARD_CACHE_OPTIONS soc_cache_management.c)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

‎soc/openhwgroup/cva6/Kconfig

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# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_OPENHWGROUP_CVA6
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config SOC_FAMILY_CVA6_PROVIDE_NONSTANDARD_CACHE_OPTIONS
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bool "Include non-standard cache management operations (currently global cache disable)"
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rsource "*/Kconfig"
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endif # SOC_FAMILY_OPENHWGROUP_CVA6

‎soc/openhwgroup/cva6/Kconfig.defconfig

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# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_OPENHWGROUP_CVA6
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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int
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default $(dt_node_int_prop_int,/cpus/cpu@0,timebase-frequency)
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config RISCV_SOC_INTERRUPT_INIT
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default y
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# highest implemented first-level interrupt is machine external, 11
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config 2ND_LVL_ISR_TBL_OFFSET
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default 12
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config 2ND_LVL_INTR_00_OFFSET
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default 11
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# 12 first level, 30 second level
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config MAX_IRQ_PER_AGGREGATOR
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default 42
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# one 2nd level aggregator (PLIC) with 30 interrupts
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# offset of 12
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config NUM_IRQS
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default 42
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config MULTI_LEVEL_INTERRUPTS
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default y
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config 2ND_LEVEL_INTERRUPTS
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default y
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# 1 PLIC
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config NUM_2ND_LEVEL_AGGREGATORS
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default 1
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config PLIC
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default y
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config 3RD_LEVEL_INTERRUPTS
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default n
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endif # SOC_FAMILY_OPENHWGROUP_CVA6

‎soc/openhwgroup/cva6/Kconfig.soc

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#Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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#SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_OPENHWGROUP_CVA6
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bool
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help
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CVA6 RISC-V CPUs, commonly used as soft cores on FPGAs.
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There is a 64-bit version with imafdc extensions and sv39 MMU and
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several 32-bit configurations, optionally with up to imafdc and sv32 MMU.
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config SOC_FAMILY
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default "openhwgroup_cva6" if SOC_FAMILY_OPENHWGROUP_CVA6
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rsource "*/Kconfig.soc"

‎soc/openhwgroup/cva6/cv32a6/CMakeLists.txt

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources()
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zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_OPENHWGROUP_CVA6 ".")

‎soc/openhwgroup/cva6/cv32a6/Kconfig

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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# RISCV32 OpenHW Group cva6 configuration options
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config SOC_CV32A6
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select RISCV
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select RISCV_PRIVILEGED
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select ATOMIC_OPERATIONS_BUILTIN
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select RISCV_HAS_PLIC
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select USE_SWITCH_SUPPORTED
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select USE_SWITCH
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select CPU_HAS_FPU
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select CPU_HAS_FPU_DOUBLE_PRECISION
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select SCHED_IPI_SUPPORTED
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select CPU_HAS_DCACHE
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select CPU_HAS_ICACHE

‎soc/openhwgroup/cva6/cv32a6/Kconfig.soc

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_CV32A6
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bool
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select SOC_FAMILY_OPENHWGROUP_CVA6
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help
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CVA6 32-bit RISC-V CPUs, commonly used as soft cores on FPGAs.
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This configuration works with the upstream project (https://github.com/openhwgroup/cva6).
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config SOC_CV32A6
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bool
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select SOC_SERIES_CV32A6
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help
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Minimal CVA6 core in 32-bit configuration: ima extensions, no MMU or PMP,
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SoC with CLINT, PLIC, UART, SPI, and Ethernet (Xilinx or lowRISC).
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config SOC_SERIES
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default "cv32a6" if SOC_SERIES_CV32A6
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config SOC
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default "cv32a6" if SOC_CV32A6

‎soc/openhwgroup/cva6/cv64a6/CMakeLists.txt

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources()
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zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_OPENHWGROUP_CVA6 ".")

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