soc: intel_adsp: ace30: set MMU permissions for rom_ext sections

This patch will set MMU permissions for rom_ext sections
It is possible to call the rom_ext code located in IMR

Signed-off-by: Adrian Bonislawski <[email protected]>

Author: abonislawski

soc/intel/intel_adsp/ace/include/adsp_memory.h

@@ -68,6 +68,13 @@
 #define IMR_BOOT_LDR_STACK_BASE		(IMR_BOOT_LDR_BSS_BASE + IMR_BOOT_LDR_BSS_SIZE)
 #define IMR_BOOT_LDR_STACK_SIZE		0x1000
 
+/* ROM_EXT sections, used only for MMU mapping */
+#define IMR_ROM_EXT_OFFSET		0xB000
+#define IMR_ROM_EXT_CODE_BASE		(L3_MEM_BASE_ADDR + IMR_ROM_EXT_OFFSET)
+#define IMR_ROM_EXT_CODE_SIZE		0xD000
+#define IMR_ROM_EXT_DATABSS_BASE	(IMR_ROM_EXT_CODE_BASE + IMR_ROM_EXT_CODE_SIZE)
+#define IMR_ROM_EXT_DATABSS_SIZE	0x18000
+
 /* position of L3 heap, size of L3 heap - till end of the L3 memory */
 /* !!! FIXME: L3 heap base MUST be automatically calculated. !!! */
 #define IMR_L3_HEAP_BASE		(IMR_BOOT_LDR_STACK_BASE + IMR_BOOT_LDR_STACK_SIZE)

soc/intel/intel_adsp/ace/mmu_ace30.c

@@ -75,6 +75,18 @@ const struct xtensa_mmu_range xtensa_soc_mmu_ranges[] = {
 		.name = "win3",
 	},
 	/* Map IMR */
+	{
+		.start = (uint32_t)IMR_ROM_EXT_CODE_BASE,
+		.end   = (uint32_t)(IMR_ROM_EXT_CODE_BASE + IMR_ROM_EXT_CODE_SIZE),
+		.attrs = XTENSA_MMU_PERM_X,
+		.name = "IMR_rom_ext_code",
+	},
+	{
+		.start = (uint32_t)IMR_ROM_EXT_DATABSS_BASE,
+		.end   = (uint32_t)(IMR_ROM_EXT_DATABSS_BASE + IMR_ROM_EXT_DATABSS_SIZE),
+		.attrs = XTENSA_MMU_PERM_W,
+		.name = "IMR_rom_ext_data_bss",
+	},
 	{
 		.start = (uint32_t)(IMR_BOOT_LDR_MANIFEST_BASE - IMR_BOOT_LDR_MANIFEST_SIZE),
 		.end   = (uint32_t)IMR_BOOT_LDR_MANIFEST_BASE,