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drivers: adc: Add SAM ADC driver
Tested on Atmel SMART SAM E70 Xplained board Origin: Original Jira: ZEP-2507 Signed-off-by: Jonas Pfaff <[email protected]>
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‎arch/arm/soc/atmel_sam/same70/soc_pinmap.h

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#include <soc.h>
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/* Analog to Digital Converter (AFEC) */
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#define PIN_AFE0_ADTRG {PIO_PA8B_AFEC0_ADTRG, PIOA, ID_PIOA, SOC_GPIO_FUNC_B}
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#define PIN_AFE1_ADTRG {PIO_PD9C_AFEC1_ADTRG, PIOD, ID_PIOD, SOC_GPIO_FUNC_C}
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/* Ethernet MAC (GMAC) */
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#define PINS_GMAC_MASK (PIO_PD0A_GMAC_GTXCK | PIO_PD1A_GMAC_GTXEN \

‎drivers/adc/Kconfig

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@@ -80,6 +80,8 @@ source "drivers/adc/Kconfig.mcux"
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source "drivers/adc/Kconfig.qmsi"
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source "drivers/adc/Kconfig.sam_afec"
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source "drivers/adc/Kconfig.ti_adc108s102"
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endif # ADC

‎drivers/adc/Kconfig.sam_afec

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# Kconfig - ADC configuration options
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#
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# Copyright (c) 2017 comsuisse AG
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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menuconfig ADC_SAM_AFEC
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bool "SAM ADC Driver"
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depends on SOC_FAMILY_SAM
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select HAS_DTS_ADC
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default n
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help
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Enable Atmel SAM MCU Family Analog-to-Digital Converter (ADC) driver
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based on AFEC module.

‎drivers/adc/Makefile

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@@ -3,3 +3,4 @@ obj-$(CONFIG_ADC_MCUX_ADC16) += adc_mcux_adc16.o
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obj-$(CONFIG_ADC_TI_ADC108S102) += adc_ti_adc108s102.o
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obj-$(CONFIG_ADC_QMSI) += adc_qmsi.o
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obj-$(CONFIG_ADC_QMSI_SS) += adc_qmsi_ss.o
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obj-$(CONFIG_ADC_SAM_AFEC) += adc_sam_afec.o

‎drivers/adc/adc_sam_afec.c

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/*
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* Copyright (c) 2017 comsuisse AG
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief Atmel SAM MCU family ADC (AFEC) driver.
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*/
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#include <errno.h>
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#include <misc/__assert.h>
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#include <misc/util.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <adc.h>
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#define SYS_LOG_DOMAIN "dev/adc_sam_afec"
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_ADC_LEVEL
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#include <logging/sys_log.h>
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#define ADC_CHANNELS 12
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struct adc_sam_dev_cfg {
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Afec *regs;
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const struct soc_gpio_pin *pin_trigger;
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void (*irq_config)(void);
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u8_t irq_id;
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u8_t periph_id;
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};
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struct channel_samples {
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u16_t *buffer;
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u32_t length;
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};
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struct adc_sam_dev_data {
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struct k_sem sem_meas;
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struct k_sem mutex_thread;
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u16_t active_channels;
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u16_t measured_channels;
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u16_t active_chan_last;
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struct channel_samples samples[ADC_CHANNELS];
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};
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#define CONF_ADC_PRESCALER ((SOC_ATMEL_SAM_MCK_FREQ_HZ / 15000000) - 1)
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#define DEV_NAME(dev) ((dev)->config->name)
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#define DEV_CFG(dev) \
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((const struct adc_sam_dev_cfg *const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct adc_sam_dev_data *const)(dev)->driver_data)
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static void adc_sam_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct adc_sam_dev_cfg *const dev_cfg = DEV_CFG(dev);
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struct adc_sam_dev_data *const dev_data = DEV_DATA(dev);
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Afec *const afec = dev_cfg->regs;
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struct channel_samples *samples = dev_data->samples;
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u32_t isr_status;
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u16_t value;
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isr_status = afec->AFEC_ISR;
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for (int i = 0; i < ADC_CHANNELS; i++) {
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if (isr_status & BIT(i)) {
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/* Channel i has been sampled */
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afec->AFEC_CSELR = AFEC_CSELR_CSEL(i);
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value = (u16_t)(afec->AFEC_CDR);
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if (samples[i].length > 0) {
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/* Save sample */
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*samples[i].buffer = value;
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samples[i].length--;
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samples[i].buffer++;
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dev_data->measured_channels |= BIT(i);
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}
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if (samples[i].length == 0) {
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afec->AFEC_CHDR |= BIT(i);
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afec->AFEC_IDR |= BIT(i);
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dev_data->active_channels &= ~BIT(i);
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}
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}
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}
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if (dev_data->active_chan_last == dev_data->measured_channels) {
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if (!dev_data->active_channels) {
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/* No more conversions needed */
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k_sem_give(&dev_data->sem_meas);
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} else {
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/* Start another conversion with remaining channels */
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dev_data->measured_channels = 0;
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dev_data->active_chan_last = dev_data->active_channels;
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afec->AFEC_CR = AFEC_CR_START;
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}
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}
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}
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static int adc_sam_read(struct device *dev, struct adc_seq_table *seq_tbl)
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{
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const struct adc_sam_dev_cfg *dev_cfg = DEV_CFG(dev);
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struct adc_sam_dev_data *const dev_data = DEV_DATA(dev);
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Afec *const afec = dev_cfg->regs;
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u8_t channel;
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u32_t num_samples;
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k_sem_take(&dev_data->mutex_thread, K_FOREVER);
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dev_data->active_channels = 0;
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/* Enable chosen channels */
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for (int i = 0; i < seq_tbl->num_entries; i++) {
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channel = seq_tbl->entries[i].channel_id;
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if (channel >= ADC_CHANNELS) {
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return -EINVAL;
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}
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/* Check and set number of requested samples */
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num_samples = seq_tbl->entries[i].buffer_length / sizeof(u16_t);
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if (!num_samples) {
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return -EINVAL;
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}
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dev_data->samples[channel].length = num_samples;
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/* Set start of sample buffer */
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dev_data->samples[channel].buffer =
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(u16_t *)seq_tbl->entries[i].buffer;
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/* Enable channel */
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dev_data->active_channels |= BIT(channel);
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}
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/* Enable chosen channels and their interrupts */
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afec->AFEC_CHER = dev_data->active_channels;
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afec->AFEC_IER = dev_data->active_channels;
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/* Start conversions */
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dev_data->measured_channels = 0;
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dev_data->active_chan_last = dev_data->active_channels;
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afec->AFEC_CR = AFEC_CR_START;
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k_sem_take(&dev_data->sem_meas, K_FOREVER);
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k_sem_give(&dev_data->mutex_thread);
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return 0;
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}
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static void adc_sam_configure(struct device *dev)
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{
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const struct adc_sam_dev_cfg *dev_cfg = DEV_CFG(dev);
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Afec *const afec = dev_cfg->regs;
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/* Reset the AFEC */
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afec->AFEC_CR = AFEC_CR_SWRST;
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afec->AFEC_MR = AFEC_MR_TRGEN_DIS
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| AFEC_MR_SLEEP_NORMAL
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| AFEC_MR_FWUP_OFF
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| AFEC_MR_FREERUN_OFF
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| AFEC_MR_PRESCAL(CONF_ADC_PRESCALER)
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| AFEC_MR_STARTUP_SUT96
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| AFEC_MR_ONE
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| AFEC_MR_USEQ_NUM_ORDER;
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/* Set all channels CM voltage to Vrefp/2 (512) */
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for (int i = 0; i < ADC_CHANNELS; i++) {
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afec->AFEC_CSELR = i;
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afec->AFEC_COCR = 512;
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}
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/* Enable PGA and Current Bias */
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afec->AFEC_ACR = AFEC_ACR_PGA0EN
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| AFEC_ACR_PGA1EN
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| AFEC_ACR_IBCTL(1);
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}
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static int adc_sam_initialize(struct device *dev)
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{
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const struct adc_sam_dev_cfg *dev_cfg = DEV_CFG(dev);
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struct adc_sam_dev_data *const dev_data = DEV_DATA(dev);
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/* Initialize semaphores */
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k_sem_init(&dev_data->sem_meas, 0, 1);
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k_sem_init(&dev_data->mutex_thread, 1, 1);
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/* Configure interrupts */
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dev_cfg->irq_config();
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/* Enable module's clock */
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soc_pmc_peripheral_enable(dev_cfg->periph_id);
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/* Configure ADC */
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adc_sam_configure(dev);
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/* Enable module interrupt */
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irq_enable(dev_cfg->irq_id);
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SYS_LOG_INF("Device %s initialized", DEV_NAME(dev));
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return 0;
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}
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static const struct adc_driver_api adc_sam_driver_api = {
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.read = adc_sam_read,
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};
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/* ADC_0 */
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#ifdef CONFIG_ADC_0
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static struct device DEVICE_NAME_GET(adc0_sam);
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static void adc0_irq_config(void)
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{
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IRQ_CONNECT(AFEC0_IRQn, CONFIG_ADC_0_IRQ_PRI, adc_sam_isr,
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DEVICE_GET(adc0_sam), 0);
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}
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static const struct soc_gpio_pin pin_adc0 = PIN_AFE0_ADTRG;
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static const struct adc_sam_dev_cfg adc0_sam_config = {
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.regs = AFEC0,
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.pin_trigger = &pin_adc0,
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.periph_id = ID_AFEC0,
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.irq_config = adc0_irq_config,
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.irq_id = AFEC0_IRQn,
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};
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static struct adc_sam_dev_data adc0_sam_data;
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DEVICE_AND_API_INIT(adc0_sam, CONFIG_ADC_0_NAME, &adc_sam_initialize,
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&adc0_sam_data, &adc0_sam_config, POST_KERNEL,
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CONFIG_ADC_INIT_PRIORITY, &adc_sam_driver_api);
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#endif
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/* ADC_1 */
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#ifdef CONFIG_ADC_1
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static struct device DEVICE_NAME_GET(adc1_sam);
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static void adc1_irq_config(void)
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{
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IRQ_CONNECT(AFEC1_IRQn, CONFIG_ADC_1_IRQ_PRI, adc_sam_isr,
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DEVICE_GET(adc1_sam), 0);
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}
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static const struct soc_gpio_pin pin_adc1 = PIN_AFE1_ADTRG;
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static const struct adc_sam_dev_cfg adc1_sam_config = {
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.regs = AFEC1,
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.pin_trigger = &pin_adc1,
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.periph_id = ID_AFEC1,
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.irq_config = adc1_irq_config,
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.irq_id = AFEC1_IRQn,
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};
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static struct adc_sam_dev_data adc1_sam_data;
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DEVICE_AND_API_INIT(adc1_sam, CONFIG_ADC_1_NAME, &adc_sam_initialize,
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&adc1_sam_data, &adc1_sam_config, POST_KERNEL,
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CONFIG_ADC_INIT_PRIORITY, &adc_sam_driver_api);
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#endif

‎dts/arm/atmel/same70.dtsi

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status = "disabled";
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label = "USART_2";
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};
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adc0: adc@4003C000 {
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compatible = "atmel,sam-afec";
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reg = <0x4003C000 0x100>;
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interrupts = <29 0>;
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status = "disabled";
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label = "ADC_0";
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};
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adc1: adc@40064000 {
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compatible = "atmel,sam-afec";
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reg = <0x40064000 0x100>;
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interrupts = <40 0>;
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status = "disabled";
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label = "ADC_1";
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};
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};
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};
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‎dts/arm/sam_e70_xplained.dts

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};
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};
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&adc0 {
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status = "ok";
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};
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&adc1 {
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status = "ok";
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};
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&usart1 {
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current-speed = <115200>;
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status = "ok";

‎dts/arm/sam_e70_xplained.fixup

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#define CONFIG_USART_SAM_PORT_1_BAUD_RATE ATMEL_SAM_USART_40028000_CURRENT_SPEED
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#define CONFIG_USART_SAM_PORT_2_NAME ATMEL_SAM_USART_4002C000_LABEL
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#define CONFIG_USART_SAM_PORT_2_BAUD_RATE ATMEL_SAM_USART_4002C000_CURRENT_SPEED
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#define CONFIG_ADC_0_BASE_ADDRESS ATMEL_SAM_AFEC_4003C000_BASE_ADDRESS_0
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#define CONFIG_ADC_0_IRQ ATMEL_SAM_AFEC_4003C000_IRQ_0
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#define CONFIG_ADC_0_IRQ_PRI ATMEL_SAM_AFEC_4003C000_IRQ_0_PRIORITY
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#define CONFIG_ADC_0_NAME ATMEL_SAM_AFEC_4003C000_LABEL
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#define CONFIG_ADC_1_BASE_ADDRESS ATMEL_SAM_AFEC_40064000_BASE_ADDRESS_0
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#define CONFIG_ADC_1_IRQ ATMEL_SAM_AFEC_40064000_IRQ_0
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#define CONFIG_ADC_1_IRQ_PRI ATMEL_SAM_AFEC_40064000_IRQ_0_PRIORITY
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#define CONFIG_ADC_1_NAME ATMEL_SAM_AFEC_40064000_LABEL

‎dts/arm/yaml/atmel,sam-afec.yaml

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---
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title: Atmel SAM Family AFEC
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id: atmel,sam-afec
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version: 0.1
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description: >
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This binding gives a base representation of the Atmel SAM AFEC
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inherits:
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- !include adc.yaml
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properties:
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- compatible:
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type: string
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category: required
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description: compatible strings
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constraint: "atmel,sam-afec"
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- reg:
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type: array
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description: mmio register space
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generation: define
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category: required
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- interrupts:
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type: array
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category: required
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description: required interrupts
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generation: define
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...

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