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add tickless idle and kernel support to RISCV32 pulpino #3651

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zephyrbot opened this issue May 30, 2017 · 2 comments
Closed

add tickless idle and kernel support to RISCV32 pulpino #3651

zephyrbot opened this issue May 30, 2017 · 2 comments
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area: RISCV RISCV Architecture (32-bit & 64-bit) Enhancement Changes/Updates/Additions to existing features priority: low Low impact/importance bug

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@zephyrbot
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zephyrbot commented May 30, 2017

Reported by Andrew Boie:

The RISCV32 pulpino SOC supports low power idle, but there is no tickless idle support in the timer driver, or support for tickless kernel. Implement this for the pulpino timer driver such that we get the lowest power consumption on this platform.

(Imported from Jira ZEP-2215)

@zephyrbot zephyrbot added priority: low Low impact/importance bug area: RISCV RISCV Architecture (32-bit & 64-bit) Enhancement Changes/Updates/Additions to existing features labels Sep 23, 2017
@andyross
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The Pulpino driver is one of the few that didn't get rewritten during the timer rework, but looking at it it's a pretty standard cycle counter with comparator like almost all the others (e.g. HPET, nRF, Xtensa, RISC-V machine timer, but not APIC or ARM SysTick as those are werider). Doing a driver would mostly be cut and paste of about 100 lines, I just don't have hardware to test with.

@nategraff-sifive
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Closing because support for Pulpino was removed from Zephyr in #12876

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Labels
area: RISCV RISCV Architecture (32-bit & 64-bit) Enhancement Changes/Updates/Additions to existing features priority: low Low impact/importance bug
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