diff --git a/boards/nxp/mimxrt1180_evk/doc/index.rst b/boards/nxp/mimxrt1180_evk/doc/index.rst
index d9dcdaed7213..c055acae6d19 100644
--- a/boards/nxp/mimxrt1180_evk/doc/index.rst
+++ b/boards/nxp/mimxrt1180_evk/doc/index.rst
@@ -120,6 +120,10 @@ configuration supports the following hardware features:
 +-----------+------------+-------------------------------------+
 | I3C       | on-chip    | i3c                                 |
 +-----------+------------+-------------------------------------+
+| DMA       | on-chip    | dma                                 |
++-----------+------------+-------------------------------------+
+| SPI       | on-chip    | spi                                 |
++-----------+------------+-------------------------------------+
 
 The default configuration can be found in the defconfig file:
 :zephyr_file:`boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig`
@@ -143,6 +147,14 @@ The MIMXRT1180 SoC has six pairs of pinmux/gpio controllers.
 +---------------+-----------------+---------------------------+
 | GPIO_AON_09   | LPUART1_RX      | UART Console              |
 +---------------+-----------------+---------------------------+
+| GPIO_SD_B1_00 | SPI1_CS0        | spi                       |
++---------------+---------------------------------------------+
+| GPIO_SD_B1_01 | SPI1_CLK        | spi                       |
++---------------+---------------------------------------------+
+| GPIO_SD_B1_02 | SPI1_SDO        | spi                       |
++---------------+---------------------------------------------+
+| GPIO_SD_B1_03 | SPI1_SDI        | spi                       |
++---------------+---------------------------------------------+
 
 System Clock
 ============
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi
index bfaa7852dce4..0da0feb14985 100644
--- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi
@@ -73,6 +73,29 @@
 		};
 	};
 
+	pinmux_lpuart3: pinmux_lpuart3 {
+		group0 {
+			pinmux = <&iomuxc_gpio_ad_14_lpuart3_rxd>,
+				<&iomuxc_gpio_ad_13_lpuart3_txd>;
+			drive-strength = "high";
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_lpuart3_sleep: pinmux_lpuart3_sleep {
+		group0 {
+			pinmux = <&iomuxc_gpio_ad_14_gpio4_io14>;
+			drive-strength = "high";
+			bias-pull-up;
+			slew-rate = "fast";
+		};
+		group1 {
+			pinmux = <&iomuxc_gpio_ad_13_lpuart3_txd>;
+			drive-strength = "high";
+			slew-rate = "fast";
+		};
+	};
+
 	/* Connected to FXLS8974 */
 	pinmux_lpi2c2: pinmux_lpi2c2 {
 		group0 {
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi
index 5af9c4555249..fcac00046657 100644
--- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi
@@ -47,6 +47,12 @@
 	pinctrl-names = "default", "sleep";
 };
 
+&lpuart3 {
+	pinctrl-0 = <&pinmux_lpuart3>;
+	pinctrl-1 = <&pinmux_lpuart3_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
 &user_button {
 	status = "okay";
 };
@@ -152,3 +158,10 @@
 
 p3t1755dp_ard_i3c_interface: &i3c2 {};
 p3t1755dp_ard_i2c_interface: &lpi2c2 {};
+
+&lpspi3 {
+	dmas = <&edma4 1 13>, <&edma4 2 12>;
+	dma-names = "rx", "tx";
+	pinctrl-0 = <&pinmux_lpspi3>;
+	pinctrl-names = "default";
+};
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts
index 97a3752628bd..7624b0704027 100644
--- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts
@@ -79,3 +79,15 @@
 &i3c2 {
 	status = "okay";
 };
+
+&lpspi3 {
+	status = "okay";
+};
+
+&edma3 {
+	status = "okay";
+};
+
+&edma4 {
+	status = "okay";
+};
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml
index bddd1e8a0a3c..ac23deb65fd0 100644
--- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml
@@ -25,4 +25,6 @@ supported:
   - pwm
   - uart
   - i3c
+  - dma
+  - spi
 vendor: nxp
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts
index 7e003fe903e2..1ecb2a35ac96 100644
--- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts
@@ -51,3 +51,15 @@
 &i3c2 {
 	status = "okay";
 };
+
+&lpspi3 {
+	status = "okay";
+};
+
+&edma3 {
+	status = "okay";
+};
+
+&edma4 {
+	status = "okay";
+};
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml
index 60b954ec5335..892934977cbb 100644
--- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml
@@ -24,4 +24,6 @@ supported:
   - pwm
   - uart
   - i3c
+  - dma
+  - spi
 vendor: nxp
diff --git a/drivers/clock_control/clock_control_mcux_ccm_rev2.c b/drivers/clock_control/clock_control_mcux_ccm_rev2.c
index 3151429fe030..504faa86bad4 100644
--- a/drivers/clock_control/clock_control_mcux_ccm_rev2.c
+++ b/drivers/clock_control/clock_control_mcux_ccm_rev2.c
@@ -82,10 +82,16 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
 #endif
 
 #ifdef CONFIG_SPI_MCUX_LPSPI
+#if defined(CONFIG_SOC_SERIES_IMXRT118X)
+	case IMX_CCM_LPSPI0102_CLK:
+		clock_root = kCLOCK_Root_Lpspi0102 + instance;
+		break;
+#else
 	case IMX_CCM_LPSPI1_CLK:
 		clock_root = kCLOCK_Root_Lpspi1 + instance;
 		break;
-#endif
+#endif /* CONFIG_SOC_SERIES_IMXRT118X */
+#endif /* CONFIG_SPI_MCUX_LPSPI */
 
 #ifdef CONFIG_UART_MCUX_LPUART
 #if defined(CONFIG_SOC_SERIES_IMXRT118X)
@@ -117,6 +123,15 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
 		break;
 #endif
 
+#ifdef CONFIG_DMA_MCUX_EDMA_V4
+	case IMX_CCM_EDMA3_CLK:
+		clock_root = kCLOCK_Root_M33;
+		break;
+	case IMX_CCM_EDMA4_CLK:
+		clock_root = kCLOCK_Root_Wakeup_Axi;
+		break;
+#endif
+
 #ifdef CONFIG_PWM_MCUX
 #if defined(CONFIG_SOC_SERIES_IMXRT118X)
 	case IMX_CCM_PWM_CLK:
diff --git a/drivers/dma/dma_mcux_edma.c b/drivers/dma/dma_mcux_edma.c
index 5575cb2a73f9..ab818cd18ec5 100644
--- a/drivers/dma/dma_mcux_edma.c
+++ b/drivers/dma/dma_mcux_edma.c
@@ -277,6 +277,28 @@ static void dma_mcux_edma_error_irq_handler(const struct device *dev)
 }
 #endif
 
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(channels_shared_irq_mask)
+static void dma_mcux_edma_multi_channels_irq_handler(const struct device *dev, uint32_t idx,
+			uint32_t *buf, uint32_t mask_width)
+{
+	uint32_t *num = &buf[mask_width * idx];
+	uint32_t count = 0;
+
+	for (int _i = 0; _i < mask_width; _i++) {
+		uint32_t value = (*num);
+
+		while (value > 0) {
+			if ((value & 0x1) == 1) {
+				dma_mcux_edma_irq_handler(dev, count);
+			}
+			value = value >> 1;
+			count++;
+		}
+		num++;
+	}
+}
+#endif
+
 /* Configure a channel */
 static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel,
 				   struct dma_config *config)
@@ -861,10 +883,22 @@ static int dma_mcux_edma_init(const struct device *dev)
 			    irq_enable(DT_INST_IRQ_BY_IDX(n, idx, irq));	\
 	}
 
+#define EDMA_CHANNELS_MASK(n) static uint32_t edma_channel_mask_##n[] =  \
+				DT_PROP(DT_DRV_INST(n), channels_shared_irq_mask);
+
+#define GET_EDMA_CHANNEL_SHARED_IRQ_MASK_WIDTH(n) \
+			(DT_INST_PROP(n, dma_channels) / 32)
+
+#define EDMA_CHANNELS_SHARED_REGISTER_IN_IRQ(dev, idx, n) \
+		dma_mcux_edma_multi_channels_irq_handler(dev, idx, edma_channel_mask_##n, \
+			GET_EDMA_CHANNEL_SHARED_IRQ_MASK_WIDTH(n));
+
 #define DMA_MCUX_EDMA_IRQ_DEFINE(idx, n)					\
 	static void dma_mcux_edma_##n##_irq_##idx(const struct device *dev)	\
 	{									\
-		dma_mcux_edma_irq_handler(dev, idx);				\
+		COND_CODE_1(DT_INST_NODE_HAS_PROP(n, channels_shared_irq_mask), \
+			(EDMA_CHANNELS_SHARED_REGISTER_IN_IRQ(dev, idx, n)),	\
+			(dma_mcux_edma_irq_handler(dev, idx);))	\
 										\
 		IF_ENABLED(UTIL_BOOL(DT_INST_PROP(n, irq_shared_offset)),	\
 			  (dma_mcux_edma_irq_handler(dev,			\
@@ -877,6 +911,8 @@ static int dma_mcux_edma_init(const struct device *dev)
 	IRQ_CONFIG(n, idx, dma_mcux_edma_##n##_irq_##idx)
 
 #define DMA_MCUX_EDMA_CONFIG_FUNC(n)						\
+	IF_ENABLED(DT_INST_NODE_HAS_PROP(n, channels_shared_irq_mask), \
+				(EDMA_CHANNELS_MASK(n))) \
 	LISTIFY(NUM_IRQS_WITHOUT_ERROR_IRQ(n), DMA_MCUX_EDMA_IRQ_DEFINE, (), n) \
 	static void dma_imx_config_func_##n(const struct device *dev)		\
 	{									\
diff --git a/dts/arm/nxp/nxp_rt118x.dtsi b/dts/arm/nxp/nxp_rt118x.dtsi
index 9b95e392aa9f..4ec1fd4495be 100644
--- a/dts/arm/nxp/nxp_rt118x.dtsi
+++ b/dts/arm/nxp/nxp_rt118x.dtsi
@@ -22,6 +22,7 @@
 
 			#address-cells = <1>;
 			#size-cells = <1>;
+			d-cache-line-size = <32>;
 
 			mpu: mpu@e000ed90 {
 				compatible = "arm,armv8m-mpu";
@@ -35,6 +36,12 @@
 
 			#address-cells = <1>;
 			#size-cells = <1>;
+			d-cache-line-size = <32>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv7m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
 		};
 	};
 };
@@ -74,6 +81,8 @@
 		reg = <0x4380000 0x4000>;
 		interrupts = <19 0>;
 		clocks = <&ccm IMX_CCM_LPUART0102_CLK 0x7c 24>;
+		dmas = <&edma3 0 16>, <&edma3 1 17>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -82,6 +91,8 @@
 		reg = <0x4390000 0x4000>;
 		interrupts = <20 0>;
 		clocks = <&ccm IMX_CCM_LPUART0102_CLK 0x68 28>;
+		dmas = <&edma3 2 18>, <&edma3 3 19>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -90,6 +101,8 @@
 		reg = <0x2570000 0x4000>;
 		interrupts = <68 0>;
 		clocks = <&ccm IMX_CCM_LPUART0304_CLK 0x68 12>;
+		dmas = <&edma4 0 17>, <&edma4 1 18>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -98,6 +111,8 @@
 		reg = <0x2580000 0x4000>;
 		interrupts = <69 0>;
 		clocks = <&ccm IMX_CCM_LPUART0304_CLK 0x6c 24>;
+		dmas = <&edma4 2 19>, <&edma4 3 20>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -106,6 +121,8 @@
 		reg = <0x2590000 0x4000>;
 		interrupts = <70 0>;
 		clocks = <&ccm IMX_CCM_LPUART0506_CLK 0x74 2>;
+		dmas = <&edma4 4 21>, <&edma4 5 22>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -114,6 +131,8 @@
 		reg = <0x25A0000 0x4000>;
 		interrupts = <71 0>;
 		clocks = <&ccm IMX_CCM_LPUART0506_CLK 0x74 6>;
+		dmas = <&edma4 6 23>, <&edma4 7 24>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -122,6 +141,8 @@
 		reg = <0x4570000 0x4000>;
 		interrupts = <196 0>;
 		clocks = <&ccm IMX_CCM_LPUART0708_CLK 0x7c 26>;
+		dmas = <&edma3 4 29>, <&edma3 5 30>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -130,6 +151,8 @@
 		reg = <0x2DA0000 0x4000>;
 		interrupts = <197 0>;
 		clocks = <&ccm IMX_CCM_LPUART0708_CLK 0x80 14>;
+		dmas = <&edma4 8 178>, <&edma4 9 179>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -138,6 +161,8 @@
 		reg = <0x2D70000 0x4000>;
 		interrupts = <156 0>;
 		clocks = <&ccm IMX_CCM_LPUART0910_CLK 0x80 14>;
+		dmas = <&edma4 10 172>, <&edma4 11 173>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -146,6 +171,8 @@
 		reg = <0x2D80000 0x4000>;
 		interrupts = <157 0>;
 		clocks = <&ccm IMX_CCM_LPUART0910_CLK 0x80 14>;
+		dmas = <&edma4 12 174>, <&edma4 13 175>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -154,6 +181,8 @@
 		reg = <0x2D90000 0x4000>;
 		interrupts = <158 0>;
 		clocks = <&ccm IMX_CCM_LPUART1112_CLK 0x80 14>;
+		dmas = <&edma4 14 176>, <&edma4 15 177>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -162,6 +191,8 @@
 		reg = <0x4580000 0x4000>;
 		interrupts = <159 0>;
 		clocks = <&ccm IMX_CCM_LPUART1112_CLK 0x80 14>;
+		dmas = <&edma3 6 31>, <&edma3 7 32>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -934,6 +965,111 @@
 		#address-cells = <3>;
 		#size-cells = <0>;
 	};
+
+	edma3: dma-controller@4000000 {
+		#dma-cells = <2>;
+		compatible = "nxp,mcux-edma";
+		nxp,version = <4>;
+		reg = <0x4000000 0x210000>;
+		dma-channels = <32>;
+		dma-requests = <39>;
+		no-error-irq;
+		interrupts = <95 0>, <96 0>, <97 0>,
+			<98 0>, <99 0>, <100 0>, <101 0>,
+			<102 0>, <103 0>, <104 0>, <105 0>,
+			<106 0>, <107 0>, <108 0>, <109 0>,
+			<110 0>, <111 0>, <112 0>, <113 0>,
+			<114 0>, <115 0>, <116 0>, <117 0>,
+			<118 0>, <119 0>, <120 0>, <121 0>,
+			<122 0>, <123 0>, <124 0>, <125 0>,
+			<126 0>, <94 0>;
+		status = "disabled";
+	};
+
+	edma4: dma-controller@2000000 {
+		#dma-cells = <2>;
+		compatible = "nxp,mcux-edma";
+		nxp,version = <4>;
+		dma-channels = <64>;
+		dma-requests = <222>;
+		reg = <0x2000000 0x4000>;
+		no-error-irq;
+		interrupts = <128 0>, <129 0>, <130 0>,
+			<131 0>, <132 0>, <133 0>, <134 0>,
+			<135 0>, <136 0>, <137 0>, <138 0>,
+			<139 0>, <140 0>, <141 0>, <142 0>,
+			<143 0>, <127 0>;
+		channels-shared-irq-mask = <0x00000003 0x00000003
+			 0x0000000C 0x0000000C 0x00000030 0x00000030
+			 0x000000C0 0x000000C0 0x00000300 0x00000300
+			 0x00000C00 0x00000C00 0x00003000 0x00003000
+			 0x0000C000 0x0000C000 0x00030000 0x00030000
+			 0x000C0000 0x000C0000 0x00300000 0x00300000
+			 0x00C00000 0x00C00000 0x03000000 0x03000000
+			 0x0C000000 0x0C000000 0x30000000 0x30000000
+			 0xC0000000 0xC0000000>;
+		status = "disabled";
+	};
+
+	lpspi1: spi@4360000 {
+		compatible = "nxp,lpspi";
+		reg = <0x4360000 0x4000>;
+		interrupts = <16 3>;
+		status = "disabled";
+		clocks = <&ccm IMX_CCM_LPSPI0102_CLK 0x6c 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	lpspi2: spi@4370000 {
+		compatible = "nxp,lpspi";
+		reg = <0x4370000 0x4000>;
+		interrupts = <17 3>;
+		status = "disabled";
+		clocks = <&ccm IMX_CCM_LPSPI0102_CLK 0x6c 2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	lpspi3: spi@2550000 {
+		compatible = "nxp,lpspi";
+		reg = <0x2550000 0x4000>;
+		interrupts = <65 3>;
+		status = "disabled";
+		clocks = <&ccm IMX_CCM_LPSPI0304_CLK 0x6c 4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	lpspi4: spi@2560000 {
+		compatible = "nxp,lpspi";
+		reg = <0x2560000 0x4000>;
+		interrupts = <66 3>;
+		status = "disabled";
+		clocks = <&ccm IMX_CCM_LPSPI0304_CLK 0x6c 6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	lpspi5: spi@2d50000 {
+		compatible = "nxp,lpspi";
+		reg = <0x2d50000 0x4000>;
+		interrupts = <194 3>;
+		status = "disabled";
+		clocks = <&ccm IMX_CCM_LPSPI0506_CLK 0x6c 6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	lpspi6: spi@2d60000 {
+		compatible = "nxp,lpspi";
+		reg = <0x2d60000 0x4000>;
+		interrupts = <195 3>;
+		status = "disabled";
+		clocks = <&ccm IMX_CCM_LPSPI0506_CLK 0x6c 6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
 };
 
 &flexspi {
diff --git a/dts/bindings/dma/nxp,mcux-edma.yaml b/dts/bindings/dma/nxp,mcux-edma.yaml
index 57e79378c045..17c8b3c3d22b 100644
--- a/dts/bindings/dma/nxp,mcux-edma.yaml
+++ b/dts/bindings/dma/nxp,mcux-edma.yaml
@@ -1,4 +1,4 @@
-# Copyright (c) 2020, NXP
+# Copyright (c) 2020,2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 description: NXP MCUX EDMA controller
@@ -65,6 +65,19 @@ properties:
     description: |
       eDMA IP revision number.
 
+  channels-shared-irq-mask:
+    type: array
+    description: |
+      Describes channel enabled mask value on every IRQ.
+      The channel number is mapped to the bit value of array element value.
+      If the interrupt is shared on one channel number, the correspongding
+      bit is set to 1.
+      Please note each element of the array must be 32-bit. If there are more
+      than 32 channels, add one or more 32-bit elements in array(elements
+      should be contiguous). The software will determine the mask value of
+      several elements corresponding to the same interrupt according to the
+      number of channels.
+
   "#dma-cells":
     type: int
     required: true
diff --git a/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h b/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h
index 89a43c734e2a..e5035584cbec 100644
--- a/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h
+++ b/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h
@@ -58,10 +58,13 @@
 
 /* LPSPI */
 #define IMX_CCM_LPSPI_CLK              0x500UL
+#define IMX_CCM_LPSPI0102_CLK          0x500UL
 #define IMX_CCM_LPSPI1_CLK             0x500UL
 #define IMX_CCM_LPSPI2_CLK             0x501UL
+#define IMX_CCM_LPSPI0304_CLK          0x501UL
 #define IMX_CCM_LPSPI3_CLK             0x502UL
 #define IMX_CCM_LPSPI4_CLK             0x503UL
+#define IMX_CCM_LPSPI0506_CLK          0x502UL
 #define IMX_CCM_LPSPI5_CLK             0x504UL
 #define IMX_CCM_LPSPI6_CLK             0x505UL
 #define IMX_CCM_LPSPI7_CLK             0x506UL
@@ -74,6 +77,8 @@
 /* DMA  */
 #define IMX_CCM_EDMA_CLK               0x700UL
 #define IMX_CCM_EDMA_LPSR_CLK          0x701UL
+#define IMX_CCM_EDMA3_CLK              0x700UL
+#define IMX_CCM_EDMA4_CLK              0x701UL
 
 /* PWM */
 #define IMX_CCM_PWM_CLK                0x800UL
diff --git a/soc/nxp/imxrt/imxrt118x/soc.c b/soc/nxp/imxrt/imxrt118x/soc.c
index e1499f03924c..cdcc8306e41e 100644
--- a/soc/nxp/imxrt/imxrt118x/soc.c
+++ b/soc/nxp/imxrt/imxrt118x/soc.c
@@ -42,6 +42,7 @@
 #define ELE_TRDC_WAKEUP_ID 0x78
 #define ELE_CORE_CM33_ID   0x1
 #define ELE_CORE_CM7_ID    0x2
+#define EDMA_DID           0x7U
 
 #ifdef CONFIG_INIT_ARM_PLL
 static const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
@@ -260,15 +261,34 @@ static ALWAYS_INLINE void clock_init(void)
 	CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0506, &rootCfg);
 #endif
 
-#if defined(CONFIG_SPI_MCUX_LPSPI) && \
-	(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi1)) \
-	|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi2)))
+#if defined(CONFIG_SPI_MCUX_LPSPI)
+
+#if	(DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi1), okay) \
+	|| DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi2), okay))
 	/* Configure LPSPI0102 using SYS_PLL3_PFD1_CLK */
 	rootCfg.mux = kCLOCK_LPSPI0102_ClockRoot_MuxSysPll3Pfd1;
 	rootCfg.div = 2;
 	CLOCK_SetRootClock(kCLOCK_Root_Lpspi0102, &rootCfg);
 #endif
 
+#if	(DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi3), okay) \
+	|| DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi4), okay))
+	/* Configure LPSPI0304 using SYS_PLL3_PFD1_CLK */
+	rootCfg.mux = kCLOCK_LPSPI0304_ClockRoot_MuxSysPll3Pfd1;
+	rootCfg.div = 2;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpspi0304, &rootCfg);
+#endif
+
+#if (DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi5), okay) \
+	|| DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi6), okay))
+	/* Configure LPSPI0506 using SYS_PLL3_PFD1_CLK */
+	rootCfg.mux = kCLOCK_LPSPI0506_ClockRoot_MuxSysPll3Pfd1;
+	rootCfg.div = 2;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpspi0506, &rootCfg);
+#endif
+
+#endif /* CONFIG_SPI_MCUX_LPSPI */
+
 #if defined(CONFIG_COUNTER_MCUX_GPT)
 
 #if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpt1)))
@@ -477,13 +497,6 @@ static ALWAYS_INLINE void clock_init(void)
 	GPC_CM_SetNextCpuMode(1, kGPC_RunMode);
 	GPC_CM_EnableCpuSleepHold(0, false);
 	GPC_CM_EnableCpuSleepHold(1, false);
-
-#if !defined(CONFIG_PM)
-	/* Enable the AHB clock while the CM7 is sleeping to allow debug access
-	 * to TCM
-	 */
-	BLK_CTRL_S_AONMIX->M7_CFG |= BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE_MASK;
-#endif
 }
 
 /**
@@ -522,6 +535,26 @@ static ALWAYS_INLINE void trdc_enable_all_access(void)
 #endif
 	} while (ELE_IS_FAILED(sts));
 
+
+	/* Set the master domain access configuration for eDMA3/eDMA4 */
+	trdc_non_processor_domain_assignment_t edmaAssignment;
+
+	/* By default, EDMA access is done in privilege and security mode,
+	 * However, the NSE bit reset value in TRDC is 0, so that TRDC does
+	 * not allow nonsecurity access to other memory by default.
+	 * So by DAC module, EDMA access mode is changed to security/privilege
+	 * mode by the DAC module
+	 */
+	(void)memset(&edmaAssignment, 0, sizeof(edmaAssignment));
+	edmaAssignment.domainId       = EDMA_DID;
+	edmaAssignment.privilegeAttr  = kTRDC_MasterPrivilege;
+	edmaAssignment.secureAttr     = kTRDC_ForceSecure;
+	edmaAssignment.bypassDomainId = true;
+	edmaAssignment.lock           = false;
+
+	TRDC_SetNonProcessorDomainAssignment(TRDC1, kTRDC1_MasterDMA3, &edmaAssignment);
+	TRDC_SetNonProcessorDomainAssignment(TRDC2, kTRDC2_MasterDMA4, &edmaAssignment);
+
 	/* Enable all access modes for MBC and MRC of TRDCA and TRDCW */
 	trdc_hardware_config_t hwConfig;
 	trdc_memory_access_control_config_t memAccessConfig;
@@ -542,12 +575,18 @@ static ALWAYS_INLINE void trdc_enable_all_access(void)
 
 	TRDC_GetHardwareConfig(TRDC1, &hwConfig);
 	for (i = 0U; i < hwConfig.mrcNumber; i++) {
+		/* Set TRDC1(A) secure access for eDMA domain, MRC i, all region for i memory */
+		TRDC_MrcDomainNseClear(TRDC1, i, 1UL << EDMA_DID);
+
 		for (j = 0U; j < 8; j++) {
 			TRDC_MrcSetMemoryAccessConfig(TRDC1, &memAccessConfig, i, j);
 		}
 	}
 
 	for (i = 0U; i < hwConfig.mbcNumber; i++) {
+		/* Set TRDC1(A) secure access for eDMA domain, MBC i, all memory blocks */
+		TRDC_MbcNseClearAll(TRDC1, i, 1UL << EDMA_DID, 0xF);
+
 		for (j = 0U; j < 8; j++) {
 			TRDC_MbcSetMemoryAccessConfig(TRDC1, &memAccessConfig, i, j);
 		}
@@ -555,12 +594,18 @@ static ALWAYS_INLINE void trdc_enable_all_access(void)
 
 	TRDC_GetHardwareConfig(TRDC2, &hwConfig);
 	for (i = 0U; i < hwConfig.mrcNumber; i++) {
+		/* Set TRDC2(W) secure access for eDMA domain, MRC i, all region for i memory */
+		TRDC_MrcDomainNseClear(TRDC2, i, 1UL << EDMA_DID);
+
 		for (j = 0U; j < 8; j++) {
 			TRDC_MrcSetMemoryAccessConfig(TRDC2, &memAccessConfig, i, j);
 		}
 	}
 
 	for (i = 0U; i < hwConfig.mbcNumber; i++) {
+		/* Set TRDC2(W) secure access for eDMA domain, MBC i, all memory blocks */
+		TRDC_MbcNseClearAll(TRDC2, i, 1UL << EDMA_DID, 0xF);
+
 		for (j = 0U; j < 8; j++) {
 			TRDC_MbcSetMemoryAccessConfig(TRDC2, &memAccessConfig, i, j);
 		}
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm33.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
new file mode 100644
index 000000000000..9b2a9986e38e
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
@@ -0,0 +1,8 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_SPI_MCUX_LPSPI_DMA=y
+CONFIG_SPI_ASYNC=n
+CONFIG_DMA_MCUX_USE_DTCM_FOR_DMA_DESCRIPTORS=n
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
new file mode 100644
index 000000000000..c1de4474f608
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* To test this sample, connect J44.8 <-> J44.10 */
+
+/ {
+	chosen {
+		zephyr,sram = &dtcm;
+	};
+};
+
+&lpspi3 {
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm7.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
new file mode 100644
index 000000000000..9b2a9986e38e
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
@@ -0,0 +1,8 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_SPI_MCUX_LPSPI_DMA=y
+CONFIG_SPI_ASYNC=n
+CONFIG_DMA_MCUX_USE_DTCM_FOR_DMA_DESCRIPTORS=n
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
new file mode 100644
index 000000000000..6a44a9ae299d
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* To test this sample, connect J44.8 <-> J44.10 */
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	chosen {
+		zephyr,sram = &ocram1;
+	};
+};
+
+&ocram1 {
+	zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
+};
+
+&lpspi3 {
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt1180_evk_mimxrt1189_cm7.conf b/tests/drivers/uart/uart_async_api/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
new file mode 100644
index 000000000000..cf4dcd316a92
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
@@ -0,0 +1,6 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_DMA_MCUX_USE_DTCM_FOR_DMA_DESCRIPTORS=n