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alexrpalexrp
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Merge pull request #23447 from alexrp/cpuid-updates
2 parents bfbf4ba + e87387e commit e922052

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5 files changed

+314
-86
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5 files changed

+314
-86
lines changed

Diff for: ‎lib/std/c/darwin.zig

+2
Original file line numberDiff line numberDiff line change
@@ -1165,6 +1165,8 @@ pub const CPUFAMILY = enum(u32) {
11651165
ARM_PALMA = 0x72015832,
11661166
ARM_DONAN = 0x6f5129ac,
11671167
ARM_BRAVA = 0x17d5b93a,
1168+
ARM_TAHITI = 0x75d4acb9,
1169+
ARM_TUPAI = 0x204526d0,
11681170
_,
11691171
};
11701172

Diff for: ‎lib/std/os/windows.zig

+3
Original file line numberDiff line numberDiff line change
@@ -5315,6 +5315,9 @@ pub const PF = enum(DWORD) {
53155315

53165316
/// This ARM processor implements the ARM v8.3 JavaScript conversion (JSCVT) instructions.
53175317
ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE = 44,
5318+
5319+
/// This Arm processor implements the Arm v8.3 LRCPC instructions (for example, LDAPR). Note that certain Arm v8.2 CPUs may optionally support the LRCPC instructions.
5320+
ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE,
53185321
};
53195322

53205323
pub const MAX_WOW64_SHARED_ENTRIES = 16;

Diff for: ‎lib/std/zig/system/arm.zig

+56-31
Original file line numberDiff line numberDiff line change
@@ -22,49 +22,73 @@ pub const cpu_models = struct {
2222

2323
// implementer = 0x41
2424
const ARM = [_]E{
25-
E{ .part = 0x926, .m32 = &A32.arm926ej_s, .m64 = null },
26-
E{ .part = 0xb02, .m32 = &A32.mpcore, .m64 = null },
27-
E{ .part = 0xb36, .m32 = &A32.arm1136j_s, .m64 = null },
28-
E{ .part = 0xb56, .m32 = &A32.arm1156t2_s, .m64 = null },
29-
E{ .part = 0xb76, .m32 = &A32.arm1176jz_s, .m64 = null },
30-
E{ .part = 0xc05, .m32 = &A32.cortex_a5, .m64 = null },
31-
E{ .part = 0xc07, .m32 = &A32.cortex_a7, .m64 = null },
32-
E{ .part = 0xc08, .m32 = &A32.cortex_a8, .m64 = null },
33-
E{ .part = 0xc09, .m32 = &A32.cortex_a9, .m64 = null },
34-
E{ .part = 0xc0d, .m32 = &A32.cortex_a17, .m64 = null },
35-
E{ .part = 0xc0f, .m32 = &A32.cortex_a15, .m64 = null },
36-
E{ .part = 0xc0e, .m32 = &A32.cortex_a17, .m64 = null },
37-
E{ .part = 0xc14, .m32 = &A32.cortex_r4, .m64 = null },
38-
E{ .part = 0xc15, .m32 = &A32.cortex_r5, .m64 = null },
39-
E{ .part = 0xc17, .m32 = &A32.cortex_r7, .m64 = null },
40-
E{ .part = 0xc18, .m32 = &A32.cortex_r8, .m64 = null },
41-
E{ .part = 0xc20, .m32 = &A32.cortex_m0, .m64 = null },
42-
E{ .part = 0xc21, .m32 = &A32.cortex_m1, .m64 = null },
43-
E{ .part = 0xc23, .m32 = &A32.cortex_m3, .m64 = null },
44-
E{ .part = 0xc24, .m32 = &A32.cortex_m4, .m64 = null },
45-
E{ .part = 0xc27, .m32 = &A32.cortex_m7, .m64 = null },
46-
E{ .part = 0xc60, .m32 = &A32.cortex_m0plus, .m64 = null },
47-
E{ .part = 0xd01, .m32 = &A32.cortex_a32, .m64 = null },
25+
E{ .part = 0x926, .m32 = &A32.arm926ej_s },
26+
E{ .part = 0xb02, .m32 = &A32.mpcore },
27+
E{ .part = 0xb36, .m32 = &A32.arm1136j_s },
28+
E{ .part = 0xb56, .m32 = &A32.arm1156t2_s },
29+
E{ .part = 0xb76, .m32 = &A32.arm1176jz_s },
30+
E{ .part = 0xc05, .m32 = &A32.cortex_a5 },
31+
E{ .part = 0xc07, .m32 = &A32.cortex_a7 },
32+
E{ .part = 0xc08, .m32 = &A32.cortex_a8 },
33+
E{ .part = 0xc09, .m32 = &A32.cortex_a9 },
34+
E{ .part = 0xc0d, .m32 = &A32.cortex_a17 },
35+
E{ .part = 0xc0e, .m32 = &A32.cortex_a17 },
36+
E{ .part = 0xc0f, .m32 = &A32.cortex_a15 },
37+
E{ .part = 0xc14, .m32 = &A32.cortex_r4 },
38+
E{ .part = 0xc15, .m32 = &A32.cortex_r5 },
39+
E{ .part = 0xc17, .m32 = &A32.cortex_r7 },
40+
E{ .part = 0xc18, .m32 = &A32.cortex_r8 },
41+
E{ .part = 0xc20, .m32 = &A32.cortex_m0 },
42+
E{ .part = 0xc21, .m32 = &A32.cortex_m1 },
43+
E{ .part = 0xc23, .m32 = &A32.cortex_m3 },
44+
E{ .part = 0xc24, .m32 = &A32.cortex_m4 },
45+
E{ .part = 0xc27, .m32 = &A32.cortex_m7 },
46+
E{ .part = 0xc60, .m32 = &A32.cortex_m0plus },
47+
E{ .part = 0xd01, .m32 = &A32.cortex_a32 },
48+
E{ .part = 0xd02, .m64 = &A64.cortex_a34 },
4849
E{ .part = 0xd03, .m32 = &A32.cortex_a53, .m64 = &A64.cortex_a53 },
4950
E{ .part = 0xd04, .m32 = &A32.cortex_a35, .m64 = &A64.cortex_a35 },
5051
E{ .part = 0xd05, .m32 = &A32.cortex_a55, .m64 = &A64.cortex_a55 },
52+
E{ .part = 0xd06, .m64 = &A64.cortex_a65 },
5153
E{ .part = 0xd07, .m32 = &A32.cortex_a57, .m64 = &A64.cortex_a57 },
5254
E{ .part = 0xd08, .m32 = &A32.cortex_a72, .m64 = &A64.cortex_a72 },
5355
E{ .part = 0xd09, .m32 = &A32.cortex_a73, .m64 = &A64.cortex_a73 },
5456
E{ .part = 0xd0a, .m32 = &A32.cortex_a75, .m64 = &A64.cortex_a75 },
5557
E{ .part = 0xd0b, .m32 = &A32.cortex_a76, .m64 = &A64.cortex_a76 },
5658
E{ .part = 0xd0c, .m32 = &A32.neoverse_n1, .m64 = &A64.neoverse_n1 },
5759
E{ .part = 0xd0d, .m32 = &A32.cortex_a77, .m64 = &A64.cortex_a77 },
58-
E{ .part = 0xd13, .m32 = &A32.cortex_r52, .m64 = null },
59-
E{ .part = 0xd20, .m32 = &A32.cortex_m23, .m64 = null },
60-
E{ .part = 0xd21, .m32 = &A32.cortex_m33, .m64 = null },
60+
E{ .part = 0xd0e, .m32 = &A32.cortex_a76ae, .m64 = &A64.cortex_a76ae },
61+
E{ .part = 0xd13, .m32 = &A32.cortex_r52 },
62+
E{ .part = 0xd14, .m64 = &A64.cortex_r82ae },
63+
E{ .part = 0xd15, .m64 = &A64.cortex_r82 },
64+
E{ .part = 0xd16, .m32 = &A32.cortex_r52plus },
65+
E{ .part = 0xd20, .m32 = &A32.cortex_m23 },
66+
E{ .part = 0xd21, .m32 = &A32.cortex_m33 },
67+
E{ .part = 0xd40, .m32 = &A32.neoverse_v1, .m64 = &A64.neoverse_v1 },
6168
E{ .part = 0xd41, .m32 = &A32.cortex_a78, .m64 = &A64.cortex_a78 },
69+
E{ .part = 0xd42, .m32 = &A32.cortex_a78ae, .m64 = &A64.cortex_a78ae },
70+
E{ .part = 0xd43, .m64 = &A64.cortex_a65ae },
71+
E{ .part = 0xd44, .m32 = &A32.cortex_x1, .m64 = &A64.cortex_x1 },
72+
E{ .part = 0xd46, .m64 = &A64.cortex_a510 },
73+
E{ .part = 0xd47, .m32 = &A32.cortex_a710, .m64 = &A64.cortex_a710 },
74+
E{ .part = 0xd48, .m64 = &A64.cortex_x2 },
75+
E{ .part = 0xd49, .m32 = &A32.neoverse_n2, .m64 = &A64.neoverse_n2 },
76+
E{ .part = 0xd4a, .m64 = &A64.neoverse_e1 },
6277
E{ .part = 0xd4b, .m32 = &A32.cortex_a78c, .m64 = &A64.cortex_a78c },
6378
E{ .part = 0xd4c, .m32 = &A32.cortex_x1c, .m64 = &A64.cortex_x1c },
64-
E{ .part = 0xd44, .m32 = &A32.cortex_x1, .m64 = &A64.cortex_x1 },
65-
E{ .part = 0xd02, .m64 = &A64.cortex_a34 },
66-
E{ .part = 0xd06, .m64 = &A64.cortex_a65 },
67-
E{ .part = 0xd43, .m64 = &A64.cortex_a65ae },
79+
E{ .part = 0xd4d, .m64 = &A64.cortex_a715 },
80+
E{ .part = 0xd4e, .m64 = &A64.cortex_x3 },
81+
E{ .part = 0xd4f, .m64 = &A64.neoverse_v2 },
82+
E{ .part = 0xd80, .m64 = &A64.cortex_a520 },
83+
E{ .part = 0xd81, .m64 = &A64.cortex_a720 },
84+
E{ .part = 0xd82, .m64 = &A64.cortex_x4 },
85+
E{ .part = 0xd83, .m64 = &A64.neoverse_v3ae },
86+
E{ .part = 0xd84, .m64 = &A64.neoverse_v3 },
87+
E{ .part = 0xd85, .m64 = &A64.cortex_x925 },
88+
E{ .part = 0xd87, .m64 = &A64.cortex_a725 },
89+
E{ .part = 0xd88, .m64 = &A64.cortex_a520ae },
90+
E{ .part = 0xd89, .m64 = &A64.cortex_a720ae },
91+
E{ .part = 0xd8e, .m64 = &A64.neoverse_n3 },
6892
};
6993
// implementer = 0x42
7094
const Broadcom = [_]E{
@@ -97,6 +121,7 @@ pub const cpu_models = struct {
97121
};
98122
// implementer = 0x51
99123
const Qualcomm = [_]E{
124+
E{ .part = 0x001, .m64 = &A64.oryon_1 },
100125
E{ .part = 0x06f, .m32 = &A32.krait },
101126
E{ .part = 0x201, .m64 = &A64.kryo, .m32 = &A64.kryo },
102127
E{ .part = 0x205, .m64 = &A64.kryo, .m32 = &A64.kryo },
@@ -110,7 +135,7 @@ pub const cpu_models = struct {
110135
E{ .part = 0xc00, .m64 = &A64.falkor },
111136
E{ .part = 0xc01, .m64 = &A64.saphira },
112137
};
113-
138+
// implementer = 0x61
114139
const Apple = [_]E{
115140
E{ .part = 0x022, .m64 = &A64.apple_m1 },
116141
E{ .part = 0x023, .m64 = &A64.apple_m1 },

Diff for: ‎lib/std/zig/system/darwin/macos.zig

+13-11
Original file line numberDiff line numberDiff line change
@@ -408,22 +408,24 @@ pub fn detectNativeCpuAndFeatures() ?Target.Cpu {
408408
switch (current_arch) {
409409
.aarch64, .aarch64_be => {
410410
const model = switch (cpu_family) {
411-
.ARM_EVEREST_SAWTOOTH => &Target.aarch64.cpu.apple_a16,
412-
.ARM_BLIZZARD_AVALANCHE => &Target.aarch64.cpu.apple_a15,
413-
.ARM_FIRESTORM_ICESTORM => &Target.aarch64.cpu.apple_a14,
414-
.ARM_LIGHTNING_THUNDER => &Target.aarch64.cpu.apple_a13,
415-
.ARM_VORTEX_TEMPEST => &Target.aarch64.cpu.apple_a12,
416-
.ARM_MONSOON_MISTRAL => &Target.aarch64.cpu.apple_a11,
417-
.ARM_HURRICANE => &Target.aarch64.cpu.apple_a10,
418-
.ARM_TWISTER => &Target.aarch64.cpu.apple_a9,
411+
.ARM_CYCLONE => &Target.aarch64.cpu.apple_a7,
419412
.ARM_TYPHOON => &Target.aarch64.cpu.apple_a8,
420-
.ARM_CYCLONE => &Target.aarch64.cpu.cyclone,
421-
.ARM_COLL => &Target.aarch64.cpu.apple_a17,
413+
.ARM_TWISTER => &Target.aarch64.cpu.apple_a9,
414+
.ARM_HURRICANE => &Target.aarch64.cpu.apple_a10,
415+
.ARM_MONSOON_MISTRAL => &Target.aarch64.cpu.apple_a11,
416+
.ARM_VORTEX_TEMPEST => &Target.aarch64.cpu.apple_a12,
417+
.ARM_LIGHTNING_THUNDER => &Target.aarch64.cpu.apple_a13,
418+
.ARM_FIRESTORM_ICESTORM => &Target.aarch64.cpu.apple_m1, // a14
419+
.ARM_BLIZZARD_AVALANCHE => &Target.aarch64.cpu.apple_m2, // a15
420+
.ARM_EVEREST_SAWTOOTH => &Target.aarch64.cpu.apple_m3, // a16
422421
.ARM_IBIZA => &Target.aarch64.cpu.apple_m3, // base
423-
.ARM_LOBOS => &Target.aarch64.cpu.apple_m3, // pro
424422
.ARM_PALMA => &Target.aarch64.cpu.apple_m3, // max
423+
.ARM_LOBOS => &Target.aarch64.cpu.apple_m3, // pro
424+
.ARM_COLL => &Target.aarch64.cpu.apple_a17, // a17 pro
425425
.ARM_DONAN => &Target.aarch64.cpu.apple_m4, // base
426426
.ARM_BRAVA => &Target.aarch64.cpu.apple_m4, // pro/max
427+
.ARM_TAHITI => &Target.aarch64.cpu.apple_m4, // a18 pro
428+
.ARM_TUPAI => &Target.aarch64.cpu.apple_m4, // a18
427429
else => return null,
428430
};
429431

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