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允许重写中断控制API以支持独立的中断管理 #9305

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merged 2 commits into from
Aug 29, 2024

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Evlers
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@Evlers Evlers commented Aug 14, 2024

…pi to support independent interrupts management

拉取/合并请求描述:(PR description)

[

为什么提交这份PR (why to submit this PR)

在程序需要精准的中断响应时,由于rt-thread多处地方调用rt_hw_interrupt_disable导致中断延迟的问题

你的解决方案是什么 (what is your solution)

  • libcpu中的rt_hw_interrupt_disable函数添加weak修饰以实现临界区的重写
  • 在对应bsp的board.c文件中添加如下代码
#ifdef RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT
#define RT_NVIC_PRO_BITS    __NVIC_PRIO_BITS

rt_base_t rt_hw_interrupt_disable(void)
{
    rt_base_t level = __get_BASEPRI();
    __set_BASEPRI(RT_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - RT_NVIC_PRO_BITS));

    __ISB();
    __DSB();

    return level;
}

void rt_hw_interrupt_enable(rt_base_t level)
{
    __set_BASEPRI(level);
}

#endif /* RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT */
  • board目录Kconfig文件中添加如下配置
    menuconfig RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT
        bool "Enable independent interrupt management"
        default n

        if RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT
            config RT_MAX_SYSCALL_INTERRUPT_PRIORITY
                int "Set max syscall interrupt priority"
                range 0 7
                default 2
        endif
  • 在新加的两个函数中使用的是basepri寄存器来完成中断管理的,例如RT_MAX_SYSCALL_INTERRUPT_PRIORITY配置为0x01,则系统只屏蔽0x01-0xFF优先级的中断
  • 而需要精准中断则使用优先级0,不受系统管理,但是也不能调用rt-thread中的任何API
  • 通过basepri寄存器实现独立的中断管理时,需要注意优先级数值低于RT_MAX_SYSCALL_INTERRUPT_PRIORITY的中断不能调用任何系统API

在不重写rt_hw_interrupt_disable & rt_hw_interrupt_enable函数的情况下不影响之前的临界区代码

请提供验证的bsp和config (provide the config and bsp)

  • BSP: bsp/gd32/arm/gd32470z-lckfb
  • .config:
    #define RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT
    #define RT_MAX_SYSCALL_INTERRUPT_PRIORITY 2
  • action:

]

当前拉取/合并请求的状态 Intent for your PR

必须选择一项 Choose one (Mandatory):

  • 本拉取/合并请求是一个草稿版本 This PR is for a code-review and is intended to get feedback
  • 本拉取/合并请求是一个成熟版本 This PR is mature, and ready to be integrated into the repo

代码质量 Code Quality:

我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:

  • 已经仔细查看过代码改动的对比 Already check the difference between PR and old code
  • 代码风格正确,包括缩进空格,命名及其他风格 Style guide is adhered to, including spacing, naming and other styles
  • 没有垃圾代码,代码尽量精简,不包含#if 0代码,不包含已经被注释了的代码 All redundant code is removed and cleaned up
  • 所有变更均有原因及合理的,并且不会影响到其他软件组件代码或BSP All modifications are justified and not affect other components or BSP
  • 对难懂代码均提供对应的注释 I've commented appropriately where code is tricky
  • 代码是高质量的 Code in this PR is of high quality
  • 已经使用formatting 等源码格式化工具确保格式符合RT-Thread代码规范 This PR complies with RT-Thread code specification

…pi to support independent interrupts management
@Rbb666 Rbb666 added the libcpu label Aug 14, 2024
@Rbb666 Rbb666 self-requested a review August 29, 2024 01:59
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Rbb666 commented Aug 29, 2024

@Evlers PR的描述内容可以整理一份readme放在这个目录下吗,在PR描述感觉容易被忽略掉。

@@ -208,6 +211,10 @@ rt_hw_context_switch_to:
CPSIE F
CPSIE I

/* clear the BASEPRI register to disable masking priority */
MOV r0, #0x00
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我看已经实现了虚定义,原来的这块为什么还要改呢?

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  • 因为在rtthread_startup函数中调用了rt_hw_interrupt_disable函数来屏蔽中断,但是之后没有再调用rt_hw_interrupt_enable函数来禁用屏蔽中断,而是直接在rt_system_scheduler_start函数中调用rt_hw_context_switch_to来启用中断。
  • rt_hw_context_switch_to中使用CPSIE指令来启用中断,所以需要在CPSIE之后清除basepri寄存器以禁用中断优先级的屏蔽。

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Evlers commented Aug 29, 2024

@Evlers PR的描述内容可以整理一份readme放在这个目录下吗,在PR描述感觉容易被忽略掉。

好的,我整理一份README.md文件到cortex-m4目录中

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Rbb666 commented Aug 29, 2024

希望后面可以把其他的Cortex-M系列都改成这种方式吧

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Evlers commented Aug 29, 2024

希望后面可以把其他的Cortex-M系列都改成这种方式吧

好嘞,我有空把支持的系列都改下。
basepri寄存器只有Cortex-M3以上才有,所以Cortex-M0Cortex-M0+就无法做这个支持了

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Rbb666 commented Aug 29, 2024

希望后面可以把其他的Cortex-M系列都改成这种方式吧

好嘞,我有空把支持的系列都改下。
basepri寄存器只有Cortex-M3以上才有,所以Cortex-M0Cortex-M0+就无法做这个支持了

m0可以不用管,m0本身也没太多的实时控制场景吧,应该是偏向低功耗的

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Rbb666 commented Aug 29, 2024

@Evlers PR的描述内容可以整理一份readme放在这个目录下吗,在PR描述感觉容易被忽略掉。

好的,我整理一份README.md文件到cortex-m4目录中

感谢~

@Rbb666 Rbb666 merged commit 8249e71 into RT-Thread:master Aug 29, 2024
45 checks passed
@Evlers Evlers deleted the opt_int branch August 29, 2024 06:08
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