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[spectext] Rename i8x16.any_true to v128.any_true
The renaming was accepted in #416. Interpreter was changed in #426. This makes similar changes to the formal text.
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‎document/core/appendix/gen-index-instructions.py

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -404,9 +404,9 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
404404
Instruction(r'\V128.\VOR', r'\hex{FD}~~80', r'[\V128~\V128] \to [\V128]', r'validation <valid-vsbinop>', r'execution <exec-vsbinop>', r'operator <op-ior>'),
405405
Instruction(r'\V128.\VXOR', r'\hex{FD}~~81', r'[\V128~\V128] \to [\V128]', r'validation <valid-vsbinop>', r'execution <exec-vsbinop>', r'operator <op-ixor>'),
406406
Instruction(r'\V128.\BITSELECT', r'\hex{FD}~~82', r'[\V128~\V128~\V128] \to [\V128]', r'validation <valid-vsternop>', r'execution <exec-vsternop>', r'operator <op-ibitselect>'),
407+
Instruction(r'\V128.\ANYTRUE', r'\hex{FD}~~98', r'[\V128] \to [\I32]', r'validation <valid-vitestop>', r'execution <exec-vitestop>'),
407408
Instruction(r'\I8X16.\VABS', r'\hex{FD}~~96', r'[\V128] \to [\V128]', r'validation <valid-vunop>', r'execution <exec-vunop>', r'operator <op-iabs>'),
408409
Instruction(r'\I8X16.\VNEG', r'\hex{FD}~~97', r'[\V128] \to [\V128]', r'validation <valid-vunop>', r'execution <exec-vunop>', r'operator <op-ineg>'),
409-
Instruction(r'\I8X16.\ANYTRUE', r'\hex{FD}~~98', r'[\V128] \to [\I32]', r'validation <valid-vitestop>', r'execution <exec-vitestop>'),
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Instruction(r'\I8X16.\ALLTRUE', r'\hex{FD}~~99', r'[\V128] \to [\I32]', r'validation <valid-vitestop>', r'execution <exec-vitestop>'),
411411
Instruction(r'\I8X16.\BITMASK', r'\hex{FD}~~100', r'[\V128] \to [\I32]', r'validation <valid-simd-bitmask>', r'execution <exec-simd-bitmask>'),
412412
Instruction(r'\I8X16.\NARROW\K{\_i16x8\_s}', r'\hex{FD}~~101', r'[\V128~\V128] \to [\V128]', r'validation <valid-vbinop>', r'execution <exec-simd-narrow>'),
@@ -427,7 +427,6 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
427427
Instruction(r'\I8X16.\AVGR\K{\_u}', r'\hex{FD}~~123', r'[\V128~\V128] \to [\V128]', r'validation <valid-vbinop>', r'execution <exec-vbinop>', r'operator <op-iavgr_u>'),
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Instruction(r'\I16X8.\VABS', r'\hex{FD}~~128', r'[\V128] \to [\V128]', r'validation <valid-vunop>', r'execution <exec-vunop>', r'operator <op-iabs>'),
429429
Instruction(r'\I16X8.\VNEG', r'\hex{FD}~~129', r'[\V128] \to [\V128]', r'validation <valid-vunop>', r'execution <exec-vunop>', r'operator <op-ineg>'),
430-
Instruction(r'\I16X8.\ANYTRUE', r'\hex{FD}~~130', r'[\V128] \to [\I32]', r'validation <valid-vitestop>', r'execution <exec-vitestop>'),
431430
Instruction(r'\I16X8.\ALLTRUE', r'\hex{FD}~~131', r'[\V128] \to [\I32]', r'validation <valid-vitestop>', r'execution <exec-vitestop>'),
432431
Instruction(r'\I16X8.\BITMASK', r'\hex{FD}~~132', r'[\V128] \to [\I32]', r'validation <valid-simd-bitmask>', r'execution <exec-simd-bitmask>'),
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Instruction(r'\I16X8.\NARROW\K{\_i16x8\_s}', r'\hex{FD}~~133', r'[\V128~\V128] \to [\V128]', r'validation <valid-vbinop>', r'execution <exec-simd-narrow>'),
@@ -453,7 +452,6 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
453452
Instruction(r'\I16X8.\AVGR\K{\_u}', r'\hex{FD}~~155', r'[\V128~\V128] \to [\V128]', r'validation <valid-vbinop>', r'execution <exec-vbinop>', r'operator <op-iavgr_u>'),
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Instruction(r'\I32X4.\VABS', r'\hex{FD}~~160', r'[\V128] \to [\V128]', r'validation <valid-vunop>', r'execution <exec-vunop>', r'operator <op-iabs>'),
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Instruction(r'\I32X4.\VNEG', r'\hex{FD}~~161', r'[\V128] \to [\V128]', r'validation <valid-vunop>', r'execution <exec-vunop>', r'operator <op-ineg>'),
456-
Instruction(r'\I32X4.\ANYTRUE', r'\hex{FD}~~162', r'[\V128] \to [\I32]', r'validation <valid-vitestop>', r'execution <exec-vitestop>'),
457455
Instruction(r'\I32X4.\ALLTRUE', r'\hex{FD}~~163', r'[\V128] \to [\I32]', r'validation <valid-vitestop>', r'execution <exec-vitestop>'),
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Instruction(r'\I32X4.\BITMASK', r'\hex{FD}~~164', r'[\V128] \to [\I32]', r'validation <valid-simd-bitmask>', r'execution <exec-simd-bitmask>'),
459457
Instruction(r'\I32X4.\WIDEN\K{\_low\_i16x8\_s}', r'\hex{FD}~~167', r'[\V128] \to [\V128]', r'validation <valid-vunop>', r'execution <exec-simd-widen>'),

‎document/core/appendix/index-instructions.rst

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -352,9 +352,9 @@ Instruction Binary Opcode Type
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:math:`\V128.\VOR` :math:`\hex{FD}~~80` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <validation <valid-vsbinop>>` :ref:`execution <execution <exec-vsbinop>>`, :ref:`operator <operator <op-ior>>`
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:math:`\V128.\VXOR` :math:`\hex{FD}~~81` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <validation <valid-vsbinop>>` :ref:`execution <execution <exec-vsbinop>>`, :ref:`operator <operator <op-ixor>>`
354354
:math:`\V128.\BITSELECT` :math:`\hex{FD}~~82` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation <validation <valid-vsternop>>` :ref:`execution <execution <exec-vsternop>>`, :ref:`operator <operator <op-ibitselect>>`
355+
:math:`\V128.\ANYTRUE` :math:`\hex{FD}~~98` :math:`[\V128] \to [\I32]` :ref:`validation <validation <valid-vitestop>>` :ref:`execution <execution <exec-vitestop>>`
355356
:math:`\I8X16.\VABS` :math:`\hex{FD}~~96` :math:`[\V128] \to [\V128]` :ref:`validation <validation <valid-vunop>>` :ref:`execution <execution <exec-vunop>>`, :ref:`operator <operator <op-iabs>>`
356357
:math:`\I8X16.\VNEG` :math:`\hex{FD}~~97` :math:`[\V128] \to [\V128]` :ref:`validation <validation <valid-vunop>>` :ref:`execution <execution <exec-vunop>>`, :ref:`operator <operator <op-ineg>>`
357-
:math:`\I8X16.\ANYTRUE` :math:`\hex{FD}~~98` :math:`[\V128] \to [\I32]` :ref:`validation <validation <valid-vitestop>>` :ref:`execution <execution <exec-vitestop>>`
358358
:math:`\I8X16.\ALLTRUE` :math:`\hex{FD}~~99` :math:`[\V128] \to [\I32]` :ref:`validation <validation <valid-vitestop>>` :ref:`execution <execution <exec-vitestop>>`
359359
:math:`\I8X16.\BITMASK` :math:`\hex{FD}~~100` :math:`[\V128] \to [\I32]` :ref:`validation <validation <valid-simd-bitmask>>` :ref:`execution <execution <exec-simd-bitmask>>`
360360
:math:`\I8X16.\NARROW\K{\_i16x8\_s}` :math:`\hex{FD}~~101` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <validation <valid-vbinop>>` :ref:`execution <execution <exec-simd-narrow>>`
@@ -375,7 +375,6 @@ Instruction Binary Opcode Type
375375
:math:`\I8X16.\AVGR\K{\_u}` :math:`\hex{FD}~~123` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <validation <valid-vbinop>>` :ref:`execution <execution <exec-vbinop>>`, :ref:`operator <operator <op-iavgr_u>>`
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:math:`\I16X8.\VABS` :math:`\hex{FD}~~128` :math:`[\V128] \to [\V128]` :ref:`validation <validation <valid-vunop>>` :ref:`execution <execution <exec-vunop>>`, :ref:`operator <operator <op-iabs>>`
377377
:math:`\I16X8.\VNEG` :math:`\hex{FD}~~129` :math:`[\V128] \to [\V128]` :ref:`validation <validation <valid-vunop>>` :ref:`execution <execution <exec-vunop>>`, :ref:`operator <operator <op-ineg>>`
378-
:math:`\I16X8.\ANYTRUE` :math:`\hex{FD}~~130` :math:`[\V128] \to [\I32]` :ref:`validation <validation <valid-vitestop>>` :ref:`execution <execution <exec-vitestop>>`
379378
:math:`\I16X8.\ALLTRUE` :math:`\hex{FD}~~131` :math:`[\V128] \to [\I32]` :ref:`validation <validation <valid-vitestop>>` :ref:`execution <execution <exec-vitestop>>`
380379
:math:`\I16X8.\BITMASK` :math:`\hex{FD}~~132` :math:`[\V128] \to [\I32]` :ref:`validation <validation <valid-simd-bitmask>>` :ref:`execution <execution <exec-simd-bitmask>>`
381380
:math:`\I16X8.\NARROW\K{\_i16x8\_s}` :math:`\hex{FD}~~133` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <validation <valid-vbinop>>` :ref:`execution <execution <exec-simd-narrow>>`
@@ -401,7 +400,6 @@ Instruction Binary Opcode Type
401400
:math:`\I16X8.\AVGR\K{\_u}` :math:`\hex{FD}~~155` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <validation <valid-vbinop>>` :ref:`execution <execution <exec-vbinop>>`, :ref:`operator <operator <op-iavgr_u>>`
402401
:math:`\I32X4.\VABS` :math:`\hex{FD}~~160` :math:`[\V128] \to [\V128]` :ref:`validation <validation <valid-vunop>>` :ref:`execution <execution <exec-vunop>>`, :ref:`operator <operator <op-iabs>>`
403402
:math:`\I32X4.\VNEG` :math:`\hex{FD}~~161` :math:`[\V128] \to [\V128]` :ref:`validation <validation <valid-vunop>>` :ref:`execution <execution <exec-vunop>>`, :ref:`operator <operator <op-ineg>>`
404-
:math:`\I32X4.\ANYTRUE` :math:`\hex{FD}~~162` :math:`[\V128] \to [\I32]` :ref:`validation <validation <valid-vitestop>>` :ref:`execution <execution <exec-vitestop>>`
405403
:math:`\I32X4.\ALLTRUE` :math:`\hex{FD}~~163` :math:`[\V128] \to [\I32]` :ref:`validation <validation <valid-vitestop>>` :ref:`execution <execution <exec-vitestop>>`
406404
:math:`\I32X4.\BITMASK` :math:`\hex{FD}~~164` :math:`[\V128] \to [\I32]` :ref:`validation <validation <valid-simd-bitmask>>` :ref:`execution <execution <exec-simd-bitmask>>`
407405
:math:`\I32X4.\WIDEN\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~167` :math:`[\V128] \to [\V128]` :ref:`validation <validation <valid-vunop>>` :ref:`execution <execution <exec-simd-widen>>`

‎document/core/binary/instructions.rst

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -572,7 +572,8 @@ All other SIMD instructions are plain opcodes without any immediates.
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\hex{FD}~~79{:}\Bu32 &\Rightarrow& \V128.\VANDNOT \\ &&|&
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\hex{FD}~~80{:}\Bu32 &\Rightarrow& \V128.\VOR \\ &&|&
574574
\hex{FD}~~81{:}\Bu32 &\Rightarrow& \V128.\VXOR \\ &&|&
575-
\hex{FD}~~82{:}\Bu32 &\Rightarrow& \V128.\BITSELECT
575+
\hex{FD}~~82{:}\Bu32 &\Rightarrow& \V128.\BITSELECT \\ &&|&
576+
\hex{FD}~~98{:}\Bu32 &\Rightarrow& \V128.\ANYTRUE \\ &&|&
576577
\end{array}
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.. _binary-vitestop:
@@ -587,7 +588,6 @@ All other SIMD instructions are plain opcodes without any immediates.
587588
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
588589
\hex{FD}~~96{:}\Bu32 &\Rightarrow& \I8X16.\VABS \\ &&|&
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\hex{FD}~~97{:}\Bu32 &\Rightarrow& \I8X16.\VNEG \\ &&|&
590-
\hex{FD}~~98{:}\Bu32 &\Rightarrow& \I8X16.\ANYTRUE \\ &&|&
591591
\hex{FD}~~99{:}\Bu32 &\Rightarrow& \I8X16.\ALLTRUE \\ &&|&
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\hex{FD}~~100{:}\Bu32 &\Rightarrow& \I8X16.\BITMASK \\ &&|&
593593
\hex{FD}~~101{:}\Bu32 &\Rightarrow& \I8X16.\NARROW\K{\_i16x8\_s} \\ &&|&
@@ -613,7 +613,6 @@ All other SIMD instructions are plain opcodes without any immediates.
613613
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
614614
\hex{FD}~~128{:}\Bu32 &\Rightarrow& \I16X8.\VABS \\ &&|&
615615
\hex{FD}~~129{:}\Bu32 &\Rightarrow& \I16X8.\VNEG \\ &&|&
616-
\hex{FD}~~130{:}\Bu32 &\Rightarrow& \I16X8.\ANYTRUE \\ &&|&
617616
\hex{FD}~~131{:}\Bu32 &\Rightarrow& \I16X8.\ALLTRUE \\ &&|&
618617
\hex{FD}~~132{:}\Bu32 &\Rightarrow& \I16X8.\BITMASK \\ &&|&
619618
\hex{FD}~~133{:}\Bu32 &\Rightarrow& \I16X8.\NARROW\K{\_i32x4\_s} \\ &&|&
@@ -644,7 +643,6 @@ All other SIMD instructions are plain opcodes without any immediates.
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\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
645644
\hex{FD}~~160{:}\Bu32 &\Rightarrow& \I32X4.\VABS \\ &&|&
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\hex{FD}~~161{:}\Bu32 &\Rightarrow& \I32X4.\VNEG \\ &&|&
647-
\hex{FD}~~162{:}\Bu32 &\Rightarrow& \I32X4.\ANYTRUE \\ &&|&
648646
\hex{FD}~~163{:}\Bu32 &\Rightarrow& \I32X4.\ALLTRUE \\ &&|&
649647
\hex{FD}~~164{:}\Bu32 &\Rightarrow& \I32X4.\BITMASK \\ &&|&
650648
\hex{FD}~~167{:}\Bu32 &\Rightarrow& \I32X4.\WIDEN\K{\_low\_i16x8\_s} \\ &&|&

‎document/core/exec/instructions.rst

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -284,6 +284,26 @@ SIMD instructions are defined in terms of generic numeric operators applied lane
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\end{array}
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287+
.. _exec-simd-any_true:
288+
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:math:`\V128\K{.}\ANYTRUE`
290+
...........................
291+
292+
1. Assert: due to :ref:`validation <valid-vitestop>`, a value of :ref:`value type <syntax-valtype>` |V128| is on the top of the stack.
293+
294+
2. Pop the value :math:`\V128.\VCONST~c_1` from the stack.
295+
296+
3. Let :math:`i` be the result of computing :math:`\ine_{128}(c_1, 0)`.
297+
298+
4. Push the value :math:`\I32.\CONST~i` onto the stack.
299+
300+
.. math::
301+
\begin{array}{lcl@{\qquad}l}
302+
(\V128\K{.}\VCONST~c_1)~\V128\K{.}\ANYTRUE &\stepto& (\I32\K{.}\CONST~i)
303+
& (\iff i = \ine_{128}(c_1, 0)) \\
304+
\end{array}
305+
306+
287307
.. _exec-simd-swizzle:
288308

289309
:math:`\K{i8x16.}\SWIZZLE`
@@ -561,26 +581,6 @@ SIMD instructions are defined in terms of generic numeric operators applied lane
561581
\end{array}
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564-
.. _exec-simd-any_true:
565-
566-
:math:`\shape\K{.}\ANYTRUE`
567-
...........................
568-
569-
1. Assert: due to :ref:`validation <valid-vitestop>`, a value of :ref:`value type <syntax-valtype>` |V128| is on the top of the stack.
570-
571-
2. Pop the value :math:`\V128.\VCONST~c_1` from the stack.
572-
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3. Let :math:`i` be the result of computing :math:`\ine_{128}(c_1, 0)`.
574-
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4. Push the value :math:`\I32.\CONST~i` onto the stack.
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.. math::
578-
\begin{array}{lcl@{\qquad}l}
579-
(\V128\K{.}\VCONST~c_1)~\shape\K{.}\ANYTRUE &\stepto& (\I32\K{.}\CONST~i)
580-
& (\iff i = \ine_{128}(c_1, 0)) \\
581-
\end{array}
582-
583-
584584
.. _exec-simd-bitmask:
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586586
:math:`t\K{x}N\K{.}\BITMASK`

‎document/core/syntax/instructions.rst

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -211,6 +211,7 @@ SIMD instructions provide basic operations over :ref:`values <syntax-value>` of
211211
\K{v128.}\vsunop \\&&|&
212212
\K{v128.}\vsbinop \\&&|&
213213
\K{v128.}\vsternop \\&&|&
214+
\K{v128.}\ANYTRUE \\&&|&
214215
\K{i8x16.}\SHUFFLE~\laneidx^{16} \\&&|&
215216
\K{i8x16.}\SWIZZLE \\&&|&
216217
\shape\K{.}\SPLAT \\&&|&
@@ -266,7 +267,6 @@ SIMD instructions provide basic operations over :ref:`values <syntax-value>` of
266267
\production{SIMD ternary operator} & \vsternop &::=&
267268
\K{bitselect} \\
268269
\production{SIMD test operator} & \vitestop &::=&
269-
\K{any\_true} ~|~
270270
\K{all\_true} \\
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\production{SIMD integer relational operator} & \virelop &::=&
272272
\K{eq} ~|~

‎document/core/text/instructions.rst

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -606,7 +606,8 @@ SIMD const instructions have a mandatory :ref:`shape <syntax-simd-shape>` descri
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\text{v128.andnot} &\Rightarrow& \V128.\VANDNOT\\ &&|&
607607
\text{v128.or} &\Rightarrow& \V128.\VOR\\ &&|&
608608
\text{v128.xor} &\Rightarrow& \V128.\VXOR\\ &&|&
609-
\text{v128.bitselect} &\Rightarrow& \V128.\BITSELECT
609+
\text{v128.bitselect} &\Rightarrow& \V128.\BITSELECT\\ &&|&
610+
\text{v128.any\_true} &\Rightarrow& \V128.\ANYTRUE
610611
\end{array}
611612
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.. _text-vitestop:
@@ -621,7 +622,6 @@ SIMD const instructions have a mandatory :ref:`shape <syntax-simd-shape>` descri
621622
\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
622623
\text{i8x16.abs} &\Rightarrow& \I8X16.\VABS\\ &&|&
623624
\text{i8x16.neg} &\Rightarrow& \I8X16.\VNEG\\ &&|&
624-
\text{i8x16.any\_true} &\Rightarrow& \I8X16.\ANYTRUE\\ &&|&
625625
\text{i8x16.all\_true} &\Rightarrow& \I8X16.\ALLTRUE\\ &&|&
626626
\text{i8x16.bitmask} &\Rightarrow& \I8X16.\BITMASK\\ &&|&
627627
\text{i8x16.narrow\_i16x8\_s} &\Rightarrow& \I8X16.\NARROW\K{\_i16x8\_s}\\ &&|&
@@ -647,7 +647,6 @@ SIMD const instructions have a mandatory :ref:`shape <syntax-simd-shape>` descri
647647
\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
648648
\text{i16x8.abs} &\Rightarrow& \I16X8.\VABS\\ &&|&
649649
\text{i16x8.neg} &\Rightarrow& \I16X8.\VNEG\\ &&|&
650-
\text{i16x8.any\_true} &\Rightarrow& \I16X8.\ANYTRUE\\ &&|&
651650
\text{i16x8.all\_true} &\Rightarrow& \I16X8.\ALLTRUE\\ &&|&
652651
\text{i16x8.bitmask} &\Rightarrow& \I16X8.\BITMASK\\ &&|&
653652
\text{i16x8.narrow\_i32x4\_s} &\Rightarrow& \I16X8.\NARROW\K{\_i32x4\_s}\\ &&|&
@@ -678,7 +677,6 @@ SIMD const instructions have a mandatory :ref:`shape <syntax-simd-shape>` descri
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\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
679678
\text{i32x4.abs} &\Rightarrow& \I32X4.\VABS\\ &&|&
680679
\text{i32x4.neg} &\Rightarrow& \I32X4.\VNEG\\ &&|&
681-
\text{i32x4.any\_true} &\Rightarrow& \I32X4.\ANYTRUE\\ &&|&
682680
\text{i32x4.all\_true} &\Rightarrow& \I32X4.\ALLTRUE\\ &&|&
683681
\text{i32x4.bitmask} &\Rightarrow& \I32X4.\BITMASK\\ &&|&
684682
\text{i32x4.widen\_low\_i16x8\_s} &\Rightarrow& \I32X4.\WIDEN\K{\_low\_i16x8\_s}\\ &&|&

‎document/core/valid/instructions.rst

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -240,6 +240,20 @@ We also define an auxiliary function to get number of packed numeric types in a
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}
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.. _valid-any-true:
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245+
:math:`\V128\K{.}\ANYTRUE`
246+
............................
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248+
* The instruction is valid with type :math:`[\V128] \to [\I32]`.
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.. math::
251+
\frac{
252+
}{
253+
C \vdashinstr \V128\K{.}\ANYTRUE : [\V128] \to [\I32]
254+
}
255+
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.. _valid-simd-shuffle:
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:math:`\K{i8x16.}\SHUFFLE~\laneidx^{16}`

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