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Opcode renumbering #209
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,124 @@ | ||
| | Memory instruction | opcode | | ||
| | ------------------ | ------ | | ||
| | v128.load | 0x00 | | ||
| | i16x8.load8x8_s | 0x01 | | ||
| | i16x8.load8x8_u | 0x02 | | ||
| | i32x4.load16x4_s | 0x03 | | ||
| | i32x4.load16x4_u | 0x04 | | ||
| | i64x2.load32x2_s | 0x05 | | ||
| | i64x2.load32x2_u | 0x06 | | ||
| | v8x16.load_splat | 0x07 | | ||
| | v16x8.load_splat | 0x08 | | ||
| | v32x4.load_splat | 0x09 | | ||
| | v64x2.load_splat | 0x0a | | ||
| | v128.store | 0x0b | | ||
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| | Basic instruction | opcode | | ||
| | -------------------- | ------ | | ||
| | v128.const | 0x0c | | ||
| | v8x16.shuffle | 0x0d | | ||
| | v8x16.swizzle | 0x0e | | ||
| | i8x16.splat | 0x0f | | ||
| | i8x16.extract_lane_s | 0x10 | | ||
| | i8x16.extract_lane_u | 0x11 | | ||
| | i8x16.replace_lane | 0x12 | | ||
| | i16x8.splat | 0x13 | | ||
| | i16x8.extract_lane_s | 0x14 | | ||
| | i16x8.extract_lane_u | 0x15 | | ||
| | i16x8.replace_lane | 0x16 | | ||
| | i32x4.splat | 0x17 | | ||
| | i32x4.extract_lane | 0x18 | | ||
| | i32x4.replace_lane | 0x19 | | ||
| | i64x2.splat | 0x1a | | ||
| | i64x2.extract_lane | 0x1b | | ||
| | i64x2.replace_lane | 0x1c | | ||
| | f32x4.splat | 0x1d | | ||
| | f32x4.extract_lane | 0x1e | | ||
| | f32x4.replace_lane | 0x1f | | ||
| | f64x2.splat | 0x20 | | ||
| | f64x2.extract_lane | 0x21 | | ||
| | f64x2.replace_lane | 0x22 | | ||
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||
| | i8x16 Cmp | opcode | i16x8 Cmp | opcode | i32x4 Cmp | opcode | | ||
| | ---------- | ------ | ---------- | ------ | ---------- | ------ | | ||
| | i8x16.eq | 0x23 | i16x8.eq | 0x2d | i32x4.eq | 0x37 | | ||
| | i8x16.ne | 0x24 | i16x8.ne | 0x2e | i32x4.ne | 0x38 | | ||
| | i8x16.lt_s | 0x25 | i16x8.lt_s | 0x2f | i32x4.lt_s | 0x39 | | ||
| | i8x16.lt_u | 0x26 | i16x8.lt_u | 0x30 | i32x4.lt_u | 0x3a | | ||
| | i8x16.gt_s | 0x27 | i16x8.gt_s | 0x31 | i32x4.gt_s | 0x3b | | ||
| | i8x16.gt_u | 0x28 | i16x8.gt_u | 0x32 | i32x4.gt_u | 0x3c | | ||
| | i8x16.le_s | 0x29 | i16x8.le_s | 0x33 | i32x4.le_s | 0x3d | | ||
| | i8x16.le_u | 0x2a | i16x8.le_u | 0x34 | i32x4.le_u | 0x3e | | ||
| | i8x16.ge_s | 0x2b | i16x8.ge_s | 0x35 | i32x4.ge_s | 0x3f | | ||
| | i8x16.ge_u | 0x2c | i16x8.ge_u | 0x36 | i32x4.ge_u | 0x40 | | ||
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| | f32x4 Cmp | opcode | f64x2 Cmp | opcode | | ||
| | --------- | ------ | --------- | ------ | | ||
| | f32x4.eq | 0x41 | f64x2.eq | 0x47 | | ||
| | f32x4.ne | 0x42 | f64x2.ne | 0x48 | | ||
| | f32x4.lt | 0x43 | f64x2.lt | 0x49 | | ||
| | f32x4.gt | 0x44 | f64x2.gt | 0x4a | | ||
| | f32x4.le | 0x45 | f64x2.le | 0x4b | | ||
| | f32x4.ge | 0x46 | f64x2.ge | 0x4c | | ||
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| | v128 Op | opcode | | ||
| | -------------- | ------ | | ||
| | v128.not | 0x4d | | ||
| | v128.and | 0x4e | | ||
| | v128.andnot | 0x4f | | ||
| | v128.or | 0x50 | | ||
| | v128.xor | 0x51 | | ||
| | v128.bitselect | 0x52 | | ||
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| | i8x16 Op | opcode | i16x8 Op | opcode | i32x4 Op | opcode | i64x2 Op | opcode | | ||
| | -------------------- | ------ | ------------------------ | ------ | ------------------------ | ------ | ----------- | ------ | | ||
| | i8x16.abs | 0x60 | i16x8.abs | 0x80 | i32x4.abs | 0xa0 | ---- | 0xc0 | | ||
| | i8x16.neg | 0x61 | i16x8.neg | 0x81 | i32x4.neg | 0xa1 | i64x2.neg | 0xc1 | | ||
| | i8x16.any_true | 0x62 | i16x8.any_true | 0x82 | i32x4.any_true | 0xa2 | ---- | 0xc2 | | ||
| | i8x16.all_true | 0x63 | i16x8.all_true | 0x83 | i32x4.all_true | 0xa3 | ---- | 0xc3 | | ||
| | ---- bitmask ---- | 0x64 | ---- bitmask ---- | 0x84 | ---- bitmask ---- | 0xa4 | ---- | 0xc4 | | ||
| | i8x16.narrow_i16x8_s | 0x65 | i16x8.narrow_i32x4_s | 0x85 | ---- narrow ---- | 0xa5 | ---- | 0xc5 | | ||
| | i8x16.narrow_i16x8_u | 0x66 | i16x8.narrow_i32x4_u | 0x86 | ---- narrow ---- | 0xa6 | ---- | 0xc6 | | ||
| | ---- widen ---- | 0x67 | i16x8.widen_low_i8x16_s | 0x87 | i32x4.widen_low_i16x8_s | 0xa7 | ---- | 0xc7 | | ||
| | ---- widen ---- | 0x68 | i16x8.widen_high_i8x16_s | 0x88 | i32x4.widen_high_i16x8_s | 0xa8 | ---- | 0xc8 | | ||
| | ---- widen ---- | 0x69 | i16x8.widen_low_i8x16_u | 0x89 | i32x4.widen_low_i16x8_u | 0xa9 | ---- | 0xc9 | | ||
| | ---- widen ---- | 0x6a | i16x8.widen_high_i8x16_u | 0x8a | i32x4.widen_high_i16x8_u | 0xaa | ---- | 0xca | | ||
| | i8x16.shl | 0x6b | i16x8.shl | 0x8b | i32x4.shl | 0xab | i64x2.shl | 0xcb | | ||
| | i8x16.shr_s | 0x6c | i16x8.shr_s | 0x8c | i32x4.shr_s | 0xac | i64x2.shr_s | 0xcc | | ||
| | i8x16.shr_u | 0x6d | i16x8.shr_u | 0x8d | i32x4.shr_u | 0xad | i64x2.shr_u | 0xcd | | ||
| | i8x16.add | 0x6e | i16x8.add | 0x8e | i32x4.add | 0xae | i64x2.add | 0xce | | ||
| | i8x16.add_saturate_s | 0x6f | i16x8.add_saturate_s | 0x8f | ---- add_sat ---- | 0xaf | ---- | 0xcf | | ||
| | i8x16.add_saturate_u | 0x70 | i16x8.add_saturate_u | 0x90 | ---- add_sat ---- | 0xb0 | ---- | 0xd0 | | ||
| | i8x16.sub | 0x71 | i16x8.sub | 0x91 | i32x4.sub | 0xb1 | i64x2.sub | 0xd1 | | ||
| | i8x16.sub_saturate_s | 0x72 | i16x8.sub_saturate_s | 0x92 | ---- sub_sat ---- | 0xb2 | ---- | 0xd2 | | ||
| | i8x16.sub_saturate_u | 0x73 | i16x8.sub_saturate_u | 0x93 | ---- sub_sat ---- | 0xb3 | ---- | 0xd3 | | ||
| | ---- dot ---- | 0x74 | ---- dot ---- | 0x94 | i32x4.dot_i16x8_s | 0xb4 | ---- | 0xd4 | | ||
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| | ---- mul ---- | 0x75 | i16x8.mul | 0x95 | i32x4.mul | 0xb5 | i64x2.mul | 0xd5 | | ||
| | i8x16.min_s | 0x76 | i16x8.min_s | 0x96 | i32x4.min_s | 0xb6 | ---- | 0xd6 | | ||
| | i8x16.min_u | 0x77 | i16x8.min_u | 0x97 | i32x4.min_u | 0xb7 | ---- | 0xd7 | | ||
| | i8x16.max_s | 0x78 | i16x8.max_s | 0x98 | i32x4.max_s | 0xb8 | ---- | 0xd8 | | ||
| | i8x16.max_u | 0x79 | i16x8.max_u | 0x99 | i32x4.max_u | 0xb9 | ---- | 0xd9 | | ||
| | ---- avgr_s ---- | 0x7a | ---- avgr_s ---- | 0x9a | ---- avgr_s ---- | 0xba | ---- | 0xda | | ||
| | i8x16.avgr_u | 0x7b | i16x8.avgr_u | 0x9b | ---- avgr_u ---- | 0xbb | ---- | 0xdb | | ||
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| | f32x4 Op | opcode | f64x2 Op | opcode | | ||
| | --------------- | ------ | --------------- | ------ | | ||
| | f32x4.abs | 0xe0 | f64x2.abs | 0xf0 | | ||
| | f32x4.neg | 0xe1 | f64x2.neg | 0xf1 | | ||
| | ---- round ---- | 0xe2 | ---- round ---- | 0xf2 | | ||
| | f32x4.sqrt | 0xe3 | f64x2.sqrt | 0xf3 | | ||
| | f32x4.add | 0xe4 | f64x2.add | 0xf4 | | ||
| | f32x4.sub | 0xe5 | f64x2.sub | 0xf5 | | ||
| | f32x4.mul | 0xe6 | f64x2.mul | 0xf6 | | ||
| | f32x4.div | 0xe7 | f64x2.div | 0xf7 | | ||
| | f32x4.min | 0xe8 | f64x2.min | 0xf8 | | ||
| | f32x4.max | 0xe9 | f64x2.max | 0xf9 | | ||
| | ---- pmin ---- | 0xea | ---- pmin ---- | 0xfa | | ||
| | ---- pmax ---- | 0xeb | ---- pmax ---- | 0xfb | | ||
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| | Conversion Op | opcode | | ||
| | ----------------------- | ------ | | ||
| | i32x4.trunc_sat_f32x4_s | 0x100 | | ||
|
There was a problem hiding this comment. nit: can this be written as 0x0100? It makes it slightly clearer that it's 2 bytes. |
||
| | i32x4.trunc_sat_f32x4_u | 0x101 | | ||
| | f32x4.convert_i32x4_s | 0x102 | | ||
| | f32x4.convert_i32x4_u | 0x103 | | ||
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The ordering here is mildly unsatisfying for decoding purposes. Similarly to the existing spec, this interleaves splat/extract/replace lane, and they have different encoding formats. Thoughts on grouping these by instruction type instead? (splats followed by lane operations)
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Yeah I think that sounds reasonable 👍