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[interpreter] Implement i64x2.abs #462

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Feb 10, 2021
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1 change: 1 addition & 0 deletions interpreter/binary/decode.ml
Original file line number Diff line number Diff line change
Expand Up @@ -375,6 +375,7 @@ let simd_prefix s =
| 0x9fl -> i16x8_extmul_high_i8x16_u
| 0xa0l -> i32x4_abs
| 0xa1l -> i32x4_neg
| 0xa2l -> i64x2_abs
| 0xa3l -> i32x4_all_true
| 0xa4l -> i32x4_bitmask
| 0xa7l -> i32x4_widen_low_i16x8_s
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1 change: 1 addition & 0 deletions interpreter/binary/encode.ml
Original file line number Diff line number Diff line change
Expand Up @@ -350,6 +350,7 @@ let encode m =
| Unary (V128 V128Op.(I32x4 WidenHighS)) -> simd_op 0xa8l
| Unary (V128 V128Op.(I32x4 WidenLowU)) -> simd_op 0xa9l
| Unary (V128 V128Op.(I32x4 WidenHighU)) -> simd_op 0xaal
| Unary (V128 V128Op.(I64x2 Abs)) -> simd_op 0xa2l
| Unary (V128 V128Op.(I64x2 Neg)) -> simd_op 0xc1l
| Unary (V128 V128Op.(I64x2 WidenLowS)) -> simd_op 0xc7l
| Unary (V128 V128Op.(I64x2 WidenHighS)) -> simd_op 0xc8l
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1 change: 1 addition & 0 deletions interpreter/exec/eval_simd.ml
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@ module SimdOp (SXX : Simd.S) (Value : ValueType with type t = SXX.t) = struct
| I32x4 WidenHighU -> to_value (SXX.I32x4_convert.widen_high_u (of_value 1 v))
| I32x4 TruncSatF32x4S -> to_value (SXX.I32x4_convert.trunc_sat_f32x4_s (of_value 1 v))
| I32x4 TruncSatF32x4U -> to_value (SXX.I32x4_convert.trunc_sat_f32x4_u (of_value 1 v))
| I64x2 Abs -> to_value (SXX.I64x2.abs (of_value 1 v))
| I64x2 Neg -> to_value (SXX.I64x2.neg (of_value 1 v))
| I64x2 WidenLowS -> to_value (SXX.I64x2_convert.widen_low_s (of_value 1 v))
| I64x2 WidenHighS -> to_value (SXX.I64x2_convert.widen_high_s (of_value 1 v))
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1 change: 1 addition & 0 deletions interpreter/syntax/operators.ml
Original file line number Diff line number Diff line change
Expand Up @@ -398,6 +398,7 @@ let i64x2_lt_s = Binary (V128 V128Op.(I64x2 LtS))
let i64x2_le_s = Binary (V128 V128Op.(I64x2 LeS))
let i64x2_gt_s = Binary (V128 V128Op.(I64x2 GtS))
let i64x2_ge_s = Binary (V128 V128Op.(I64x2 GeS))
let i64x2_abs = Unary (V128 V128Op.(I64x2 Abs))
let i64x2_neg = Unary (V128 V128Op.(I64x2 Neg))
let i64x2_bitmask = SimdBitmask Simd.I64x2
let i64x2_add = Binary (V128 V128Op.(I64x2 Add))
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1 change: 1 addition & 0 deletions interpreter/text/arrange.ml
Original file line number Diff line number Diff line change
Expand Up @@ -217,6 +217,7 @@ struct
| I32x4 WidenHighU -> "i32x4.widen_high_i16x8_u"
| I32x4 TruncSatF32x4S -> "i32x4.trunc_sat_f32x4_s"
| I32x4 TruncSatF32x4U -> "i32x4.trunc_sat_f32x4_u"
| I64x2 Abs -> "i64x2.abs"
| I64x2 Neg -> "i64x2.neg"
| I64x2 WidenLowS -> "i64x2.widen_low_i32x4_s"
| I64x2 WidenHighS -> "i64x2.widen_high_i32x4_s"
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3 changes: 1 addition & 2 deletions interpreter/text/lexer.mll
Original file line number Diff line number Diff line change
Expand Up @@ -526,8 +526,7 @@ rule token = parse
| (simd_float_shape as s)".min" { BINARY (simd_float_op s f32x4_min f64x2_min) }
| (simd_float_shape as s)".max" { BINARY (simd_float_op s f32x4_max f64x2_max) }
| (simd_shape as s)".abs"
{ only ["i8x16"; "i16x8"; "i32x4"; "f32x4"; "f64x2"] s lexbuf;
UNARY (simdop s i8x16_abs i16x8_abs i32x4_abs unreachable f32x4_abs f64x2_abs) }
{ UNARY (simdop s i8x16_abs i16x8_abs i32x4_abs i64x2_abs f32x4_abs f64x2_abs) }
| "i8x16.popcnt"
{ UNARY i8x16_popcnt }
| (simd_int_shape as s)".all_true"
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12 changes: 11 additions & 1 deletion test/core/simd/meta/simd_int_arith2.py
Original file line number Diff line number Diff line change
Expand Up @@ -523,6 +523,14 @@ def gen_test_cases(self):
fp.write(self.get_all_cases())


class Simdi64x2Case(SimdLaneWiseInteger):
LANE_TYPE = 'i64x2'
class_summary = """;; Tests for {lane_type} [abs] operations."""
BINARY_OPS = ()

UNKNOWN_BINARY_OPS = ()


class Simdi32x4Case(SimdLaneWiseInteger):
LANE_TYPE = 'i32x4'
class_summary = """;; Tests for {lane_type} [min_s, min_u, max_s, max_u, abs] operations."""
Expand All @@ -537,7 +545,6 @@ class Simdi16x8Case(SimdLaneWiseInteger):

BINARY_OPS = ('min_s', 'min_u', 'max_s', 'max_u', 'avgr_u')
UNKNOWN_BINARY_OPS = ('i16x8.avgr', 'i16x8.avgr_s')
UNKNOWN_UNARY_OPS = ('i64x2.abs',)


class Simdi8x16Case(SimdLaneWiseInteger):
Expand All @@ -551,6 +558,9 @@ class Simdi8x16Case(SimdLaneWiseInteger):


def gen_test_cases():
simd_i64x2_case = Simdi64x2Case()
simd_i64x2_case.gen_test_cases()

simd_i32x4_case = Simdi32x4Case()
simd_i32x4_case.gen_test_cases()

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1 change: 0 additions & 1 deletion test/core/simd/simd_i16x8_arith2.wast
Original file line number Diff line number Diff line change
Expand Up @@ -336,7 +336,6 @@
;; Unknown operators
(assert_malformed (module quote "(memory 1) (func (result v128) (i16x8.avgr (v128.const i16x8 0 0 0 0 0 0 0 0) (v128.const i16x8 1 1 1 1 1 1 1 1)))") "unknown operator")
(assert_malformed (module quote "(memory 1) (func (result v128) (i16x8.avgr_s (v128.const i16x8 0 0 0 0 0 0 0 0) (v128.const i16x8 1 1 1 1 1 1 1 1)))") "unknown operator")
(assert_malformed (module quote "(memory 1) (func (result v128) (i64x2.abs (v128.const i16x8 -1 -1 -1 -1 -1 -1 -1 -1)))") "unknown operator")

;; Type check
(assert_invalid (module (func (result v128) (i16x8.min_s (i32.const 0) (f32.const 0.0)))) "type mismatch")
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