Support GOARCH=mips64

src/cmd/asm/internal/arch/arch.go

@@ -471,9 +471,6 @@ func archMips64(linkArch *obj.LinkArch) *Arch {
 	for i := mips.REG_FCR0; i <= mips.REG_FCR31; i++ {
 		register[obj.Rconv(i)] = int16(i)
 	}
-	for i := mips.REG_W0; i <= mips.REG_W31; i++ {
-		register[obj.Rconv(i)] = int16(i)
-	}
 	register["HI"] = mips.REG_HI
 	register["LO"] = mips.REG_LO
 	// Pseudo-registers.
@@ -491,7 +488,6 @@ func archMips64(linkArch *obj.LinkArch) *Arch {
 		"FCR": true,
 		"M":   true,
 		"R":   true,
-		"W":   true,
 	}
 
 	instructions := make(map[string]obj.As)

src/cmd/asm/internal/arch/mips.go

@@ -63,10 +63,6 @@ func mipsRegisterNumber(name string, n int16) (int16, bool) {
 		if 0 <= n && n <= 31 {
 			return mips.REG_R0 + n, true
 		}
-	case "W":
-		if 0 <= n && n <= 31 {
-			return mips.REG_W0 + n, true
-		}
 	}
 	return 0, false
 }

src/cmd/asm/internal/asm/testdata/mips.s

@@ -429,11 +429,6 @@ label4:
 	CLZ	R1, R2 // 70221020
 	CLO	R1, R2 // 70221021
 
-	WSBH	R1, R2 // 7c0110a0
-
-	SEB	R1, R2 // 7c011420
-	SEH	R1, R2 // 7c011620
-
 	// to (Hi, Lo)
 	MADD	R2, R1 // 70220000
 	MSUB	R2, R1 // 70220004

src/cmd/asm/internal/asm/testdata/mips64.s

@@ -587,50 +587,8 @@ label4:
 	CALL	foo(SB)
 	RET	foo(SB)
 
-	// unary operation
 	NEGW	R1, R2 // 00011023
 	NEGV	R1, R2 // 0001102f
-
-	WSBH	R1, R2 // 7c0110a0
-	DSBH	R1, R2 // 7c0110a4
-	DSHD	R1, R2 // 7c011164
-
-	SEB	R1, R2 // 7c011420
-	SEH	R1, R2 // 7c011620
-
-	RET
-
-// MSA VMOVI
-	VMOVB	$511, W0   // 7b0ff807
-	VMOVH	$24, W23   // 7b20c5c7
-	VMOVW	$-24, W15  // 7b5f43c7
-	VMOVD	$-511, W31 // 7b700fc7
-
-	VMOVB	(R0), W8       // 78000220
-	VMOVB	511(R3), W0    // 79ff1820
-	VMOVB	-512(R12), W21 // 7a006560
-	VMOVH	(R24), W12     // 7800c321
-	VMOVH	110(R19), W8   // 78379a21
-	VMOVH	-70(R12), W3   // 7bdd60e1
-	VMOVW	(R3), W31      // 78001fe2
-	VMOVW	64(R20), W16   // 7810a422
-	VMOVW	-104(R17), W24 // 7be68e22
-	VMOVD	(R3), W2       // 780018a3
-	VMOVD	128(R23), W19  // 7810bce3
-	VMOVD	-256(R31), W0  // 7be0f823
-
-	VMOVB	W8, (R0)       // 78000224
-	VMOVB	W0, 511(R3)    // 79ff1824
-	VMOVB	W21, -512(R12) // 7a006564
-	VMOVH	W12, (R24)     // 7800c325
-	VMOVH	W8, 110(R19)   // 78379a25
-	VMOVH	W3, -70(R12)   // 7bdd60e5
-	VMOVW	W31, (R3)      // 78001fe6
-	VMOVW	W16, 64(R20)   // 7810a426
-	VMOVW	W24, -104(R17) // 7be68e26
-	VMOVD	W2, (R3)       // 780018a7
-	VMOVD	W19, 128(R23)  // 7810bce7
-	VMOVD	W0, -256(R31)  // 7be0f827
 	RET
 
 // END

src/cmd/dist/build.go

@@ -1743,6 +1743,7 @@ var cgoEnabled = map[string]bool{
 	"windows/arm64":   true,
 	"noos/thumb":      false,
 	"noos/riscv64":    false,
+	"noos/mips64":     false,
 }
 
 // List of platforms that are marked as broken ports.

src/cmd/internal/obj/mips/a.out.go

@@ -43,7 +43,6 @@ const (
 	NSYM   = 50
 	NREG   = 32 /* number of general registers */
 	NFREG  = 32 /* number of floating point registers */
-	NWREG  = 32 /* number of MSA registers */
 )
 
 const (
@@ -181,41 +180,6 @@ const (
 	REG_FCR30
 	REG_FCR31
 
-	// MSA registers
-	// The lower bits of W registers are alias to F registers
-	REG_W0 // must be a multiple of 32
-	REG_W1
-	REG_W2
-	REG_W3
-	REG_W4
-	REG_W5
-	REG_W6
-	REG_W7
-	REG_W8
-	REG_W9
-	REG_W10
-	REG_W11
-	REG_W12
-	REG_W13
-	REG_W14
-	REG_W15
-	REG_W16
-	REG_W17
-	REG_W18
-	REG_W19
-	REG_W20
-	REG_W21
-	REG_W22
-	REG_W23
-	REG_W24
-	REG_W25
-	REG_W26
-	REG_W27
-	REG_W28
-	REG_W29
-	REG_W30
-	REG_W31
-
 	REG_HI
 	REG_LO
 
@@ -253,8 +217,6 @@ func init() {
 	f(REG_F0, REG_F31, 32) // For 32-bit MIPS, compiler only uses even numbered registers --  see cmd/compile/internal/ssa/gen/MIPSOps.go
 	MIPSDWARFRegisters[REG_HI] = 64
 	MIPSDWARFRegisters[REG_LO] = 65
-	// The lower bits of W registers are alias to F registers
-	f(REG_W0, REG_W31, 32)
 }
 
 const (
@@ -281,7 +243,6 @@ const (
 	C_FREG
 	C_FCREG
 	C_MREG /* special processor register */
-	C_WREG /* MSA registers */
 	C_HI
 	C_LO
 	C_ZCON
@@ -394,8 +355,6 @@ const (
 	AROTRV
 	ASC
 	ASCV
-	ASEB
-	ASEH
 	ASGT
 	ASGTU
 	ASLL
@@ -417,7 +376,6 @@ const (
 	ATLBWR
 	ATNE
 	AWORD
-	AWSBH
 	AXOR
 
 	/* 64-bit */
@@ -437,8 +395,6 @@ const (
 	AADDVU
 	ASUBV
 	ASUBVU
-	ADSBH
-	ADSHD
 
 	/* 64-bit FP */
 	ATRUNCFV
@@ -451,12 +407,6 @@ const (
 	AMOVVF
 	AMOVVD
 
-	/* MSA */
-	AVMOVB
-	AVMOVH
-	AVMOVW
-	AVMOVD
-
 	ALAST
 
 	// aliases
@@ -482,7 +432,4 @@ func init() {
 	if REG_FCR0%32 != 0 {
 		panic("REG_FCR0 is not a multiple of 32")
 	}
-	if REG_W0%32 != 0 {
-		panic("REG_W0 is not a multiple of 32")
-	}
 }

src/cmd/internal/obj/mips/anames0.go

@@ -10,7 +10,6 @@ var cnames0 = []string{
 	"FREG",
 	"FCREG",
 	"MREG",
-	"WREG",
 	"HI",
 	"LO",
 	"ZCON",