Dynamic Pipeline States

[davll]

There are several render states outside PSOs in Vulkan:

• set_line_width
• set_depth_bounds
• set_depth_bias
• set_stencil_compare_mask
• set_stencil_write_mask

However, the above states are inside PSOs in DX12, so it needs discussion to find out a mechanism to emulate dynamic states in DX12 backend.

References:

• Pipeline states investigation
• d3d11's render state cache in ANGLE project
• DX12 Pipeline State Cache Example

[kvark]

Note that stencil read/write masks are required for Dota to work, adding a blocker tag.

[grovesNL]

@kvark I can grab the read/write masks for Metal, most of the work is already in place from my last PR

[kvark]

thanks @grovesNL , that would be great!

[kvark]

Pretty sure these are addressed now.