sycl-rel_5_2_0: [CUDA][LIBCLC] Implement RC11 seq_cst for PTX6.0 (#12516) #13403
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intel#12983) … info pre-commit PR for oneapi-src/unified-runtime#1429 --------- Signed-off-by: Neil R. Spruit <[email protected]> Co-authored-by: Kenneth Benzie (Benie) <[email protected]>
Implement `seq_cst` RC11/ptx6.0 memory consistency for CUDA backend. See https://dl.acm.org/doi/pdf/10.1145/3297858.3304043 and https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#memory-consistency-model for full details. Requires sm_70 or above. With this PR there is now a complete mapping between SYCL memory consistency model capabilities and the official CUDA model, fully exploiting CUDA capabilities when possible on supported arches. This makes the SYCL-CTS atomic_ref tests fully pass for sm_70 on the cuda backend. Fixes intel#11208 Depends on intel#12907 --------- Signed-off-by: JackAKirk <[email protected]>
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Cherry-pick for sycl-rel_5_2_0 depends on #13401
Implement
seq_cstRC11/ptx6.0 memory consistency for CUDA backend.See https://dl.acm.org/doi/pdf/10.1145/3297858.3304043 and
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#memory-consistency-model
for full details. Requires sm_70 or above. With this PR there is now a
complete mapping between SYCL memory consistency model capabilities and
the official CUDA model, fully exploiting CUDA capabilities when
possible on supported arches.
This makes the SYCL-CTS atomic_ref tests fully pass for sm_70 on the
cuda backend.
Fixes #11208
Depends on #12907
Signed-off-by: JackAKirk [email protected]