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[SYCL][E2E] Reenable in_order_profiling_queue for L0 #14328

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steffenlarsen
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Due to some confusion about the output from the in_order_profiling_queue test on L0, the test was disabled. However, the test can be safely reenabled for that target, while keeping it disabled for FPGA.

Additionally, the failure in profiling_queue is believed to be due to the same issue, so the JIRA has been added to it and the note in in_order_profiling_queue has been updated to reflect the known information about the failure.

Due to some confusion about the output from the in_order_profiling_queue
test on L0, the test was disabled. However, the test can be safely
reenabled for that target, while keeping it disabled for FPGA.

Additionally, the failure in profiling_queue is believed to be due to
the same issue, so the JIRA has been added to it and the note in
in_order_profiling_queue has been updated to reflect the known
information about the failure.

Signed-off-by: Larsen, Steffen <[email protected]>
@steffenlarsen steffenlarsen requested a review from sarnex June 27, 2024 14:16
@steffenlarsen steffenlarsen requested a review from a team as a code owner June 27, 2024 14:16
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@sarnex sarnex left a comment

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Thanks again, sorry for the noise.

@steffenlarsen steffenlarsen merged commit d5eb1e5 into intel:sycl Jun 28, 2024
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3 participants